types of asics introduction to vhdl gate arraysdesign entry • traditionally performed with...
TRANSCRIPT
Introduction to VHDL
• What is an ASIC?
• What is an FPGA?
• ASIC (and FPGA) Design Flow
• VHDL
What’s an ASIC?
• Application Specific Integrated Circuit» “Specialized circuits block or entire chip which are designed specifically
for a given application”
Types of ASICs
Standard cellsHierarchical cells
Macro cellsGenerators:
memory/PLAdatapath components etc
Cell based
Mask programmableGate arrays
Field programmableAnti-fuse basedMemory based
Array based
Semi CustomFull Custom
Types of ASICs
Often FPGAs are not considered a type of ASIC
What’s an FPGA?
• Field Programmable Gate Array. But it is not an ”array of gates”
• Configurable Logic Blocks
• Programmable interconnect
• Input/output blocks are also configurable
Spartan IIe block diagram
Spartan-IIE Slice – two slices in one CLB Abstraction levels – Y-chart
System synthesis
Behavioral synthesis
Logic synthesis
Circuit synthesis
Processors, Memories
Registers, ALUs, MUXs
Gates, flip-flops
Transistors
Structural viewBehavioral view
System Level
RT Level
Logic Level
Geometric Level
Transistor layouts
Cells
Chips
Boards, MCMs
Physical view
Definition of Register Transfer Level
• Inputs and outputs are defined
• Architecture (and of course function) of circuit is defined
• Placing of memory elements (flip-flops etc) are known
Example of RTL model in schematic form
D Q
CompareA<B
1
0
D Q1
0
1
00
1
1
0
CompareB=0
1
0A[7:0]
Reset_n
B[7:0]
Load
Y[7:0]
Done
Clock
Text book definition of Synthesis
• Logic Synthesis» Translates and minimizes Boolean functions into gates
• RTL Synthesis» Same as logic synthesis but also translates sequential language
constructions into gates and flip-flops
• Behavioural Synhtesis» Can reuse one one hardware component for more than one parallel
sequential language construction.
Problem – Definitions vary from author to author...
Design example – a hardware implementation of the GCD algorithm
• Find the Greatest Common Divisor for two unsigned chars (1 byte)
• Both flow chart and VHDL code below are behavioral descriptions. VHDL code is not synthesizable with RTL synthesis tool
processvariable A, B, Swap : integer range 0 to 255;
beginA := A_in;B := B_in;if (A /= 0 and B /= 0) thenwhile (B /= 0) loopwhile (A >= B) loopA := A-B;
end loop;Swap := A; A := B; B := Swap;
end loop;elseA := 0;
end if;Y <= A;
end process;
GCD algorithm RTL description• With RTL synthesis we have to write RTL VHDL code. This is what
we do in this course and this is what is most common in the industry.
• An RTL VHDL description can be written that infers the sequential structure below.
• Going from behavioral to RTL description is most often manual work
Hierarchical design representation
Top-down design methodologyvs
Bottom-up design methodology
ASIC design flow
• The requirements is the basis for the specification
• A behavioral model may be written in VHDL, C or some other high level language.
• A RTL model for the design is written in the design entry phase
Design Entry
FunctionalSimulation
Synthesis
Floorplanning
Place andRoute
ChipFabrication Testing
CircuitExtraction
Specification
Post Layoutsimulation
Static TimingAnalysis
Errors?
Errors?
Design entry
• Traditionally performed with schematic entry tools, but with increased complexity schematic entry is not feasible
• Hardware Description Languages (HDL) allows designer to model hardware using abstract programming. Two HDLs are dominant: VHDL and Verilog (both are standardized by IEEE)
• Mixed HDL and schematic entry tools
• Module generators. Generate multiplexers, memory, data path elements for the specific target technology
• IP cores, Intellectual Property. Synthesizable VHDL/Verilog model or netlist of complex cores. For instance PCI, processor core, etc
VHDL
• VHSIC (Very High Speed Integrated Circuits) Hardware Description Language
• Created by USA Department of Defense. Adopted as an IEEE standard in 1987. Latest standard is IEEE 1076 ‘93
• Intended for documenting and and modeling digital systems at different abstraction levels ranging from system level down to gate level
• Only a subset of the language is synthesizable, and that subset may differ from tool to tool
RTL functional simulation
• At this stage you have a HDL RTL model with no timing information (delays of combinational logic and nets are unknown). Only the function of the RTL model is verified
• The Unit Under Test (UUT) is instantiated in a HDL test bench and verified in a simulator
• The reference vector may come from a high level model
WAVEFORM GENERATION
COMPARE RESULTS
UNIT UNDER TEST
REFERENCE VECTORS
STIMULUS VECTORS OUTPUT VECTORS
TEST VECTOR
FILERESULTS
FILE
Optional Optional
HDL TESTBENCH
Synthesis
• Language synthesis. HDL code is compiled to known structural elements
• Optimization. Different algorithms are used to make your design as small and/or as fast as possible, depending on what you are optimizing for
• Technology mapping. The optimized structure is mapped to the target technology. The available components in the target technology is defined in a technology library
• The output is a netlist readable for the implementation tools
Floorplanning, placement and route
• Floorplanning. Arranges some or all of the blocks or cells in the design. Floorplanning is done manually by the aid of tools
• Placement. Decides the placement of all cells
• Route. Makes the connections between the cells
Add Mult
RAM
Floor plan
Mult
RAM
Add
Placement
Circuit extraction• The implemented design is converted to a HDL
description
• The delays of logic and interconnects are determinedStatic timing analysis
• Evaluates if timing constraints have been met
• Uses graph algorithms to evaluate delay through all paths Post layout simulation
• Simulates the implemented design using same test bench as in functional simulation
• Timing information is available. But for a fully synchronous design static timing analysis should cover all timing constraints
FPGA design flow - used in labs
Why do we use FPGAs in the course?- FPGA design is less complex than ASIC design -An FPGA can be configuredin fractions of a second- Initial costs are much less
More about implementation technologies in later lecture
VHDL testbenchVHDL RTLdescription RTL simulation
Structural VHDL
EDIF netlist
StructuralsimulationRTL synthesis
SDF timinginformation.
Structural VHDLTiming
simulation
Configurationdata
Place and route.Back annotation
Netlist withdelay
informationStatic timing
analysis
Simulationlibrary
Synthesislibrary
Simulationlibrary
Emacs -design entry
Synplify Pro
Xilinx ISE
Xilinx ISE
Cadence NC VHDL
Cadence NC VHDL
Introduction to VHDL
• VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
• Current standard is IEEE 1076-1993 (VHDL-93). Most tools support VHDL-93. Tools used in the lab support VHDL-93
• ADA like syntax, strictly typed language, concurrent
• Feature rich language for modeling digital systems at system level down to gate level.
• Only a subset of the language is supported for synthesis. Only RTL VHDL code is synthesizable with most tools
• The goal with this course is not that you should learn the complete language. You should learn how to write RTL VHDL code, but also some behavioral “stuff” for test benches
Main language concepts
• Concurrency» VHDL can describe activities that are happening in parallel
• Structure, hierarchy» VHDL allows to structure a design in a hierarchical manner
• Sequential statements» VHDL also allows sequential execution of statements. Just like any other
programming language
• Time» VHDL allows modeling of time
VHDL design units
• Entity declaration Specifies the interface of an entity
• Architecture bodyDescribes the function of an entity. An entity can have more than one architectures.
• Configuration declarationUsed to bind entity statements to particular architecture bodies.
• Package declarationUsed to store a set of common declarations such as components, types, procedures and functions
• Package bodyUsed to store the definition of functions and procedures declared in the package declaration
entity Ent1 isbeginend Ent1;
architectureA1 of Ex isbeginend A;
architecture A2 of Ex isbeginend A;
configurationCFG of Ent1 isend CFG;
package PKG isend PKG;
package bodyPKG isend PKG;architecture A3 of Ex is
beginend A3;
Common design data
VHDL is not case sensitive
• VHDL is not case sensitive – but do not MiX lOwEr CaSe aNd UpPer cAse
• In order to get your labs accepted your code must be commented, readable and idented. Ugly code will not be graded
• Use Emacs as it has an excellent VHDL mode
The entity declaration
• The entity specifies the interface of a design unit - component.
• May be seen as a “black box” description
A[3:0]
B[3:0]
Cin
Sum[3:0]
Cout
Adder
entity Adder isport
(A, B : in bit_vector(3 downto 0);Cin : in bit; -- Carry inS : out bit_vector(3 downto 0);Cout : out bit);
end Adder;Port signal name
Port signal name
Port modePort modeEntity nameEntity name
Signal typeSignal type
CommentComment
Port modes• Three most often used port modes
» in
» out
» inout
Entity
Port signal
DriverS
Driver
Note that an inout driver practically means that you
need to implement a 3-state buffer
Note that an inout driver practically means that you
need to implement a 3-state buffer
Entity
Port signal
DriverS
S
Port signal
Driver
Mode out with internal signal I assigned to port signal S.
Entity
Port signal
DriverS
Signal I can be read inside the entity
I
I
Mode out
Signal S cannot be read inside the entity
Mode in
Entity
Mode out
Signal can be read inside the entity
The architectureThe architecture defines the contents of the “black box”
entity Adder is
end Adder;
architecture Demo of Adder is
begin
end Demo;
Entity name
Architecturename
Portdeclarations
Architecturedeclarations
Architecturebody
Modeling styles – sequential
entity eqcomp4 isport(A, B : in bit_vector(3 downto 0);Equals : out bit);
end eqcomp4;
architecture seq1 of eqcomp4 isbeginprocess(A, B)beginif A = B thenEquals <= '1';
elseEquals <= '0';
end if;end process;
end seq1;
A=B
A
BEquals
Modeling styles – dataflow (set of concurrent statements)
architecture concurrent of eqcomp4 isbeginEquals <= '1' when (A = B) else '0';
end concurrent;
architecture concurrent_bool of eqcomp4 isbeginEquals <= not(A(0) xor B(0)) and
not(A(1) xor B(1)) andnot(A(2) xor B(2)) andnot(A(3) xor B(3));
end concurrent_bool;
Modeling styles - structuraluse work.gates.all; -- component declarations found in package gates
entity eqcomp4 isport(A, B : in bit_vector(3 downto 0);Equals : out bit);
end eqcomp4;
architecture structure of eqcomp4 issignal X : bit_vector(3 downto 0);
beginu0 : xnor2 port map(A => A(0), B => B(0), O => X(0));
u1 : xnor2 port map(A => A(1), B => B(1), O => X(1));
u2 : xnor2 port map(A => A(2), B => B(2), O => X(2));
u3 : xnor2 port map(A => A(3), B => B(3), O => X(3));
u4 : and4 port map(A => X(0), B => X(2), C => X(3), D => X(4), O => Equals);
end structure;
A simple example of a hierarchical/structural VHDL code
entity And2 isport (A, B : in bit;Y : out bit);
end And2;
architecture Gate of And2 isbeginY <= A and B;
end Gate;
entity Or2 isport (A, B : in bit;Y : out bit);
end Or2;
architecture Gate of Or2 isbeginY <= A or B;
end Gate;
File Or2.vhd File And2.vhd
We want to model the following and-or structure (Y = AB + CD)
First we create two VHDL files, containing the description of an OR-gate and an AND-gate. Name the files the same name as the name of the entity as it makes it easy to maintain the source code.
Example cont.Next we create a third file, the top-level in the hierarchy. In the top-level gate models are instantiated
The components are declared
The signal declarations create architecture internal signals
entity AndOr isport ( A, B, C, D : in bit;
Y : out bit);end AndOr;
architecture struct of AndOr is-- Component declarationscomponent Or2port ( A, B : in bit;
Y : out bit);end component;component And2port ( A, B : in bit;
Y : out bit);end component;signal A1, B1 : bit;
begin-- InstancesU1: And2 port map( A => A, B => B, Y => A1);
U2: And2 port map( A => C, B => D, Y => B1);
U3: Or2 port map( A => A1, B => B1, Y => Y);
end struct;
File AndOr.vhd
U2: And2 port map( A => C, B => D, Y => B1);
♦ Create an instance named U2 of entity And2♦ Connect input A of U2 to input C of AndOr ♦ Connect input B of U2 to input C of AndOr ♦ Connect output Y of U2 to internal signal B1
U3
U1
U2
AB
CD
Y
A1
B1AB Y
Example cont.A more compact way to instantiate entities is direct instantiation. With this approach there is no need for a component declaration (note that this is new for VHDL’93)
Syntax is similar to the previous instantiation, the keyword entity is added and the full name of the library path where the instantiated component can be found.
entity AndOr isport ( A, B, C, D : in bit;
Y : out bit);end AndOr;
architecture struct of AndOr issignal A1, B1 : bit;
begin-- Direct instantiationU1: entity work.And2(gate) port map( A => A, B => B, Y => A1);
U2: entity work.And2(gate)port map( A => C, B => D, Y => B1);
U3: entity work.And2(gate) port map( A => A1, B => B1, Y => Y);
end struct;
Modified file AndOr.vhd
U2: entity work.And2(gate)port map ( A => C, B => D, Y =>
B1);The library work is the current working library. gate is the architecture name.
U3
U1
U2
AB
CD
Y
A1
B1AB Y
Example cont.
But this is much simpler…
entity AndOr isport ( A, B, C, D : in bit;
Y : out bit);end AndOr;
architecture dataflow of AndOr isbegin
Y <= (A and B) or (C and D); end dataflow;
Open and constant ports
Remember an input must always have a driver even if it a constant.
Unused outputs may be left open if not used.
U1: entity work.Nisse(RTL) port map( A => ’1’,
B => B, Y1 => open, Y2 => Z );
1
B
1A
B
Y1
Y2 Z
Concurrent VHDL
• Variables are sequential objects, just like in any programming language
• Signals are concurrent objects (but may also be sequential)
• Signal assignment statement:
• Example with no delay
• Concurrent signal assignments may be labeled
<target_indentifier> <= <selected_expression>;
architecture RTL of NAND_gate isbeginy <= a nand b;
end NAND_gate;
architecture RTL of Labels isbeginLabel_1: y <= a or b;Label_2: x <= a and b;
end Labels;
Signal assignments and delays• Delayed signal assignment
• Defining several values in one signal assignment
• By the default delay are inertial, that is all spikes shorter than the delay are not propagated
• Transport delays propagate all pulses
• Reject can be used to define length of spikes to let through
y <= a nand b after 3 ns;
y <= ’1’, ’0’ after 20 ns, a after 30 ns;
y <= a transport after 5 ns;
y <= reject 3 ns inertial a after 5 ns;
Signal assignments and delays
b1 <= a after 10 ns;b2 <= transport a after 10 ns;b3 <= reject 4 ns inertial a after 10 ns;
a b
1 0
1 0
1 0
1 0
a
b1
b2
b3
Time (ns)0 10 20 30 40 50 60 70 80
Delays are not Synthesizable!
• Delays are only for simulation and makes no sense for synthesis
• Synthesis tools ignore delays
• The timing of a circuit can be estimated after synthesis
• The timing of a circuit can be verified after place and route
Concurrent statements• The architecture body contains concurrent statements - sequential
statements are not allowed in the architecture body• Order of concurrent statements are irrelevant
architecture RTL of ex isbeginA <= B;B <= C;
end RTL;
architecture RTL of ex isbeginB <= C;A <= B;
end RTL;
ABC
When statement - concurrent
signal_name <= value_a when condition_1 else,value_b when condition_2 else,value_c when condition_3 else,value_x;
Y <= a when (s = “00”) else,b when (s = “01”) else,c when (s = “10”) else,d;
abcd
Y
s
X <= a when en = ’1’ else ’Z’; Xa
en
Order of conditions matter!
High impedance in std_logic type
Whith statement - concurrent
abcd
Y
s
with s selectX <= a when en = ’1’
’Z’ when others;Xa
en
Order does not matter!
with s selectY <= a when ”00”,
b when ”01”,c when ”10”,d when others;
with selection_signal selectsignal_name <= value_a when value_1_of_selection_signal,
value_b when value_2_of_selection_signal,value_c when value_3_of_selection_signal,value_x when last_value_of_selection_signal;
last_value_of_selection_signal must be others if not all values are covered
The assert command
• The assert command enables checking of function and time constraints inside a VHDL model
• If the condition for an assert is not met during simulation a certain severityis sent to the simulator
• The message text will be echoed in the simulator console
• The simulator can be set to halt at desired severity level
• The assert keyword may be left out in sequential code
assert <condition>report <message>severity <error_level>; -- note, warning,
-- error or failure
if A = 0 thenreport ”A is zero”;<other sequential statements>
end if;
VHDL objects, classes and types
• An object is a named item that has a value of a specific type• There are four classes of object
» Constant – do not change valueconstant A : integer := 12; -- Constant declaration
» Variable – is updated immediately when assigned a new valuevariable A : integer; -- Variable declarationA := 21; -- Variable assignment
» Signal – is updated after a delta delay when assigned a new valuesignal A : integer; -- Signal declarationA <= 21; -- Signal assignment
» File – only used for simulationfile my_file : text open write_mode is "file5.dat";
• Type indicates what can be done with the object
Type declarations
• Type declarations may be put in the architecture declarative region• If own types are defined for ports they must be declared in a package
type <identifier> is <type_definition>;
package int_types istype byte is integer range 0 to 255;
end package;
use work.int_types.all;entity Adder is
port( A, B : in byte,S : out byte);
end entity;
Subtypes• Two integer type declarations
type year is range 0 to 2100;type day_of_month is range 1 to 31;
• We declare one variable of each typevariable today : day_of_month := 2; variable start_year : year;
• Then this is illegal eventhough 2 is a member of type todaystart_year := today;
• However this is OKtype year is range 0 to 2100;subtype day_of_month is year range 1 to 31;
variable today : day_of_month := 2; variable start_year : year;
start_year := today;A subtype is not a new type. It is a contraint of an existing type
VHDL predefined typestype Bit is ('0', '1'); type Bit_vector is array (Natural range <>) of Bit; type Boolean is (false, true); type Character is ( --256 characters-- ); subtype Delay_length is Time range 0 fs to Time'high; type File_open_kind is (read_mode, write_mode, append_mode); type File_open_status is (open_ok, status_error, name_error, mode_error); type Integer is range --usually typical integer-- ; subtype Natural is Integer range 0 to Integer'high; subtype Positive is Integer range 1 to Integer'high; type Real is range --usually double precision floating point-- ; type Severity_level is (note, warning, error, failure); type String is array (Positive range <>) of Character; type Time is range --implementation defined-- ; units fs; -- femtosecond
ps = 1000 fs; -- picosecond ns = 1000 ps; -- nanosecond us = 1000 ns; -- microsecond ms = 1000 us; -- millisecond sec = 1000 ms; -- second min = 60 sec; -- minute hr = 60 min; -- hour
end units;attribute Foreign : String ; impure function Now return Delay_length;
Boolean type
• Constants, signals and variables can be of boolean typearchitecture DummyCode of ex is
signal Done : boolean;constant DEBUG : boolean := true;
beginprocess(Done, ...)
variable DidIt : boolean; begin
if DEBUG then DidIt := true;
elseDidIt := Done;
end if;if DidIt then
...end if;
end process;end DummyCode;
The synthesizer maps boolean type: false ’0’, true ’1’
The signal and constant are visible inside the architecture
The variable is only visible inside the process. More about processes later
Integer type
• Size of integers are implementation defined – i.e. not defined in the language
• The majority of tools use 32 bits
• If you do not need 32 bits the range of the integer should be defined as it will limit the required hardware resources
signal Count : integer; -- Maps to 32 bitssignal Byte : integer range 0 to 255; -- Maps to 8 bits
Bit and bit_vector type
• The types are predefined as
• Shortcomings» Not possible to model tri-state» Not possible to have several drivers for the same signal» Not possible to assign unknown to a signal » Not possible to assign don’t care to a signal» Not possible to describe pull up or pull down» Not possible to describe that the signal is unitialized
type Bit is ('0', '1'); type Bit_vector is array (Natural range <>) of Bit;
UnconstrainedUnconstrained
The IEEE std_ulogic type
• Vendors of VHDL tools created their own ”bit” types which led to non-portable code
• Today all tools use the IEEE std_logic and std_ulogic types
• Std_ulogic is defined in the IEEE package std_logic_1164
• The ”u” in std_ulogic means that it is unresolved – a signal of type std_ulogic can only have one driver
type std_ulogic is ( 'U', -- Uninitialized'X', -- Forcing Unknown'0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance'W', -- Weak Unknown'L', -- Weak 0'H', -- Weak 1'-' -- Don't care );
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
The IEEE std_logic type
• The std_logic type is a resolved subtype of std_logic
• A resolution function determines values of signals with multiple drivers
Driver 1
Driver 2
'1'
'Z'
Resolution Function
'1'?
-- ----------------------------------------------------------- | U X 0 1 Z W L H - | | -- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |);
subtype std_logic is resolved std_ulogic;type std_logic_vector is array ( natural range <>) of std_logic;
std_ulogic compared to std_logic
library ieee;use ieee.std_logic_1164.all;entity ex is
port (A, B, A_en, B_en : in std_logic;Q : out std_logic);
end ex;
architecture RTL of ex isbegin
Q <= A when A_en = '1' else 'Z';Q <= B when B_en = '1' else 'Z';
end RTL;
library ieee;use ieee.std_logic_1164.all;entity ex is
port (A, B, A_en, B_en : in std_ulogic;Q : out std_ulogic);
end ex;
architecture RTL of ex isbegin
Q <= A when A_en = '1' else 'Z';Q <= B when B_en = '1' else 'Z';
end RTL;
Error!
q_1
q_2
Q
B_en
A_en
B
A
Enumeration types
• Boolean, bit, and std_logic are examples of enumerated types
• Very useful for state machinestype state is (Idle, Enabled, Stopped);
• The values of the enumerated type must be either identifiers (as the above) or character literalstype tri_bit is (’Z’, ’0’ ,’1’);
Arrays• Array declaration
type <identitifier> is array <discrete_range, ...> of<element_type>;
• Examplestype std_logic_vector is array (natural range <>) of std_logic;type rom is array (15 downto 0) of std_logic_vector(7 downto 0);
• ”Vectors” in VHDL are arrays. Typically we use vectors to represent a group of bits that are related such as a data bus
• Big-endian examplesignal Data : std_logic_vector(0 to 7);
• Little-endian example signal Data : std_logic_vector(7 downto 0);
Assigning values to bit vectors• If we only have one bit we assign bit values as specified in the enumerated
type. Assuming that A and B is of type std_logic we can writeA <= ’1’; B <= ’Z’;
• As the bit_vector and std_logic_vector are enumation types consisting of character literals they are assigned string literalsA_vec <= ”10001000”;
• It is also possible to use the VHDL construct array aggregrate using positional associationA_vec <= (’1’, ’0’, ’0’, ’0’, ’1’, ’0’, ’0’, ’0’);
• Aggregate using named associationA_vec <= (7 => '1', 3 => '1', others => '0'); -- orA_vec <= (7 | 3 => '1', others => '0');
• It is also possible to use bit string literals of base binary, octal or hexadecimal
A_vec <= X"88"; B_vec <= B"10001000"; C_vec <= B"1000_1000";
Integer literals
• Several ways of writing the value 253
2#11111101#16#FD#8#375#
Slice of array and concatenation
• Examples
signal A : std_logic_vector(7 downto 0);signal B : std_logic_vector(7 downto 0);
...
A(7 downto 4) <= B(3 downto 0);A(3 downto 0) <= ’0’ & B(2) & B(1) & B(3);
Record data type• Example type declaration
• Object declaration
• Object assignments
type FloatType isrecordSign : std_logic;Mantissa : std_logic_vector(7 downto 0);Exponent : std_logic_vector(15 downto 0);
end record;
signal A : FloatType;
A.Sign <= ’0’;A.Mantissa <= ( 0 => ’1’, others => ’0’); A.Exponent <= ( others => ’1’);
Type conversions and qualifiers
• “Type conversion” may be used to change the type of an expression. Type conversions are allowed only between types that are “closely” related. Two types are closely related if and only if one of the following conditions hold: » A type is closely related to itself.
» Conversion between integer types and the floating-point types. Loss in precision may occur
» Two array types are closely related if and only if they have the same number of dimensions, the array element types are equal, and the corresponding index types are closely related.
• “Qualified expressions” may be used to explicitly identify the type of an expression. Such qualification is a "hint" to the compiler, informing it as to the desired interpretation of the expression being qualified. Hence, such qualification is legal only if the expression can be legally interpreted as a value of the qualifying type
• If the to above are not possible a type conversion function must be used
Type conversion examples
variable int : integer;variable float : real;variable a_vec : std_logic_vector(7 downto 0);variable b_vec : std_ulogic_vector(7 downto 0);...-- Legalint := integer(float); -- converting real to integerreal := integer(int); -- converting integer to reala_vec := std_ulogic_vector(b_vec); -- conv. std_logic_vector
-- to std_ulogic_vector
-- Illegalint := integer(a_vec); -- not closely relateda_vec := b_vec; -- not same type
QualifierA common use for qualified expressions is in disambiguating the meaning of strings and aggregates whose type can only be determined from context. For example, the textio package has write procedures for both strings and bit vectors, so the following example is ambiguous:
variable L: std.textio.line;...std.textio.write( L, "1001" );
The problem here is that the string "1001" can be interpreted either as a character string or as a bit vector. Since textio contains write procedures for both strings and bit vectors, the VHDL analyzer cannot determine which write procedure to call, so an error is generated.
The fix is simple: Use a qualified expression to disambiguate the string. Either of the following lines may be substituted for the ambiguous line above:
std.textio.write( L, string'("1001") );or
std.textio.write( L, bit_vector'("1001") );
Type conversion functions• Type conversion functions are found in packages.
• For instance, type conversion functions between std_logic_vector and bit_vector may be found in the std_logic_1164 package
• Quick reference sheet for standard packages are available at the course home page
library IEEE;use IEEE.std_logic_1164.all;...
signal S_vec : std_logic_vector(3 downto 0);signal B_vec : bit_vector(3 downto 0);
...
B_vec <= to_bitvector(S_vec);S_vec <= To_StdLogicVector(B_vec);
Classification of VHDL typestypes
scalar types
discrete types
floating point types
physical types
integer types
boolean
bit character
file_open_kind
file_open_status
severity_levelinteger
enumeration types
real time
access types
file types
composite types
array types
record types
unconstrained array types
constrained array types
bit vector
string
Scalar type attributes
T’left First (leftmost) value in TT’right Last (rightmost) value in TT’low Lowest value in TT’high Highest value in TT’ascending True if T is an ascending range, false otherwiseT’image(x) A string representing the value of xT’value(s) The value in T that is represented by s
type state is (Idle, Enabled, Stopped);state’left = Idlestate’right = Stoppedstate’low = Idlestate’high = Stoppedstate’ascending = truestate’image(Enabled) = ”Enabled”state’value(”Idle”) = Idle
Discrete and physical type attributes
T’pos(x) Position number of x in TT’val(n) Value in T at position nT’succ(x) Value in T at position one greater than that of xT’pred(x) Value in T at position one less than that of xT’leftof(x) Value in T at position one to the left of xT’rigthof(x) Value in T at position one to the rigth of x
type state is (Idle, Enabled, Stopped);state’pos(Idle) = 0state’val(1) = Enabledstate’succ(Enabled) = Idlestate’pred(Enabled) = Stoppedstate’leftof(Enabled) = Idlestate’rightof(Enabled) = Stopped
Array type and object attributes
A’left(n) Leftmost value in index of dimension nA’right(n) Rightmost value in index of dimension nA’low(n) Least value in index of dimension nA’high(n) Greatest value in index of dimension nA’ascending(n) True if index range of dimension n is ascending,
false otherwiseA’range(n) Index range of dimension nA’reverse_range(n) Index range of dimension n reversed in direction
and in bounds
variable V : std_logic_vector(7 downto 0);
V’range = 7 downto 0V’reverse_range = 0 to 7
Initial values
• At simulation time signals and variables are given their initial value defined by T’left. Hence the initial value of std_logic is ’U’
• It is possible to change the initial value when the signal or variable is declared
variable V : integer := 25;signal S : integer := 333;
• This can be useful for simulation, but it is NOT supported for synthesis
• Do NOT use variable or signal initialization for models intended for synthesis!
Aliases• Aliases are intended to make a model clearer
• An alias is simply an alternate name for something
• May be used for data objects and other items that to not represent data in a model, such as functions, types and procedures
signal MIPS_Instruction : std_logic_vector(31 downto 0);alias OP_Code : std_logic_vector(5 downto 0) is MIPS_Instruction(31 downto 26);alias RS : std_logic_vector(4 downto 0) is MIPS_Instruction(25 downto 21);alias RT : std_logic_vector(4 downto 0) is MIPS_Instruction(20 downto 16);alias RD : std_logic_vector(4 downto 0) is MIPS_Instruction(15 downto 11);
Relational operations
Greater than>=
Less than or equal<=
Greater than>
Less than<
Not equal/=
Equal=
OperationOperator
Any type except file and protected type
Scalar type or 1-D array of any discrete type
Only objects of same type may be compared
Logic operations
• AND, NAND, OR, NOR, XOR, XNOR and NOT is predefined for types boolean, bit, and 1-D arrays of bit and boolean
• Same operators are defined for std_logic and std_logic_vector in the std_logic_1164 package
library IEEE;use IEEE.std_logic_1164.all;...
signal A_vec : std_logic_vector(3 downto 0);signal B_vec : std_logic_vector(3 downto 0);
...
B_vec <= (A_vec and ”1010”) or ”0100”;
Arithmetic operations
• Note that arithmetic operations for std_logic_vector is NOT defined in the package std_logic_1164
• Initially tool vendors created their own arithmetic packages.
• Synopsys put their packages std_logic_arith, std_logic_unsigned and std_logic_signed in the IEEE library – but those packages are NOT IEEE standards
• Instead you should use the IEEE package numeric_std
• The text book we have is a bit outdated as it uses the Synopsys packages – but you should not!
Remainderrem
Modulusmod
Exponentiation**
Absolute valueabs
Division/
Multiplication*
Subtraction-
Addition+
OperationOperator
Example use of numeric_std
variable A : signed(7 downto 0);variable C : std_logic_vector(7 downto 0);
...A := A + 1;C <= std_logic_vector(A);
A := A + signed(C);
• Both unsigned and signed are defined in numeric_std
type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC;type SIGNED is array ( NATURAL range <> ) of STD_LOGIC;
• Aritmetic operators are overloaded with integers
Example use of numeric_std
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity Add isport (A, B : in unsigned(7 downto 0);Cin : in std_logic;S : out unsigned(7 downto 0);Cout : out std_logic);
end Add;
architecture RTL of Add issignal Sum : unsigned(8 downto 0);
beginSum <= ('0'&A) + B + (""&Cin);S <= Sum(7 downto 0);Cout <= Sum(8);
end RTL;
Addition of std_logic not supported so we
create a vector of zerolength
Addition of std_logic not supported so we
create a vector of zerolength
One operand is padded with a ’0’ in
order to get the carry out
One operand is padded with a ’0’ in
order to get the carry out
Shift and rotate operations
Shift right arithmeticsra
Shift left arithmeticsla
Rotate rightror
Rotate leftrol
Shift right logical srl
Shift left logical sll
OperationOperator•Left operand is a 1D array of bit or boolean
•Shift operations for std_logic_vector type is not defined in std_logic_1164
•Use numeric_std package instead. Need to convert to unsigned or signed
Operator precedence
1. **, abs, not
2. *, /, mod, rem
3. +, - (identity and negation)
4. +, -, &
5. sll, srl, sla, sra, rol, ror
6. =, /=, <, <=, >, >=
7. and, nand, or, nor, xor, xnor
Most binding
Least binding
Use parentheses to alter order, or for clarity
Concurrent and sequential VHDL
• In VHDL it is important to understand the difference between sequential and concurrent execution
• Different VHDL statement are concurrent while others are sequential
• Some statements, such as signal assignments, can be both sequential and concurrent depending on where they are used
• Sequential statements are only allowed in» Processes» Procedures» Functions
Concurrent statementsThe architecture body contains concurrent statements. Sequential statements are not allowed in the architecture body.
Y
X
B
A
entity Test isport (
A, B : in bit;X, Y : out bit);
end Test;
architecture Concurrent of Test isbeginX <= A xor B;
with A select Y <= B when ’1’,’Z’ when ’0’,’-’ when others;
end Concurrent;
Two concurrent statements order is unimportant
The process• A process itself is a concurrent statement but the code inside the
process is executed sequentially
0
1
Y
X
BA
Sensitivity listProcess is activated whenever an event occurs on signal A or B
Process label(optional)
Statements in the process body are executed sequentially!
Process declarativeregion
Process body
-- signal declarations not allowed
entity Test isport (
A, B : in bit;X, Y : out bit);
end Test;
architecture Proc of Test isbegin
P1: process (A, B)
beginif A = ’1’ and B = ’0’ then
X <= A;Y <= ’1’;
elseX <= B;Y <= ’0’;
end if;end process P1;
end Proc;
Sensitivity lists
For a process that models combinational logic, the sensitivity list must be complete! All signals that are read (“inputs” to the process) must be in the sensitivity list.
What does this process model?
process(A)beginY <= A or B or C or D;
end process;
Our synthesis tool Synplify will assume that the sensitivity list is complete. The function of the synthesized logic will not match the function of the VHDL model you simulated.
Process execution and suspension• A process is executed with its initial conditions until it reaches a
wait statement. • In the wait statement the process suspends and updates signals that
has been assigned new values.• In the code below, the process resumes whenever there is an event
on either A or B
• This form of process is so common that there exist a shorthand notation
P1 : processbegin
Y1 <= A or B;Y2 <= A and B;wait on A, B;
end process P1;
P1 : process(A, B)begin
Y1 <= A or B;Y2 <= A and B;
end process P1;
”We” always use the shorthand
notation!
”We” always use the shorthand
notation!
Multiple processes interact concurrently0
1
0
1
Y
X
BA
Process 1 Process 2
Each process execute its statements sequentially. Each process execute when there is an event on one of the signals on its sensitivity list. This may cause an event on another signal that triggers another process… and another…
entity Test isport
( A, B : in bit;X, Y : out bit);
end Test;
architecture Proc of Test issignal Internal : bit;
beginP1 : process (A, B)begin
if A = '1' and B = '0' thenX <= A; Internal <= '0';
elseX <= B; Internal <= '1';
end if;end process P1;
P2 : process (A, B, Internal)begin
if Internal = '1' thenY <= A;
elseY <= B;
end if;end process P2;
end Proc;
The process itself is a concurrent statement
Two equivalent descriptions
architecture RTL of Nisse isbeginP1 : process (A, B)begin
S <= A xor B;end process P1;
end RTL;
architecture RTL of Nisse isbegin
P1 : S <= A xor B;end RTL;
You may (should) label processes, CSAs (concurrent signal assignments) etc. Useful for debugging and understanding tool outputs.
Concurrent vs. sequential execution
A signal that is assigned to within a process is not updated until the process is suspended. The two architectures are not equivalent.
?
A
B
C
D
Y C
DY
Resolution function
Synplify will report errors!Multiple non-tristate drivers for net Y
The signal is updated with the lastvalue assigned to it
architecture Concurrent of Test isbeginY <= A or B;Y <= C and D;
end Concurrent;
architecture Sequential of Test isbegin
process (A, B, C, D)beginY <= A or B;Y <= C and D;
end process ; end Sequential;
Signals
Holds a list of values, which include the current value, past value and a set of possible scheduled values that are to appear on thesignal. Future values can be assigned to the signal using the signal assignment operator.
signal shiftReg : std_logic_vector(7 downto 0);
shiftreg <= shiftreg(6 downto 0) & Input;
May be assigned initial values when declared:
signal Count : std_logic_vector(3 downto 0) := “0101”;
But this is not meaningful for synthesis!
Signals can represent wires and memory holders (flip-flops, latches).
Signal attributes
S’delayed(T) A signal that takes the same value as S but is delayed by time T
S’stable(T) A Boolean signal that is true if there has been no event on S in the time interval T up to current time, otherwise false
S’quiet(T) A Boolean signal that is true if there has been no transaction on S in the time interval T up to current time, otherwise false
S’transaction A signal of type bit that changes value from ’0’ to ’1’ or vice versa if there is an transaction on S
S’event True if there is an event on signal S in the current simulation cycle otherwise false
S’active True if there is a transaction on signal S in the currentsimulation cycle otherwise false
S’last_event The time interval since the last event on SS’last_active The time interval since the last transaction on SS’last_value The value of S just before the last event on S
Internal signals
Internal signals can be declared in the declarative region of the architecture
Int Y
X
BA
entity Test isport (
A, B : in bit;X, Y : out bit);
end Test;architecture Internal of Test issignal Int : bit;
beginInt <= A xor B;
X <= not Int ;
Y <= Int and A;
end Internal;
Signaldeclaration
Internal signal can be read and beassigned new values.
X and Y is not readable!
Delta time• Delta delays are used to order, queue, events
• Delta delays have no equivalent in real time» Simulation time may be 100 ns + 1 delta, 100 ns + 2 delta
• Delta time is orthogonal to simulation time
• Advance in time when no more processes are scheduled to execute in current simultation time
Delta
Time
SignalUpdate
ProcessExecution
Simulation delta cycle
Simulation - an example
0 +0 0 0 0 0 U U U 0 +1 0 0 0 0 0 0 U0 +2 0 0 0 0 0 0 05 +0 0 1 0 1 0 0 05 +1 0 1 0 1 1 1 0 5 +2 0 1 0 1 1 1 110 +0 1 1 1 1 1 1 1 10 +1 1 1 1 1 0 0 1 10 +2 1 1 1 1 0 0 0
t (ns) ∆ A B C D S1 S2 Y
AB
CD
Y
S1
S2
A'0''0' 5ns
B'0''1' 5ns
C'0''0' 5ns
D'0''1' 5ns
'1' 10ns
'1' 10ns
0
architecture sim of Test issignal A, B, C, D : std_logic := ’ ’;signal S1, S2, Y : std_logic;
begin
A <= ’0’ after 5 ns, ’1’ after 10 ns;B <= ’1’ after 5 ns;C <= ’0’ after 5 ns, ’1’ after 10 ns;D <= ’1’ after 5 ns;
S1 <= A xor B;S2 <= C xor D;Y <= S1 and S2;
end Sim;
Combinational feedback loops
In a synchronous design combinational feedback loops “must” be avoided. (There are some rare exceptions though.)
AS
Assume S = 0 and A = 1.What will happen in simulation?
Simulation will never advancein time!
S <= S xor A;
VariablesA variable is locally declared in a process or subprograms and can only be used locally. Variables are more abstract compared to signals. Variable assignments are immediately and not scheduled.
variable ShiftReg : std_logic_vector(7 downto 0);
shíftreg := shiftreg(6 downto 0) & Input;
Use variable whenever possible since a variable uses less simulation resources than a signal. Variables do not have histories.
Variables in processes
Variabledeclaration
A variable is declared inside the process and is not visible outside the process. A variable is updated immediately. Retains its value through the simulation
Y
D
C
BA
architecture Var of Test isbeginprocess(A, B, C, D)variable Temp : std_logic;
begintemp := '0';temp := temp xor A;temp := temp xor B;temp := temp xor C;temp := temp xor D;Y <= temp;
end process;end Var;