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U H M E P •01/08/2010 •Ed Hungerford - University of Houston •1 Perspectives on an Electron Tracker for e Conversion The MECO Experience Ed Hungerford University of Houston

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Page 1: U H M E P 01/08/2010Ed Hungerford - University of Houston 1 Perspectives on an Electron Tracker for  e Conversion The MECO Experience Ed Hungerford University

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Perspectives on an Electron Tracker for e Conversion

TheMECO Experience

Ed HungerfordUniversity of Houston

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General Considerations

• ResolutionMinimal Detector Material – Thin, Low Z Vacuum EnvironmentSufficient position measurements

• Rates> 500 kHz single rates>>1000 ChannelsNeed both timing (~1-2ns) and analog information

• Dynamic RangeProtons 30-40 times Eloss for MIP electronsMaintain High MIP efficiencyPileup can be a problems in the tracker and calorimeter

• Low Power, Low foot print electronicsSignal Transmission to the DAQNoise and Cross Talk

• Redundancy (Redundancy, Redundancy)ambiguous hits, dead channels, noise, accidentals,ghost tracks

It’s not what you know that limits the result

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ProposedMECO Electron Tracker

– Two tracker geometry options

• “Longitudinal” geometry with ~3000 3m long straws oriented nearly coaxial with the DS and ~23000 capacitively coupled cathode strips for axial coordinate measurement

• “Transverse” geometry with ~13000 1m straws, oriented transverse to the axis of the DS, readout at both ends

– Two readout options

• Digitizing inside the DS cryostat

• Sending analog signals through the vacuum walls to digitize remotely

Longitudinal Tracker Transverse Tracker

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Longitudinal Straw Tracker Structure

Eight planes projecting radially outward from each vertex of the octagon (blue in the figure)30cm2~300cm

An octagonal array of eight detector planes (red in the right figure) 30cm~300cm

• Each plane is constructed with 3 layers of straw detectors

• Blue straws have conductive cathodes and orange straws have highly resistive cathodes .

• Inductively coupled readout strips on both sides ~5 mm wide

• The whole detector would have ~3000 anode wires and >19000 cathode strips.

• Both the amplitude and timing information are readout from each channel.

• The detector operates in a vacuum environment.

Construction of Straw Detector

Cross Section of L-Tracking Detector

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Transverse Straw TrackerStructure

Support Frame Open Space

Space for ElectronicsManifold

Straw Array Front

(60 straws)

Straw Array Back

(60 straws)

54 planes - 60° rotation with respect to neighbors

13,000 channels of TDC and ADC readout of the Anode wires

All straws conducting - 70 -130 cm length 5mm diameter - 15 (25)mm thickness

One (x,y) layer per frame – Hit Position Resolution ~150 m

3 spare planes

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Manifold

•05-30-09• Ed Hungerford

for the COMET collaboration

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Straw Tubes(Conducting)

ConstructionStraws composed of 2 over-wound

layers of 12 μm thick, 5000 Angstrom Cu

coated Kapton

5 mm - diameter 68 to 112 cm long

25 μm Au coated W – 5% Re Sense wire

17 um may be possible

Material warps by sputtering so must be annealed

(M-S Angle) 2 Contribution

Kapton => 16.5 (27.5) x 10-5

Gas (C4H10)=> 2.3 x 10-5

Cu layer => 4.4 x 10-5

Anode W => 450 x 10-5

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Straw Tubes (Resistive)

Simulated Induction Amplitude vs time

Resistivity of Cathode walls 0.5 M - 1.0 M per sq

Resolution of <1mm

Conductive strip needed to bleed charge from beam flash

Resistive straw composed of ~19m XC Kapton and [overwound by ~10 m H Kapton (how to ground?) or 2nd layer of XC]

Must have 3 internal supports for 3m wire

Alternative seamless straw - PEEK (1m)

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Straw DeflectionMeasurements

Tensioned by Weights

PressureSlide Clamps Ends

Horizontally

Deflection measured

By height from a precision table

The Straws Twist, Elongate, and

Expand under pressure

Plane Lay-up Fixture

Micrometer to measure expansion

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Longitudinal Tracker(Resistive Vane)

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Conductive Straws

Leak Rates andRadiation Exposure

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Straw Expansion under stress

Straw Creep (ΔL/L) -80 g

(7 days)

~ 1.6 x 10-4

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Parameters for W wires

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Wires Tensioned at 80 gNo intermediate supportAdd 3% Re to stabilize

Wire Tension

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HV vs collected charge57 % Ar/ 43% C2H6

HV ~2 kVFor operation

Background 0.5 fc gain 5 x 104

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Drift SimulationTransverse Tracker

•05-30-09•16

Gas – 80 %CF4/20% C6H10 Velocity - 8.5 cm/μsDrift Time - 45 ns

Trajectory

Wire

Trajectory

Wire

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Simulations

Simulated Anode

Preamp Signal

Simulated Charge

15 ns Filter

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Muon Capture Particle Yieldas a function of Z

p,2nx

p,n

p

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Simulated backgrounds

•05-30-09• Ed Hungerford

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Proton Neutron

Photon2 gamma, 2 neutrons,

0.1 proton per μ capture

<10 MeV - Thermal

>10 MeV Exp tail

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Readout Architecture(Internal Digitization)

• On-Detector amplification and digitizing – events passed by optical fiber in serial to DAQ (Parallel transfer also works)

• Electronics based on CMOS to conserve space and power (<50 mw/ch)

• Mounted on the detector frame

• This system has been prototyped and demonstrated in a proton beam

• Rad damage is not a problem

If analog signals were transmitted through the

vacuum wall then it requires a ribbon cable bundle

5 cm thick placed around the inner wall of the DS

cryostat and a power consumption of 150-200 mW/channel

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EXAMPLE

• The readout electronics works for either tracker

• The system is based on CMOS to conserve space and power

• Mounted on the detector frame

• The system has been prototyped and demonstrated

• Rad damage is not a problem

Readout Electronics WBS 1.3.4.3.7

Mounting for Transverse

Detector

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FEB Cabling for Signals and HV

Flex-ribbon cable

Through manifold to

FEB – Signals an HV

Fused HV

15 ns LRC

Filter/channel

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Front End Tests

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Front-end electronics design & test results• A front-end board was developed to

test the ASD-4 and a driver board is used to adapt the LVDS output to our lab CAMAC TDC.

• The Digitizing Board was completed. It used Elefant (Babar) but an updated version was needed and designed to the protype level

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Specifications of Preamp

Parameter Name Value Note

Polarity BipolarPositive input for

Colorimeter

Channel number 16Cover 8 cm with 5-

mm straws

Linear range <60 fC

Input capacitance 20 pF

Equivalent Noise Charge

0.5 fC

Peaking time 100 nsAmplitude

measurement

(250-ns signal width)

Coupling AC

Timing resolution <2 ns

Power consumption <5 mW/ch

Test input Yes

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Scheme of FE ASIC

•FE ASIC will have 8 channels. One of the channels is shown above.• Input signal is amplified by a preamplifier;• After that, signal is split into two arms;• One arm is amplified by a slow shaper (100-ns peaking time) for amplitude

measurement;• The other arm is amplified by a fast shaper (10-ns peaking time);• The discriminator circuit is to compare the input signal with a trimmed

threshold. The result is converted to an analog signal that is proportional to the interval between the system clock and the discriminator output.

ASIC

PreAmp

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On-Detector PipelinedDigitizer

• Digitizer ASIC Design WBS 1.3.4.3.7.2 based on the ELEFANT ASIC used in BABAR (8 channels/ASIC)

Work done in collaboration with design engineers at LBL

Rescale ASIC to 0.25 m technology and 3.2 V interfaces

Solves identified problems with the ELEFANT design

Change clock frequency (20-60 Mhz)

Change from waveform sampling to time-slice integration

Increase ADC bits to 10

• ~5 s Latency, self or external triggered

• 18 serial, 20 Mb/s optic data lines through the vacuum

• Power Consumption 65 mW/channel (Power 1,650 W)

Design (LBL Engineer) $518K; Fabrication (2prototypes) 2 x $45k;

Preproduction samples $50k; Production and packaging $231k, Testing $42k

=> $931k + 37% contingency

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Scheme of Analog Buffer ASIC

• This ASIC follows the FE ASICs and provides analog buffers to temporally store the signals. The buffer length is latency of trigger signal from the colorimeter.

• Peak Detector Array has peak detection circuits for each channel. It generates peak-found signal to latch the amplitude and timing information of that channel to the analog memory.

• The Pipiline Control and Sparsification Readout Logic• Controls the write/read sequence of the buffers• Provides zero-compression readout logic

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Beam Test

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Summary of electronic development

• A front-end board was developed to test the ASD-4 and a driver board is used to adapt the LVDS output to our lab CAMAC TDC.

Elefant Chips (2 x 8 channels)

Mother Board with FPGA

Memory and PCI controller

Digitizing Boards

Input 16 channels

• The Digitizing Board layout is completed. Backplane designed with FPGA , buffers, and PCI driver completed. System tested for rate and efficiency

FEB Board

• A replacement for ELEFANT was designed to the prototype level

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Newcomer, et al Front End for ATLAS Straws

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Tracker Cost Profile

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