u niversity of s cience and t echnology of c hina design for distributed scheme of wcda readout...

University of Science and Technology of China

Design for Distributed Scheme of WCDA Readout

ElectronicsCAO Zhe


Feb 18, 2011

12011/02/18


Outline

• Architectural of distributed scheme

• Detail describe of principle

• Prototype modules for verification

• Electronics for prototype detector

22011/02/18


Distributed Scheme for LHAASO

• 1 FEE for 9 PMTs• 100 FEEs in 1 array

30PMT

30PMT FEE

Off -shore On-shore

On-shore electronics

Off -shore electronics

~100m~15m

Clk/cmd/trigger

Data/state/hi t

Analog domain Digi t domain

32011/02/18


Architecture: Distributed vs. Lumped

• Digitalization on the frontend boards

• Only digital signals are required to transmitted over the long distance

• Ethernet, flat cable, or optical fiber can do the work

• The clock distribution will be critical in this architecture

• All the digitalization must be carried with the common precise clock

• Trigger decision will be another issue

42011/02/18


Architectural of the distributed scheme

• Off-shore part• FEE• PMT readout• Hits collection

• On-shore part• Trigger: trigger form

and distribution• Clock: Common clock

distribution• Data processing: digit

data collection and clock distribution

Clock module

Trigger module

FEEFEE

Data processing

modules

FEEFEEFEEs

Hi tTrigger

ControlData

OnshoreOff shore

Clock

Clock

Clock

VME Crate

52011/02/18


Design principle • Clock distribution

• Serializer/Deserializer• electro-optical/optical-electro

• FPGA-based TDC• Coarse counter + fine counter• High frequency clock phase shift

• Transmission delay calibration• Echo-based calibration

• PMT readout• QTC• FPGA-based TDC

62011/02/18


Clock distribution• Offshore has the same frequency and fixed phase with onshore• Onshore:

• Clock and data combined in the SerDes• Bit stream sent to the offshore by optical transmitter

• Offshore:• After long fiber, bit stream received by optical receiver• Clock and data decoded in the SerDes• Parallel data sent to FPGA as command or config• Recovered clock as system clock after cleaned jitter by PLL

SerDes

System clock

OpticalTransmitter

OpticalReceiverSerDes

System clockOff -shore On-shore

Paral lel data Paral lel dataTo FPGA From FPGA

PLL

Recovered CLK

72011/02/18


FPGA-based TDC• Implemented in FPGA (Virtex4-10)• Coarse counter: 40MHz system clock• Fine counter: 400MHz divided into 4 phases, equals to

1.6GHz• LSB=625ps• Dynamic range=no limited

CLK 0

CLK π

High speed CLK

400MHz

1.6GHz

2.5ns

625ps

CLK π /2

CLK 3π /2

82011/02/18


Transmission delay calibration

• Echo-based calibration• Time recorded by FPGA-based TDC

in Onshore• ΔTdown = ΔTup= (T3 - T0 – ΔTs) / 2

T0

CLK

Cal ibration

MP

Echo

T1 T2 T3

TDC

Δ Tdown Δ Ts Δ Tup

TDC

SP

Cal ibration

Echo

CLK

92011/02/18


Digitalization in Distributed Architecture

• Time over threshold scheme with linear charge-to-time conversion

• CLC101EF, designed for Super-Kamiokande, covers our requirement• Input channel: 3• Dynamic range: 0.2~2500pC• Gains: 3/channel (1:7:49)

• 0.2~51pC,1~357pC,5~2500pC• Time resolution: 0.3ns• Charge resolution: 0.2pC

• 10 chips have been purchased for prototype design

102011/02/18


Detail of QTC

Block diagram of QTC Timing chart for QTC operation

In/Out signals of QTC

PMT data rate: 50kHz/channelQTC dead time: 900nsData loss: 0.968‰ (Poisson distribution)

112011/02/18


Prototype design• MasterPrototype (MP)

• Onshore function: clock, trigger, data processing• Clock distribution• Data transmission• TDC based transmission delay calibration• VME module

• SlaverPrototype (SP) • Offshore function: FEE• Clock distribution• Data transmission• PMT charge measurement• PMT arrival time measurement• USB module (test only)

• Version 1.0• Clock distribution and TDC verification

• Version 2.0• Readout electronics for prototype detector array

122011/02/18


Schematic of Version 1.0

MasterPrototype (MP) SlaverPrototype (SP)

FPGA CPLD

CLKFANOUT

Transceiver

OscPLLCLKIN

VME

Bus

SerDesGroup1

Transceiver

Transceiver

Transceiver

SerDesGroup2

SerDesGroup3

SerDesGroup4

SerDesGroup1

FPGA

CLKFANOUT

Transceiver

OscPLL

CY7C68013 USB

SerDesGroup2

Transceiver

SerDesGroup3

Transceiver

SerDesGroup4

Transceiver

Group Serializer Deserializer

1 SN65LVDS1023A SN65LVDS1224B

2 DS92LV16 DS92LV16

3 TLK1521 TLK1521

4 TLK1501 TLK1501

132011/02/18


Evaluation boards of Version 1.0

MasterPrototype (MP)SlaverPrototype (SP)

142011/02/18


SPMP

Optical fiber

152011/02/18


Clock distribution test

EX380SerDesTransceiver

TransceiverSerDesPLLTo FPGA

To SerDes

For test

MP

WavePro715Zi

SP

162011/02/18


Clock distribution test

Group SerDes Cycle to cycle jitter/ ps Phase relationshipTransmission Recovery Jitter cleaned

1 SN65LVDS1023A/1224B 23.30 47.18 15.82 Uncertainty2 DS92LV16 23.24 18.80 16.78 Fixed3 TLK1521 23.36 21.69 16.89 Uncertainty4 TLK1501 23.33 28.92 16.50 Uncertainty

Test waveform in oscilloscopeBlue: Transmission clock in MPGreen: Recovered clock in SPRed: PLL output clock in SP

172011/02/18


TDC test• Spartan3A was used• High speed clock ≤ 200MHz• LSB=1.25ns• DNL: -0.0544~+0.0558 LSB• INL: -0.0037~+0.0800 LSB• Virtex4-10 will be used in next version

• High speed clock ≤ 400MHz• LSB=625ps

182011/02/18


Calibration test

• In different lengths of fibers• Resolution better than 1LSB

• Upgrade to 625ps in next version

192011/02/18


Version 2.0 for prototype detector array

MASTER1MFEE

GPS

VME

crea

t

Off shore On shore

Trigger/hi t9 channels

Data/clk

FEEData/ cl k

Tri gger/ hi t

202011/02/18


Sketch of Version 2.0

• Q & T measurement: Time of Threshold-based QTC and FPGA-based TDC

• PMT signal preamplifiers• QTC• Calibration circuit

• Clock distribution and data transmission: SerDes and fiber

• SerDes• PLL and clock fan out

• Others• Power• USB interface

FPGA

QTC

QTC

Analog buff er

Analog buff er

QTCAnalog buff er

SerDesTransceiver

SerDesTransceiver

PLL

68013POWER

• Upgrade to version 2• Virtex 4 instead of Spartan 3A• 4 fiber channels for extending more

FEEs • Clock: synthesize clock from Ru OSC,

distribute clock to FEE• Trigger: collect hits, form and distribute

trigger• data processing: collect digit result

212011/02/18


Progress

• FEE module under testing

• MP module under PCB layout

222011/02/18


THANK YOU!

232011/02/18

u niversity of s cience and t echnology of c hina design for distributed scheme of wcda readout...

Documents

u niversity of s cience

distribution clock

optical receiver clock

system clock fine counter

distributed architecture

poisson distribution

pc time resolution

fpga virtex4