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Electrostatic Discharge

Electrostatic Discharge (ESD) has become one of the most

critical reliability issues in integrated circuits (ICs).

Electrostatic discharge (ESD) is a charge re-balancing process

between two adjacent objects, which involves a rapid

discharge of accumulated static electricity.

The ESD is a major cause of failure during the manufacturing,

testing, handling and assembly of integrated circuits (ICs).

Human beings, wafer-processing equipment, testing and

automation equipment that come in contact with the ICs, can

generate the static charge responsible for the ESD events.

The phenomenon of ESD can often be observed in our daily

lives.

For example, static electricity can be generated due to the

friction between different materials, and the accumulated

electrostatic charge can spontaneously be transferred to the

object at lower potential; either through a direct contact or

through an induced electric field.

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ESD events usually give a mild shock to human beings.

However, if the same amount of ESD stress is injected into a

microelectronic component, it could be detrimental.

ESD events often involve high voltage (~ several kV) and high

current stress (1 - 10 A) on small electric devices.

Despite the fact that ESD events are of very short duration

(0.2 - 200 ns), the massive current / voltage pulses can give

fatal damage to integrated circuits (ICs).

Several examples of catastrophic ESD failures in the modern

ICs, are junction breakdown, molten metal/via effects and

the gate oxide damage.

ESD events can be observed in various environments: silicon

fabrication facilities, assembly and test sites, offices, home

etc.

Moreover, the various sources such as human beings,

machines, and other harsh environments can cause ESD

stress.

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Depending on the environment and the objects involved in

the ESD events, the characteristics of ESD stress can vary

considerably; the ESD failure mechanisms and signatures

accordingly have variations.

Proper ESD models can be of help in designing suitable

protection schemes and in the development of test

equipment which can effectively mimic the actual ESD events.

Technology scaling which leads to thinner gate oxides,

shallower junctions, higher doping densities, narrower

metal lines and vias, LDD, thin epi-substrates, shallow

trench isolation (STI), silicided contacts etc. has had negative

impact on ESD immunity.

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Introduction to ESD

What is ESD?

ESD - Electro-Static Discharge - is a charge balancing process

between two objects at different potential.

ESD is a transient discharge of static charge that arises from

either human handling or a machine contact.

Although ESD is the result of a static potential in a charged

object, the energy dissipated and damages made are mainly

due to the current flowing through ICs during discharge.

Most ESD damages are thermally initiated in the form of

device / interconnect burn-out or oxide break-down.

The basic phenomenon of ESD is that is a large amount of

heat is generated in a localized volume significantly faster

than it can be removed, leading to a temperature in excess of

the materials’ safe operating limits.

ESD Damages:

pn-junction may melt.

Gate oxide may have void formation.

Metal interconnects & Vias may melt or vaporization,

leading to shorts or opens.

Gate-oxide breakdown is another form of ESD damage.

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Why is ESD Critical?

The aggressive decrease in physical dimensions and increase

in doping in modern CMOS technology result in a significant

decrease in gate-oxide thickness and pn-junction width −→

Require less energy and lower voltages to destroy MOS

devices.

Figure 1: Scaling of gate oxide thickness of MOS transistors.

Figure 2: Scaling of junction depth of MOS transistors.

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Figure 3: Scaling of the breakdown voltage of gate oxide (Vox) and

the avalanche breakdown voltage (Vt1) of pn-junctions.

The level of ESD stress, however, does not scale down with

the technology.

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Principle Sources of ESD in ICs

Human Handling

A person walking on a synthetic floor can accumulated up to

20 kV.

This voltage is discharged when the person touches an object

that is sufficiently at ground.

Charge exchange occurs between the person and the object

in a very short time duration (10 ns - 100 ns).

The charging current is approximately 1A - 10A, depending

upon the time constant.

Test and Handling Systems

Equipment can accumulate static charge due to improper

grounding.

The charge is transmitted through ICs when it is picked up

for placement in test sockets.

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IC Itself is Charged During Transport / Contact With

Charged Objects

ICs remain charged until they come into contact with a

grounded surface (large metal plates /test sockets).

Charge is discharged through the pins of ICs.

Large currents in the internal interconnects can result in

high voltage inside the devices which can cause damage to

thin dielectrics and insulators.

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ESD Models

Human Body Model (HBM)

The HBM is a component level stress developed to simulate

the action of a human body discharging accumulated static

charge through a device to ground, and employs a series RC

network consisting of a 100pF capacitor and a 1500Ω resistor.

HBM models the ESD of a human body.

Peak current ≈ 1.3A, rise time ≈10-30ns.

Equivalent circuit of the human body model of ESD.

The switch closes upon an ESD event.

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Machine Model (MM)

MM models the ESD of manufacturing / testing equipment.

Peak current ≈ 3.7A, rise time ≈15-30ns, bandwidth ≈ 12 MHz.

Equivalent circuit of the machine model of ESD. The switch closes upon an ESD event.

ESD stress caused by charged machines is sever because of

zero body resistance.

Most ESD protection circuits can only protect HBM and MM.

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Charge Device Model (CDM)

CDM models the ESD of charged integrated circuits.

Inductance in the model is mainly due to the inductance of

bond wires.

Peak current ≈ 10A, rise time ≈1ns.

Gate oxide breakdown is the signature failure of CDM stress,

in contrast to the thermal failure signature of HBM and MM

stress.

CDM stress has the fastest transient and has the max. peak

current.

CDM stress is the most difficult ESD stress to protect against.

Equivalent circuit of charged device model of ESD.

The switch closes upon an ESD event.