uartproject.doc

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UART:

The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device

for data communication in the field of telecommunication. There are different versions of

UARTs in the industry. The UART block diagram is shown in below.

Figure.6 : Block diagram of bi-directional UART

1. High bit lossless data comparison

2. Behavior deriding of modeling block

3. Design the stimulitated

Some of them contain FIFOs for the receiver/transmitter data buffering and some of them have

the 9 Data bits mode (Start bit + 9 Data bits + Parity + Stop bits). This application note describes

a fully configurable UART optimized for and implemented in a variety of Lattice devices,


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FIGURE.7 .UART BIT CONFIGURATON

4.2.2 INTERNAL REGISTER

The UART contains two data buffering registers (RBR and THR), three status registers (IIR,

LSR, and MSR), and three control registers (IER, LCR, and MCR). These registers and their

addresses are shown below. The further discussions of the data buffering registers are in the

Transmitter and Receiver sections. Note that the programmable baud rate control register and the

user accessable Scratchpad register are not implemented in this design. For details, refer to the

Compatibility section.

4.2.2.1.LINE CONTROL REGISTER (LSR, Addr=101)

TABLE. 1 LSR

Bit7

Bit

6

Bit5

Bit4 Bit3 Bit 2 Bit1 Bit 0

0 TEMT THRE BI FE PE OE DR

DR: Receiver Data Ready

DR indicates status of RBR. It will be set to logic 1 when RBR data is valid and will be reset to

logic 0 when RBR is empty. When line errors (OE/PE/FE/BI) happen, DR will also be set to

logic 1 and RBR will be updated to reflect the Data bits portion of the frame. Pin RxRDYn is

actually a complement of this bit.

OE: Overrun Error
http://en.wikipedia.org/wiki/File:Charactercode.png


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This bit will be set when the next character is transferred into RBR before the previous RBR data

is read by the CPU. Even though DR will still be 1 when OE is set to logic 1, the previous frame

data stored in RBR which is not read by the CPU is trashed and cant be recovered.

PE: Parity Error

This bit will be set to logic 1 only when the Parity is enabled and the Parity bit is not at the logic

state it should be. For Even Parity, the Parity bit should be 1 if an odd number of 1s in the Data

bits is received, otherwise, the Parity bit should be 0. For Odd Parity, the Parity bit should be 1 if

an even number of 1s in the Data bits is received, otherwise, the Parity bit should be 0. For Stick

Parity '1', the Parity bit should be 1. For Stick Parity '0', the Parity bit should be 0.

FE: Framing Error

FE will be reset to logic 0 whenever SIN is sampled high at the center of the first Stop bit,

regardless of how many Stop bits the UART is configured to.

BI: Break Interrupt

BI will be set to logic 1 whenever SIN is low for longer than the whole frame (the time of Start

bit + Data bits+ Parity bit + Stop bits), not at the SIN rising edge where Break is negated. If SIN

is still low after BI is reset to logic 0 by reading LSR, BI will not be set to logic 1 again. Since

Break is also a Framing error, FE will also be set to 1 when BI is set.

THRE: THR Empty

THRE will be set to logic 1 whenever THR is empty which indicates that the transmitter is ready

to accept new data to transmit. Pin TxRDYn is actually a complement of this bit.

TEMT: Both THR and TSR are Empty

This bit will be set to logic 1 when THRE is set to 1 and the last Data bit in the TSR is shifted

out through SOUT. The four error flags (OE, PE, FE and BI) of LSR will be reset to logic 0 after

a LSR read.

4.2.2.2 MODEM Status Register (MSR, Addr=110)

TABLE.2. MSR


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Bit7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bit1 Bit 0

DCD RI DSR CTS DDCD

T

ERI

DD

SR DCTS

Bit 7:

DCD (Data Carrier Detect) is the complement of DCDn input

Bit 6:

RI (Ring Indicator) is the complement of RIn input

Bit 5:

DSR (Data Set Ready) is the complement of DSRn input

Bit 4:

CTS (Clear to Sent) is the complement of CTSn input

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 TEMT THRE BI FE PE OE DR

Bit 3:

DDCD (Delta DCD) indicates that the DCDn input has changed state

Bit 2:

TERI (Trailing Edge of RI) indicates that the RIn input has changed from a low to high state

Bit 1:

DDSR (Delta DSR) indicates that the DSRn has changed state since last time read by CPU

Bit 0:

DCTS (Delta CTS) indicates that the CTSn has changed state since last time read by CPU


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Whenever bit 0-3 is set to logic 1, a MODEM status interrupt is generated if the interrupt is

enabled. These four bits will be reset to logic 0 whenever CPU reads MSR.

4.3VHDL IMPLEMENTATION

The detail design of systems at the gate and flip-flop level has become time consuming as the

integrated circuit technology has become very complex . In recent years this fact has motivated

usage of hardware description language in the design process of digital system. VHDL is used to

describe and simulate the operation of variety of digital system which is ranging in complexity

from a few gates to an interconnection of many complex integrated circuits. Advantages of

VHDL implementation includes minimum cost and time, better design, faster time to market and

increased flexibility.

VHDL can be used for the behavioral level design implementation of a digital UART and it

offers several advantages.

THE ADVATAGES OF USING VHDL IMPLEMENTATION OF UART

VHDL allows us to describe the function of the transmitter in a more behavioral

manner, rather than focus on its actual implementation at the gate level.

VHDL makes the design implementation easier to read and understand, they also

provide the ability to easily describe dependencies between various processes that

usually occur in such complex event-driven systems.

It is easier to test the UART by the VHDL simulation and find out if any

discrepancy occurs.

4.4 PROPOSED UART ARCHITECTURE:


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FIGURE: 8 Simple UART

Figure 8 shows the block diagram of UART. This UART consist of three blocks Transmitter,

receiver and baurd generator. Serial data is transmitted via its serial port. A serial port is one of

the most universal parts of a computer. It is a connector where serial line is attached and

connected to peripheral devices such as mouse, modem, printer and even to another computer. In

contrast to parallel communication, these peripheral devices communicate using a serial bit

stream protocol (where data is sent one bit at a time). The serial port is usually connected to

UART, an integrated circuit which handles the conversion between serial and parallel data.


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FIGURE 9 Serial Data Transmission and Receive

Fig. 9 shows how the UART receives a byte of parallel data and converts it to a sequence of

voltage to represent 0s and 1s on a single wire (serial). To transfer data on a telephone line, the

data must be converted from 0s and 1s to audio tones or sounds (the audio tones are sinusoidal

shaped signals). This conversion is performed by a peripheral device called a modem

(modulator/demodulator). The modem takes the signal on the single wire and converts it tosounds. At the other end, the modem converts the sound back to voltages, and another UART

converts the stream of 0s and 1s back to bytes of parallel data.

In this project, we present UART which includes three modules which are the Line control

register, baud rate generator, transmitter and receiver. The proposed design of UART satisfies

the system requirements of high integration, stabilization, low bit error rate, and low cost. It also

supports configurable baud rate generator and variable data length from 5-8 bits per frame.

.

START

BIT

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

STOP

BIT

START

BIT

DATA

FRAME


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Figure 10. Frame Format For UART

The UART architecture is given in the figure below :

FIGURE 11. UART Propose Architecture

Figure 11 shows the proposed UART architecture

VHDL implementation. The UART are capable of the following:


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a) Fully programmable serial interface characteristics:

i. 5-, 6-, 7-, or 8-bit characters

ii. Even-, odd-, or no-parity bit generation and detection

iii. 1-, or 2-stop bit generation

iv. Baud generation

b) False-start bit detection

c) Line break generation and detection

d) Hold and shift registers eliminate the need for precise synchronization between the CPU and

serial data

e) Programmable baud rate generator allows division of any input reference clock by 1 to (2161)

and generates an internal 16 clock

f) Standard asynchronous communication bits (start, stop, and parity) added to or deleted from

the serial data stream

g) Modem control functions (CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)

h) Independent receiver clock input

i) Transmit, receive, line status, and data set interrupts independently controlled

4.4.1 FIFO


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An asset-management and valuation method in which the assets produced or acquired first are

sold, used or disposed of first. FIFO may be used by a individual or a corporation.

FIGURE 12 FIFO operation

FIFO use of synchronizing two different frequency master.FIFo is use different data is high

speed and reading data,add low speed.

FIFO is an acronym for First In, First Out, which is an abstraction related to ways of

organizing and manipulation of data relative to time and prioritization. This expression describes

the principle of a queue processing technique or servicing conflicting demands by ordering

process by first-come, first-served (FCFS) behavior: where the persons leave the queue in the

order they arrive, or waiting one's turn at a traffic control signal.

FCFS is also the jargon term for the FIFO operating system scheduling algorithm, which gives

every process CPU time in the order they come. In the broader sense, the abstraction LIFO, or
http://en.wikipedia.org/wiki/Acronymhttp://en.wikipedia.org/wiki/Acronymhttp://en.wikipedia.org/wiki/Queue_(data_structure)http://en.wikipedia.org/wiki/First-come,_first-servedhttp://en.wikipedia.org/wiki/Jargonhttp://en.wikipedia.org/wiki/Scheduling_(computing)http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/LIFO_(computing)http://en.wikipedia.org/wiki/Acronymhttp://en.wikipedia.org/wiki/Queue_(data_structure)http://en.wikipedia.org/wiki/First-come,_first-servedhttp://en.wikipedia.org/wiki/Jargonhttp://en.wikipedia.org/wiki/Scheduling_(computing)http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/LIFO_(computing)


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Last-In-First-Out is the opposite of the abstraction FIFO organization. The difference perhaps is

clearest with considering the less commonly used synonym of LIFO, FILO (meaning First-In-

Last-Out). In essence, both are specific cases of a more generalized list (which could be accessed

anywhere). The difference is not in the list (data), but in the rules for accessing the content. One

sub-type adds to one end, and takes off from the other, its opposite takes and puts things only on

one end.[

FIGURE 13 FIFO RTL schematics

FIFO full/empty
http://en.wikipedia.org/wiki/FIFO#cite_note-Kruse-1http://en.wikipedia.org/wiki/FIFO#cite_note-Kruse-1


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In hardware FIFO is used for synchronization purposes. It is often implemented as a circular

queue, and thus has two pointers:

1. Read Pointer/Read Address Register

2. Write Pointer/Write Address Register

Read and write addresses are initially both at the first memory location and the FIFO queue is

Empty.

FIFO Empty

When read address register reaches to write address register, the FIFO triggers the Empty

signal.

FIFO FULL

When write address register reaches to read address register, the FIFO triggers the FULL

signal.

In both cases, the read and write address end up being equals. To distinguish the two situations, a

simple and robust solution is to add one extra bit for each read and write address which is

inversed each time the address wrap. With this in place, the conditions are:

FIFO Empty

When read address register equals to write address register, the FIFO is empty.

FIFO FULL

When read address LSBs equal to write address LSBs and extra MSBs are different, the

FIFO is full.

.4..4.2 Line Control Register (LCR):

The Line Control register sets the general connection parameters. Its 0 and 1 define the word

length (number of data bits). The line control register (LCR) is a 8 bit register. It is used for

precise specification of frame format and desired baud rate. The parity bits, stop bits, baud rate

selection and word length can be changed by writing the appropriate bits in LCR, format of
http://en.wikipedia.org/wiki/Circular_queuehttp://en.wikipedia.org/wiki/Circular_queuehttp://en.wikipedia.org/wiki/Circular_queuehttp://en.wikipedia.org/wiki/Circular_queue


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which is shown in Figure below indicates exact voltage levels of selection lines for selecting

different baud rates, odd/even parity and data word length.

Table3:LCR Bit Description Table


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Figure14: LCR Format

4.4.3 Baud Rate Generator:

The baud rate generator is programmable by three control bits Bit 0, Bit 1, Bit 2 in LCR as

shown in LCR bit description Table. 1 different baud rates can be selected by different

combinations of Bit 0, Bit 1 and Bit 2. For the selective baud rate the divisor can be obtained by

dividing the system clock by desired baud rate as shown in Table below which shows divisors

for various baud rates using 10 MHz system clock.

FIGURE 15. Baud Rate Generator


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The UART core can implement any of the standard baud rates for APB connections. The baud

rate can be configured in one of two ways:

Fixed rate

The baud rate is fixed at system generation time and cannot be changed via the Avalon-MM

slave port.

Variable rate

The baud rate can vary, based on a clock divisor value held in divisor register. A master

peripheral changes the baud rate by writing newvalues to the divisorregister.

The baud rate is calculated based on the clock frequency provided by the Avalon-MM interface.

Changing the system clock frequency in hardware without regenerating the UART core hardware

results in incorrect signaling.

Baud Rate (bps) Setting

The Baud Rate setting determines the default baud rate after reset. The

Baud Rate option offers standard preset values. The baud rate value is used to calculate an

appropriate clock divisor value to implement the desired baud rate. Baud rate and divisor values

are related as shown in

Equation 1 and Equation 2

Equation 1

Divisor = int (clock frequency/baud rate + 0.5)


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Equation 2

Baud rate =clock frequency/divisor + 1

Equation 3

Baud clk = t/p clk /16 * baud rate

Baud Rate Can Be Changed By Software Setting

When this setting is on, the hardware includes a 16-bit divisor register at address offset 4. The

divisor register is writable, so the baud rate can be changed by writing a new value to this

register. When this setting is off, the UART hardware does not include a divisor register. The

UART hardware implements a constant baud divisor, and the value cannot be changed after

system generation. In this case , writing to address offset 4 has no effect, and reading fromaddress offset 4 produces an undefined result.

4.4.4 Transmitter:

The transmitter section accepts parallel data, makes the frame of the data and transmits the data

in serial form on the Transmitter Output (TXOUT) terminal. Data is loaded from the inputs

TXIN0-TXIN7 into the Transmitter FIFO by applying logic high on the WR (Write) input.

If words less than 8 bits are used, only the least significant bits are transmitted. FIFO is 16-byte

register. When FIFO contains some data, it will send the signal to Transmitter Hold Register

(THR), which is an 8-bit register. At a same time, if THR is empty it will send the signal to

FIFO, which indicates that THR is ready to receive data from FIFO.

If Transmitter Shift Register (TSR) is empty it will send the signal to THR and it indicates that

TSR is ready to receive data from THR. TSR is a 12-bit register in which framing process

occurs. In frame start bit, stop bit and parity bit will be added. Now data is transmitted from TSR

to TXOUT serially.

The data which be receive when Tx done is high. The data is FIFo is taken and given to the Tx

hold register. THR makes a framing depends control register. After that data is transmitted to the

TSR. TSR shifts serially bit by bit depends open control logic the transmission is completed

when stop bit is transfer.


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FIGURE 16: Transmit module

Figure 16 showa the transmitter module .in this module shows the operation of transmitter .

The figures below show the entire working in form of flowcharts.
http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/txmit.vhdhttp://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/txmit.vhd


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Figure 17. Transmitter flowchart (Input to FIFO)

Figure 17 shows the flowchart of transmitter with FIFO input.


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Figure18. Transmitter flowchart (FIFO to Output)

4.4.5 Receiver:

The transmitted data from the TXOUT pin is available on the RXIN pin. The received data is

applied to the sampling logic block. The receiver timing and control is used for synchronization

of clock signal between transmitter and receiver. Initially the logic line is high whenever it goes

low sampling and logic block will take 4 samples of that bit and if all four are same it indicatesthe start of a frame. After that remaining bits are sampled in the same way and all the bits are

send to Receiver Shift Register (RSR) one by one where the entire frame is stored. RSR is a 12

bit shift register. Now if the Receiver Hold Register (RHR) is empty it sends signal to RSR so

that only the data bits from RSR goes to RHR which is an 8 bit register. The remaining bits in

the RSR are used by the error logic block. Now if receiver FIFO is empty it send the signal to


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RHR so that the data bits goes to FIFO. When RD signal is asserted the data is available in

parallel form on the RXOUT0-RXOUT7 pins. The error logic block handles 4 types of errors:

Parity error, Frame error, Overrun error, break error. If the received parity does not match with

the parity generated from data bits PL bit will be set which indicates that parity error occurred. If

receiver fails to detect correct stop bit or when 4 samples do not match frame error occurs and

SL bit is set. If the receiver FIFO is full and other data arrives at the RHR overrun error occurs

and OL bit is set. If the RXIN pin is held low for long time than the frame time then there is a

break in received data and break error occurs and BL bit is set.

FIGURE 19.: Receive module

Working of receiver is shown in terms of flowcharts in fig
http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/rxcver.vhdhttp://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/rxcver.vhd


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.

FIGURE 20. : Receiver flowchart (Input to FIFO)


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Figure 21 Receiver flowchart (FIFO to Output)

The operation of these two modules is not discussed here (with the exception of the baud rate

clock generator) as it is not required to be able to use the UART module. For further

information concerning this, refer to the UART App note or the respective VHDL code.

In order to use the UART you need to know what baud rate you want to transmit at. The

transmitter and receiver modules have been designed with a clock divider inside, which runs 16

times slower than the clock signal sent to it. Therefore, there should be a clock divider running

at 16 times the baud rate driving the UART modules.

The implemented UART module has 12 I/O ports, which are used to control it, get I/O to and

from it, and to determine its status.

4.4.6 STATUS REGISTER
http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/an20.pdfhttp://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/UART/an20.pdf


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The status register is a hardware register which contains information about the state of the

processor. Individual bits are implicitly or explicitly read and/or written by the machine code

instructions executing on the processor. The status register in a traditional processor design

includes at least three central flags: Zero, Carry, and Overflow, which are set or cleared

automatically as side effects of arithmetic operations. They may then be tested via conditional

branch or jump instructions. A status register may often have other fields as well, such as more

specialized flags,interrupt enable bits, and similar types of information. During an interrupt, the

status of the thread currently executing can be preserved (and later recalled) by storing the

current value of the status register along with theprogram counterand other active registers into

the machine stackor a reserved area of memory.

The Status Register takes the inputs from the error logic block and gives out four outputs thatspecify the Break error, overflow error, framing error and parity error.

Character framing:

The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in

which the line is held high to show that the line and transmitter are not damaged. Each character

is sent as a logic low start bit(0), a configurable number of data bits (usually 8, but legacy

systems can use 5, 6, 7) an optional parity bit, and one or two logic high stop bits(1).

Overrun error:

An "overrun error" occurs when the receiver cannot process the character that just came in before

the next one arrives. Various devices have different amounts of buffer space to hold received

characters. The CPU must service the UART in order to remove characters from the input buffer.

If the CPU does not service the UART quickly enough and the buffer becomes full, an Overrun

Error will occur, and incoming characters will be lost.

Framing error:

A "framing error" occurs when the designated "start" and "stop" bits are not valid. As the

"start" bit is used to identify the beginning of an incoming character, it acts as a reference for the
http://en.wikipedia.org/wiki/Hardware_registerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Machine_codehttp://en.wikipedia.org/wiki/Interrupthttp://en.wikipedia.org/wiki/Interrupthttp://en.wikipedia.org/wiki/Program_counterhttp://en.wikipedia.org/wiki/Call_stackhttp://en.wikipedia.org/wiki/Hardware_registerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Machine_codehttp://en.wikipedia.org/wiki/Interrupthttp://en.wikipedia.org/wiki/Program_counterhttp://en.wikipedia.org/wiki/Call_stack


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remaining bits. If the data line is not in the expected idle state when the "stop" bit is expected, a

FramingError will occur.

Parity error:

A "parity error" occurs when the number of "active" bits does not agree with the specified parity

configuration of the USART, producing a Parity Error. Because the "parity" bit is optional, this

error will not occur if parity has been disabled. Parity error is set when the parity of an incoming

data character does not match the expected value.

Break condition or Break Error:

A "break condition" occurs when the receiver input is at the "space" level for longer than someduration of time, typically, for more than a character time. This is not necessarily an error, but

appears to the receiver as a character of all zero bits with a framing error.

Some equipment will deliberately transmit the "break" level for longer than a character as an out-

of-band signal. When signaling rates are mismatched, no meaningful characters can be sent, but

a long "break" signal can be a useful way to get the attention of a mismatched receiver to do

something (such as resetting itself). Unix-like systems can use the long "break" level as a request

to change the signaling rate, to support dial-in access at multiple signaling rates.


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SIMULATION

Once all modifications to the test bench and subsystem .bfm are completed and the script let

created, the design can be simulated. Simulation is done in Very Large Scale Integration circuits

for evaluating the codes, that are used in certain applications to improve the integration process.

Simulation in VLSI is used in the PCB Fabrication process. Simulation is done to determine the

fault in the process. It has great role in PCB fabrication. Mainly two types of simulation used in

VLSI, they are serial and parallel simulation.

simulation is the process of checking the codes for vlsi for a particular application to implement

it in real time. mainly the codes for vlsi are written using Xilinx software.

BAUD RATE SIMULATION

In this simulation is present on 57600 burd rate clock is generate. In normal baud rate is fixed but

in this project baud rate is not fixed.


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Baud rate simulation

5.2 FIFO SIMULATION

In this simulation In this simulation FIFO is use staring different data is high speed and readingodd low speed. when FIFO is full then data is transmit. Write enable is 1 that time wait for 3024

ns .

FIFO SIMULATION


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5.3 LCR SIMULATION

When input bit will be set to logic 1 when RBR data is valid and will be reset to logic 0 whenRBR is empty. When line errors (OE/PE/FE/BI) happen, input bit will also be set to logic 1 and

data will be updated to reflect the Data bits portion of the frame

LCR SIMULATION

5.4 Transmitter Simulation


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The simulation shows the transmission of an 8-bit UART frame format with 1 stop bit and

without a parity bit. The transmission was set at 115.2kbps using 40MHz clock, which is equal to

25ns (1/40MHz = 25ns) period.

This simulation shows the signal results of the 8-bit data (00000111B) transmission via

DATA[7:0]. The transmitted UART frame format can be observed at TXD (1 low start bit, 8 data

bits (LSB to MSB), and 1 high stop bit).

THR

TSR


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TX RTL 1


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TX RTL 2


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5.5 Receiver Simulation

Fig. 5 shows how an 8-bit serial data from RXD is received. The data consists of 4 high bits and

4 low bits. The data is then converted to parallel RXDATA at 93.01us. S_RXDATA is the

internal parallel data received at the receiver. The output of the received parallel data is then

routed to DATA[7:0] outputs pin. The parallel data will be activated when the data output is

enabled (s_data oe = 0). The received data can be observed between the high impedance

DATA[7:0] (if the time/div is widened).

RX TOP MODULE

Receiver Simulation


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Rx RTL 1

RX RTL MODULE 2


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5.6 SAMPLING MODULE


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5.7 STATUS REGISTER

RTL STATUS REGISTER MODULE 1


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RTL STATUS REGSTER MODULE 2


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5.7 Without EXTENSION SIMULATION


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RTL UART module -1

RTL UART module -1


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RTL UART module-2


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WITH EXTATION SIMULATION


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RTL SCHEMATIC MODAL 1


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RTL SCHEMATIC MODAL 2

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