University of Calgary

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Graduate Studies The Vault: Electronic Theses and Dissertations

2017

Behavioral Modeling of Mixerless Three-Way

Amplitude Modulator-Based Transmitter

Chatrath, Jatin

Chatrath, J. (2017). Behavioral Modeling of Mixerless Three-Way Amplitude Modulator-Based

Transmitter (Unpublished master's thesis). University of Calgary, Calgary, AB.

doi:10.11575/PRISM/25102

http://hdl.handle.net/11023/3777

master thesis

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UNIVERSITY OF CALGARY

Behavioral Modeling of Mixerless Three-Way Amplitude Modulator-Based Transmitter

by

Jatin Chatrath

A THESIS

SUBMITTED TO THE FACULTY OF GRADUATE STUDIES

IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE

DEGREE OF MASTER OF SCIENCE

GRADUATE PROGRAM IN ELECTRICAL AND COMPUTER ENGINEERING

CALGARY, ALBERTA

APRIL, 2017

© Jatin Chatrath 2017

ii

Abstract

With an enormous rise in the application of smartphones, the need for highly efficient radio

architectures has increased significantly. Modern communication systems will be adopting a 5th

Generation (5G) standard for meeting the demands of the users efficiently. Analog mixers are a vital

component of any transmitter and perform the necessary task of up-converting a signal. However, there

are certain limitations associated with mixers including energy inefficiency. To eliminate these effects,

three-way mixerless transmitter (TWMT) architecture has been proposed in the literature. Existing

behavioral model for such an architecture make use of the digital splitters and combiners. In this thesis,

we propose a Triadic Complex Memory Polynomial based model for the forward and inverse modeling

of TWMT using analog combiners and splitters leading to a realistic scenario. Extensive simulations

and measurements have been used to validate their performance. The model meet the desired design

criteria concerning NMSE and ACLR.

iii

Acknowledgements

I would like to take this opportunity to acknowledge people who have contributed immensely

towards the completion of my thesis. Firstly, I would extend my deep sense of gratitude to my

supervisor, Dr. Mohamed Helaoui for his guidance, support and maintaining patience throughout

my degree. Without his excellent supervision and constructive inputs, my thesis would not have

been successfully completed.

I am grateful to my professor Dr. Fadhel M. Ghannouchi for letting me utilize his research space

and for providing me with excellent facilities and atmosphere for the completion of this thesis.

Furthermore, I would like to thank my committee member Dr. Rushi Vyas for his valuable

comments and advice on the thesis work.

I extend sincere thanks to my mentors Suhas Illath Veetil and Mohsin Aziz Baig for the stimulating

discussions and for helping me troubleshoot the experiments whenever needed. I would also like

to thank Chris Simon for his technical support and the entire iRadio Lab for their friendships and

for sustaining positive atmosphere in the lab.

Mom and Dad, thank you for keeping me sane, for always encouraging me to do my best, for

always believing in me and supporting me along the way. I would also like to thank Kanika Nagpal

for providing me constant support and motivation even though you are thousands of miles away.

Last but certainly not the least, I would like to thank my friends Rosy Dabas, Piyush Rawat, Prithvi

Tiwari, and Tushar Sharma for their continuous support, unparalleled love, and for the wonderful

times. This journey would not have been possible without your contributions.

Finally, a big thank you to everyone who has been a part of my journey and helped me to complete

my degree!

iv

Dedication

To my friends and family

v

Table of Contents

Abstract .............................................................................................................................................ii

Acknowledgements ........................................................................................................................ iii

Dedication ........................................................................................................................................ iv

Table of Contents ............................................................................................................................. v

List of Tables ................................................................................................................................ viii

List of Figures and Illustrations ...................................................................................................... ix

List of Symbols, Abbreviations and Nomenclature .....................................................................xii

Chapter One: Introduction ............................................................................................................... 1

1.1 Conventional direct conversion transmitters....................................................................... 3

1.1.1 Introduction ................................................................................................................. 3

1.1.2 Distortion in mixers .................................................................................................... 5

1.2 Parameters for performance analysis of a transmitter ........................................................ 7

1.2.1 Linearity ...................................................................................................................... 7

1.2.2 Adjacent channel power ratio .................................................................................... 9

1.2.3 Normalized mean square error ................................................................................... 9

1.3 Goals and objectives ........................................................................................................... 10

1.4 Thesis outline ...................................................................................................................... 11

Chapter Two: State of the Art ........................................................................................................ 12

2.1 Introduction ......................................................................................................................... 12

2.2 Polar Transmitters ............................................................................................................... 12

2.2.1 Implementation of phase modulator section in polar transmitters ........................ 14

2.2.2 Envelope and phase signal recombination techniques ........................................... 15

vi

2.2.3 Mixerless polar modulator-based transmitter ......................................................... 17

2.3 Summary of transmitter architectures ............................................................................... 19

2.4 Variable gain amplifier ....................................................................................................... 20

2.4.1 Variable gain amplifier as an amplitude modulator ............................................... 22

2.4.2 Imperfections in VGA .............................................................................................. 23

2.4.3 VGA calibration........................................................................................................ 24

2.5 Mixerless three-way amplitude modulator-based transmitter.......................................... 25

2.5.1 Introduction ............................................................................................................... 25

2.5.2 Three-way decomposition algorithm....................................................................... 26

2.5.3 Architecture of mixerless three-way amplitude modulator based transmitter ...... 30

2.5.4 Calibration Technique .............................................................................................. 32

2.5.5 Implementation of transmitter architecture ............................................................. 34

2.5.6 Measurement results ................................................................................................. 35

2.6 Conclusion........................................................................................................................... 36

Chapter Three: Forward Behavioral Modeling ............................................................................ 37

3.1 Introduction ......................................................................................................................... 37

3.2 Extended three-way signal decomposition algorithm ...................................................... 38

3.2.1 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in

00-1200. .................................................................................................................... 43

3.2.2 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in

1200-2400. ................................................................................................................ 46

3.2.3 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in

2400-3600. ................................................................................................................ 49

vii

3.3 Forward model for mixerless three-way amplitude modulator-based transmitter.......... 51

3.3.1 Mathematical analysis for 00-1200 ........................................................................... 51

3.3.2 Mathematical analysis for 1200-2400 ...................................................................... 54

3.3.3 Mathematical analysis for 2400-3600 ...................................................................... 55

3.4 Model Extraction Algorithm .............................................................................................. 57

3.5 Implementation of mixerless three-way amplitude modulator-based transmitter .......... 58

3.6 Measurement results ........................................................................................................... 61

3.7 Conclusion........................................................................................................................... 65

Chapter Four: Reverse Behavioral Modeling ............................................................................... 66

4.1 Introduction ......................................................................................................................... 66

4.2 Digital predistortion (DPD)................................................................................................ 68

4.3 Reverse model for mixerless three-way amplitude modulator-based transmitter .......... 69

4.3.1 Triadic complex memory polynomial calibration .................................................. 69

4.4 Implementation of the DPD system................................................................................... 72

4.5 Measurement results ........................................................................................................... 73

4.6 Conclusion........................................................................................................................... 76

Chapter Five: Conclusion and Future Work ................................................................................. 77

5.1 Contributions ....................................................................................................................... 78

5.2 Future work ......................................................................................................................... 79

References ....................................................................................................................................... 80

viii

List of Tables

Table 2.1 Summary of architectures .................................................................................................. 19

Table 2.2 VGA ADL5330 Specifications ......................................................................................... 21

Table 2.3 Summary of performance evaluation................................................................................ 35

Table 3.1 Expressions for xin,1, yin,1 and zin,1 when S1 lies in three different tridants...................... 39

Table 3.2 Expressions for S1, S2 and S3 in three different tridants................................................... 42

Table 3.3 Expressions of constants in different tridants .................................................................. 50

Table 3.4 Summary of performance for digital combining and proposed analog combining ....... 61

Table 4.1 Summary of performance evaluation of the proposed model ......................................... 74

ix

List of Figures and Illustrations

Figure 1.1. Ideal software defined radio architecture. ........................................................................ 2

Figure 1.2. Conventional analog transmitter. ...................................................................................... 4

Figure 1.3. Conventional direct conversion transmitter. .................................................................... 5

Figure 1.4. The circuitry of switching mixer. ..................................................................................... 6

Figure 1.5. Two-tone test representation. ............................................................................................ 8

Figure 2.1. Polar transmitter. ............................................................................................................. 13

Figure 2.2. Block diagram of mixerless polar modulator-based transmitter. ................................. 17

Figure 2.3. Variable Gain Amplifier (Analog Devices ADL5330). ................................................ 20

Figure 2.4. VGA as an amplitude modulator. ................................................................................... 22

Figure 2.5. Characteristics of VGA: (a) AM-PM, (b) AM-AM ...................................................... 23

Figure 2.6. Three coordinate based signal decomposition when S in1 lies in 00-1200 tridant. ........ 26

Figure 2.7. Representation of law of sines. ....................................................................................... 27

Figure 2.8. Three coordinate based signal decomposition when S in1 lies in tridant 1200-2400. .... 28

Figure 2.9. Three coordinate based signal decomposition when S in1 lies in tridant 2400-3600. .... 29

Figure 2.10. Mixerless three-way transmitter architecture with digital combining. ...................... 30

x

Figure 2.11. Block schematic of mixerless three-way amplitude modulator-based transmitter,

digital combining architecture with signal processing. .................................................................... 31

Figure 2.12. Approximation employed in linearization technique [39]. ......................................... 33

Figure 2.13. Mixerless three-way amplitude modulator-based transmitter implementation. ........ 34

Figure 3.1. High level block schematic of mixerless three-way amplitude modulator based

transmitter with analog combining and splitting. ............................................................................. 37

Figure 3.2. Expressing a point, Sin1 in 00-1200.................................................................................. 40

Figure 3.3. Expressing a point, Sin1 in 1200-2400. ............................................................................ 47

Figure 3.4. Expressing a point, Sin1 in 2400-3600. ............................................................................ 48

Figure 3.5. Block schematic of mixerless three-way amplitude modulator-based transmitter,

analog combining architecture with signal processing..................................................................... 56

Figure 3.6. Implementation of mixerless three-way amplitude modulator-based transmitter. ...... 60

Figure 3.7. Hardware implementation of the mixerless three-way amplitude modulator-based

transmitter. .......................................................................................................................................... 60

Figure 3.8. Characteristics of modeled and measured output signals for digital combining

architecture: (a) AM-PM, (b) AM-AM ............................................................................................. 62

Figure 3.9. Characteristics of modeled and measured output signals for analog combining

architecture: (a) AM-PM, (b) AM-AM ............................................................................................. 63

xi

Figure 3.10. Spectral response of modeled and measured output along with error signal for the

three-way transmitter implementation with digital combining........................................................ 64

Figure 3.11. Spectral response of modeled and measured output along with error signal for the

three-way transmitter implementation with analog combining. ...................................................... 64

Figure 4.1. Block schematic for the operation of digital predistorter based on indirect learning. 67

Figure 4.2. Predistortion and linearization. ....................................................................................... 68

Figure 4.3. Forward model of the mixerless three-way amplitude modulator-based transmitter.. 70

Figure 4.4. Reverse model of mixerless three-way amplitude modulator-based transmitter. ....... 71

Figure 4.5. LTE signal spectrum comparison between input signal, output signal before DPD and

output signal after DPD. ..................................................................................................................... 75

Figure 4.6. Wideband spectral response of the proposed architecture. ........................................... 75

xii

List of Symbols, Abbreviations and Nomenclature

Symbol Definition

3 GPP 3rd Generation Partnership Project

3G Third Generation

4G Fourth Generation

5G

ACLR

ACPR

ADC

ADS

AM

AM-AM

AM-PM

CW

DAC

DC

DCO

DPA

DPD

DSP

DUT

EER

EVM

Fifth Generation

Adjacent Channel Leakage Ratio

Adjacent Channel Power Ratio

Analog to Digital Converter

Advanced Design System

Amplitude Modulation

Amplitude to Amplitude Modulation

Amplitude to Phase Modulation

Continuous Wave

Digital to Analog Converter

Direct Current

Digitally Controlled Oscillator

Digital Power Amplifier

Digital Predistortion

Digital Signal Processing

Device Under Test

Envelope Elimination and Restoration

Error Vector Magnitude

xiii

FIR

FPGA

I

IF

K

LO

LTE

LTE-A

LUT

M

MP

NMSE

PA

PLL

PM

PM-AM

PM-PM

PSA

PWM

Q

QPSK

RF

SDR

Finite Impulse Response

Field Programmable Gate Array

In-Phase

Intermediate Frequency

Nonlinearity

Local Oscillator

Long Term Evolution

Long Term Evolution Advanced

Look Up Table

Memory Depth

Memory Polynomial

Normalized Mean Square Error

Power Amplifier

Phase Locked Loop

Phase Modulation

Phase Modulation to Amplitude Modulation

Phase Modulation to Phase Modulation

Power Signal Analyzer

Pulse Width Modulation

Quadrature

Quadrature Phase Shift Keying

Radio Frequency

Software Defined Radio

xiv

TC-MP

Tridant

TWMT

VGA

VSA

WCDMA

WLAN

Triadic Complex Memory Polynomial

There is no such word in the English dictionary

which refers to one third of a plane. However, in

this thesis, tridant is proposed to get a more

accurate appellation to refer one third of a plane.

Tridant is derived from the Latin prefix tri- and

suffix ant- like “quadrant”, which refers to quarter

of a plane.

Three-Way Mixerless Transmitter

Variable Gain Amplifier

Vector Signal Analyzer

Wireless Code Division Multiple Access

Wireless Local Area Network

1

Chapter One: Introduction

Evolution in the wireless communication industry has been extreme in the last 25 years. A sheer

tool of conversation and exchange of information has become an unavoidable part of our day-to-

day lives [1]. For a very long time, being the biggest market segment, wireless communication

has only been associated with cellular telephony. However, modern wireless communication has

applications in many fields including medicine, military, and engineering [2]. Vast development

in the integrated circuit industry has been noticed which resulted in doubling the number of

transistors on a single chip every second year as predicted by Moore’s law. The increasing number

of transistors has thus resulted in smartphones with better signal processing power and data rates.

Moreover, reduced cost of production in the semiconductor industry has also enhanced the

production of reliable and cheap priced communication devices. Combined, these developments

led to designing and manufacturing of smartphones with continuously increasing processing

power. To fully exploit high processing power of smartphones, signal modulation schemes should

be developed with high data rates and efficiency [3]. Therefore, the need for very high-speed

communication systems gave rise to new communication protocols and standards.

A variety of communication standards, such as Wireless Local Area Network (WLAN) and

Wireless Code Division Multiple Access (WCDMA), should be supported by new smartphones.

With the invention of 3rd Generation Partnership Project (3GPP) communication signals, a

milestone in the communications industry has been achieved [4]. The 3GPP standard offers higher

data rates and complex modulation schemes. Another breakthrough in the communication industry

was witnessed with the invention of Long Term Evolution (LTE) signal standard. It is based on

Orthogonal Frequency Division Multiplexing (OFDM) and operated in different bandwidths and

modulation schemes. Therefore, the LTE signal required high-performance transceiver systems.

2

With the passing time, communication standards have continuously evolved to integrate higher

data rate and efficiency. The recent development of Long Term Evolution Advanced (LTE-A)

from LTE allows to deploy bandwidths up to 100 MHz [5]. With the evolution of wireless

communication standards and signals, it was of prime importance to either upgrade or replace the

existing radio hardware. One of the vital features of this new radio hardware should be the

compatibility with the devices which still work on older communication schemes.

Micro-

processor

Micro-

processorDAC ADC

Tx Rx

Figure 1.1. Ideal software defined radio architecture.

In recent years, researchers from all over the world have been trying to develop transceivers which

can cater to the needs of different standards. The development of transceivers would facilitate

bringing the digital domain of the hardware as close as possible to the antenna to realize Software-

Defined Radio (SDR) [6, 7]. An ideal SDR supports any waveform by modifying the firmware or

software, keeping the hardware unchanged. Hereby, the term waveform refers to a signal with a

specific value for all parameters such as carrier frequency, data rate, modulation, coding, sampling

frequency, etc. The ideal SDR is shown in Fig. 1.1. The microprocessor maps the user data into

the desired waveform. The Digital-To-Analog Converter (DAC) converts the digital samples to a

Radio Frequency (RF) signal which is further sent to the transmitting antenna. The transmitted

signal enters the receiver through the receiver’s antenna, followed by sampling and digitization by

3

an Analog-To-Digital converter (ADC). The sampled signal is finally processed in real time by a

general-purpose microprocessor to obtain the user data.

It is extremely challenging to develop such an ideal and sophisticated SDR. The quest of

developing an ideal SDR has just started. The performance of these systems is gravely affected by

the various impairments associated with the different blocks in the transceiver. Modeling and

moderation of these impairments is a major step towards the realization of an optimal SDR

platform [7].

1.1 Conventional direct conversion transmitters

1.1.1 Introduction

Transmitter and receiver are the two vital blocks of any radio. In this thesis, the primary focus will

be on the transmitter block. Frequency up-conversion, digital modulation, and amplification are

some of the crucial functions performed by the transmitter. The amplified signal is then transmitted

through an antenna to a distant receiver. A block diagram of a conventional analog transmitter is

shown in Fig. 1.2. Components like RF power amplifier, anti-aliasing filter, and band-pass filter

are frequency selective, which means they work over a certain frequency range, and therefore they

limit the bandwidth of the transmitter. However, filtering the signal at different stages of the

transmitter reduces the unwanted signals and spurs, therefore, is essential to meet the spectrum

mask requirements in conventional transmitter design. Since these filters limit the RF bandwidth

of the transmitter architecture, designing broadband and multi-standard transmitters is a

challenging task. Multi-standard transmitters are often designed using multiple parallel transmitter

chains, each for a different standard. This approach results in high hardware complexity, high cost,

and is not reconfigurable for future standards. Therefore, transmitters that are reconfigurable and

4

can accommodate multiple standards are needed. To build such architectures, frequency selective

filters which are band limiting and hard to integrate should be eliminated from the transmitter

design.

Antenna

DSP DAC

Anti-aliasing

Filter

Variable Gain

AmplifierMixer Band Pass

Filter

RF Power

Amplifier

Local

Oscillator (LO)

Figure 1.2. Conventional analog transmitter.

Evidently, there are mainly three main topologies of transmitter architectures: super-heterodyne,

low Intermediate Frequency (IF) and, direct conversion [8]. Direct conversion architecture is the

most frequently used topology in multi-band and multi-standard applications due to its ease in

design and low implementation complexity [9]. Fig. 1.3 represents an analog quadrature RF

transmitter, which is based on direct conversion topology. The DACs are fed with digital baseband

In-Phase (I) and Quadrature (Q) data. The Nyquist criterion is satisfied by the DACs which in turn

moves the DAC replicas away from the desired band. Reconstruction filters that are placed after

the DACs remove the aliasing replicas. Variable Gain Amplifiers (VGAs) adjust the gain in the I

and Q paths. The signal in the form of I and Q is then fed to a quadrature modulator. To up-convert

the signal to the desired carrier frequency and generate the complex modulated signal, the in-phase

(I) component is multiplied with a Local Oscillator (LO) signal having 00 phase shift while the

quadrature (Q) component is multiplied with an LO signal having 900 phase shift. The two

5

multiplied signals are summed together to generate the complex modulated signal at the desired

RF frequency. Band-pass filters are used to suppress the out-of-band emissions produced by the

mixers of the quadrature modulator while the RF Power Amplifier (PA) is used to adjust the power

level of the RF signal. The desired RF signal is then transmitted through the antenna.

DSP

DAC

DAC

`

00

900

LO

Mixer

Mixer

Variable Gain

Amplifier

Variable Gain

Amplifier

Band Pass

Filter

Re-construction

Filter

RF Power

Amplifier

Antenna

Re-construction

Filter

I

Q

Figure 1.3. Conventional direct conversion transmitter.

However, several off-chip components like filters and power amplifiers limit the bandwidth of the

transmitter. Multiple filtering is involved in suppressing out-of-band distortions produced by

switching mixers and to meet spectral mask requirements. This, in turn, reduces the RF bandwidth

of the complete transmitter.

1.1.2 Distortion in mixers

One of the significant components of conventional direct conversion topology is the switching

mixer. Fig. 1.4 shows the diagram of ideal switching mixer that is commonly used in direct

conversion architectures. Such mixers implement polarity switching function in response to the

LO input while maintaining the low noise and high linearity objectives.

6

-1

+1

Baseband Input

Output

fLO

Switching

x(t)

x(t).LO

3fLO

Frequency (f)

Frequency (f)

fLO 5fLO

. . .

Am

pli

tud

e

fLO

Frequency (f)

3fLO 5fLO

. . .

00

0

Am

pli

tud

e

Figure 1.4. The circuitry of switching mixer.

In switching mixers, LO signal is a square wave which can be expressed using Fourier series as,

4 1 1

sin(2 ) sin(6 ) sin(5 ) ...3 5

LO LO LOLO f t f t f t

(1.1)

where fLO is the frequency of the LO.

Then, the output of the switching mixer can be represented as,

4 1( ) cos(2 ( ))sin(2 ) cos(2 ( ))sin(6 ) ...

3BB LO BB LOOutput A t f t t f t f t t f t

(1.2)

where fBB is the frequency of baseband signal.

This equation can be further simplified and represented as,

sin(2 ( ) ( )) sin(2 ( ) ( ))2

( ) 1 1sin(2 ( 3 ) ( )) sin(2 ( 3 ) ( )) ...

3 3

BB LO BB LO

BB LO BB LO

f f t t f f t t

Output A tf f t t f f t t

(1.3)

where fRF and fLO are the baseband and LO frequency, respectively.

The equation (1.3) shows that switching mixers are responsible for producing harmonics at

different frequencies of LO. These harmonic distortions are generated by switching function of the

mixer and not by nonlinear gain. Therefore, these distortions cannot be compensated with

7

linearization techniques [10]. Hence, filtering at different stages of the conventional direct

conversion topology cannot be avoided.

Consequently, this thesis emphasizes on the behavioral modeling and impairment compensation

of a re-configurable mixerless transmitter for SDR applications. It aims at implementing a

broadband mixerless transmitter in the analog domain and developing forward and reverse

mathematical models to imitate the system performance and mitigate the nonlinear and linear

distortion effects in this transmitter architecture. Once linearized, this transmitter will not require

any band-limiting RF filtering before the power amplifier. This transmitter design would be

suitable for integration, and for multi-standard and multi-band reconfigurability. Therefore,

mixerless transmitters are suitable candidates for SDR topologies.

1.2 Parameters for performance analysis of a transmitter

1.2.1 Linearity

Linearity is a crucial requirement of a transmitter as nonlinearity in the transmission system causes

degradation in the signal quality, which makes the information detection and demodulation

difficult at the receiver. A transmitter is said to be linear if and only if the corresponding output is

directly proportional to its input. Off-chip linear and nonlinear components like power amplifiers

and band-pass filters, generally degrade the signal quality in the transmitter by introducing linear

and nonlinear distortions. To achieve high quality signals, the transmitter should be equalized and

linearized to suppress these distortions. The nonlinear distortions in the transmitter generate

intermodulation products in the band of the signal and harmonic products at multiples of the carrier

frequency [11]. A two-tone test or a modulated signal test can be used to measure these harmonics

[12]. Fig. 1.5 shows how intermodulation products are generated when a two-tone signal is fed to

8

a nonlinear system. When a signal is supplied to a nonlinear system it generates even and odd

order products such as second order and third order. The even-order nonlinearities lie away from

the desired band and are often filtered out at the output of the nonlinear system using RF band-

pass filters. Odd order nonlinearities generate intermodulation distortion close to fundamental

frequency resulting in in-band distortion and cannot be filtered out.

f1 f2

Non-Linear

System

f1 f2

2f1-f2 2f2-f1

3f1-2f2 3f2-2f1

Third-Order

Distortion Product

Fifth-Order

Distortion Product

f1+f2

2f1 2f2

{Second-Order

Distortion Product

Figure 1.5. Two-tone test representation.

Conventionally, linearization techniques such as digital and analog predistortion [13] are used to

compensate for these nonlinear effects. A very low power of the intermodulation product (2f1-f2

and 2f2-f1) as compared to the power of fundamental tones (f1 and f2) depicts a highly linear

transmitter architecture and minimum in-band distortion to the signal. The in-band distortion can

be quantified using a figure of merit called Normalized Mean Square Error (NMSE) while the out-

of-band distortion is quantified using a figure of merit called Adjacent Channel Power Ratio

(ACPR).

9

1.2.2 Adjacent channel power ratio

In case of modulated signals, nonlinearity in the device results in intermodulation products, which

leads to spectral regrowth. This regrowth, in turn, may cause interference in the adjacent channels

[11]. To avoid the interference, nonlinearity in the devices must be modeled and mitigated. ACPR

is an important figure of merit for evaluating the performance of a transmitter in the presence of

nonlinearity. It quantifies the spectral regrowth in nonlinear systems and devices. ACPR can be

defined as the difference between the out-of-band power spectral density measured at certain offset

channel in dBm, Poffset (dBm), and the in-band power spectral density in dBm, Pinband (dBm) [12].

( ) ( ) ( )offset inbandACPR dBc P dBm P dBm (1.4)

Adjacent Channel Leakage Power Ratio (ACLR) is the term used instead of ACPR for LTE signal

waveform format.

1.2.3 Normalized mean square error

Normalized Mean Square Error (NMSE) is an important metric for evaluating the in-band

performance of a forward and reverse behavioral model of a nonlinear system such as the

transmitter. NMSE is an estimator of the overall deviations between modeled and measured values.

It gives a measure of the difference between the value that is estimated by the model and the value

that is measured. The NMSE [14] can be mathematically represented as,

2

mod

10 21

( ) ( )1( ) 10log

( )

Nmeas

n meas

Y n Y nNMSE dB

N Y n

(1.5)

where, Ymeas(n) and Ymod(n) are the output waveforms measured and estimated from the model,

respectively. N is the number of discrete time samples of the signal considered in the calculation.

10

1.3 Goals and objectives

The primary aim of this thesis work is to implement a wideband mixerless transmitter architecture

that is suitable for multi-band, multi-standard, and SDR applications. The primary aim will be

reached through various steps.

First, this work targets the hardware implementation of the RF front-end of a “Mixerless three-

way amplitude modulation-based transmitter” with all the passive components such as three-way

power splitter/combiner and phase shifters in the analog domain.

Additionally, this thesis aims at understanding and modeling the type and nature of distortion

generated by this topology. A behavioral forward model, triadic complex memory polynomial

(TC-MP), which models the amplitude response of all the three VGAs as a single block, will be

proposed. The linear distortion in passive components such as phase shifters and power

combiners/splitters will also be considered in this modeling exercise. The accuracy of the model

will be decided by calculating the difference in terms of NMSE, between the model output and the

actual hardware measured output.

Finally, once a sound understanding of the nature and characteristics of distortions is obtained,

which further will be mitigated by proposing a reverse model. The proposed reverse model will be

used as a predistorter or precompensator for the mixerless transmitter. The predistorted transmitter

will be measured to show the effectiveness of the reverse model by compensating the linear and

nonlinear distortions. Both in-band and out-of-band distortion will be quantified in terms of NMSE

and ACPR, respectively. Additionally, the power of the harmonic distortions will be measured to

prove that this topology does not need any RF band-pass filtering.

11

1.4 Thesis outline

The thesis is described as follows:

The fundamentals of a radio transmitter for wireless communication is presented in chapter one.

Herein, the key parameters and the performance metrics of a radio transmitter are discussed.

Additionally, the chapter introduces the objectives and methodology of this thesis work.

In chapter two, different mixerless architectures that are proposed in literature are introduced.

Specifically, the advantages of mixerless polar transmitters and mixerless three-way amplitude

modulator-based transmitters are discussed. Limitations and challenges in implementing mixerless

three-way amplitude modulator-based transmitters, such as signal combining and splitting and

digital predistortion implementation are listed and explained. Finally, this chapter concludes by

highlighting the need to model the responses of the full transmitter, including the three amplitude

modulators and other passive components, in a single box.

In chapter three, the three-way amplitude modulator-based transmitter front-end is implemented

fully in hardware for the first time. The transmitter translates the baseband signal to RF domain

without using mixers. The responses of the VGAs and the other passive components are measured

by proposing a new black box behavioral forward modeling technique for the complete three-way

amplitude modulator-based transmitter. Finally, the chapter is concluded with implementation

details and measurement results.

In chapter four, a new reverse model is proposed to be used for digital predistortion of the mixerless

transmitter. The implementation details, measurement results and the performance evaluation of

the architecture are also provided at the end of this chapter.

Finally, the thesis is concluded in chapter 5, with a summary of the significant contributions

achieved in this work. A proposal for future work direction is also presented.

12

Chapter Two: State of the Art

2.1 Introduction

In chapter one, the concerns with the existing mixer-based conventional direct conversion

architecture were discussed. Also, the need of mixerless transmitter architecture which is more

suitable for integration and reconfigurabilty was justified. The current chapter discusses the state-

of-the-art attempts to realize the mixerless transmitter topologies.

2.2 Polar Transmitters

The direct conversion transmitter architecture is the most frequently used topology. However,

there are certain drawbacks related to the direct conversion architecture such as distortions in

mixers, In-Phase and Quadrature (I/Q) modulator impairments, Direct Current (DC) offset, a Local

Oscillator (LO) leakage and quantization noise as explained in [15 16]. Additionally, due to

separate I and Q branches, direct conversion architectures suffer from different timing

misalignment, which also results in signal quality degradation and affects the accuracy of the time

delay estimation in behavioral modeling and predistortion function estimation. Many research

groups have previously addressed these limitations by proposing new designing techniques and

modulator architectures, suggesting signal processing algorithms to compensate for the

impairments, or by testing new homodyne transmitter topologies that avoid the use of quadrature

modulators and mixers.

Another promising candidate for direct digital transmitters is polar transmitters, which is inspired

by Envelope Elimination and Restoration (EER) technique by Kahn [17]. In polar transmitters,

unlike conventional transmitters, modulation of baseband signal occurs in the amplitude and phase

domain rather than I and Q components.

13

DSP

LO PA

QΦ

IΦ

00

900

Amplitude

I

Q

Band Pass

Filter

Mixer

Mixer

Antenna

Figure 2.1. Polar transmitter.

Fig. 2.1 shows the block diagram of a polar transmitter architecture in which digital baseband

signal IQ is decomposed into amplitude A(t) and phase Φ(t) by,

2 2( ) ( ) ( )A t I t Q t (2.1)

1 ( )

( ) tan( )

Q tt

I t

(2.2)

where, I and Q are the in-phase and quadrature components of the complex IQ signal.

As seen from Fig. 2.1, the phase signal Φ(t) is passed through quadrature modulator and converted

in Radio Frequency (RF) domain from baseband. The phase modulated RF signal, having constant

envelope is recombined with envelope signal A(t) to generate complex RF signal. High-efficiency

switch mode Power Amplifier (PA) is used to recombine the envelope signal and the phase-

modulated RF signal [18]. Having greater power efficiency means less DC power consumption.

Also, better carrier suppression can be achieved with the polar transmitter as compared to

conventional IQ architectures.

However, there are certain integral challenges with the polar transmitter such as nonlinear

decomposition results in bandwidth expansion. Also, delay adjustments should be precise between

14

the amplitude and phase paths. To satisfy spectrum mask requirements of the wireless standards,

recombination of the envelope and phase signals should be done after proper delay adjustments

[19].

2.2.1 Implementation of phase modulator section in polar transmitters

There are different techniques by which the phase modulator segment can be implemented such as

quadrature up-converters [20, 21], external signal generators [22], vector modulators [23, 24] and

Phase Lock Loop (PLL) circuits [25, 26]. The phase modulators, when realized with quadrature

up-converters, have problems that are mutual to mixer based circuits. Mixer based circuits use

mixers and quadrature up-converters to translate the baseband phase signal to RF domain. Such

circuits suffer from mixer spurs and distortions. To eliminate these distortions, imperfect bulky

filters are incorporated into the design, which further reduces the ability of integration. Besides,

these filters are frequency components that limit the transmitter bandwidth.

PLL circuit can be used as an exceptional phase modulator. In such circuits, phase modulation is

directly applied to the synthesized RF carrier signal [16]. Apparently, it eliminates the use of IQ

up-converters which in turn reduces the problem of spurious emissions. By using a digital PLL

circuit, bandwidth constraints can be eradicated [27]. By decomposing IQ baseband digital signal,

the phase signal is obtained which can be differentiated to obtain the frequency deviations. To

generate the phase modulated carrier signal, the differentiated phase signal is supplied to the

Digitally Controlled Oscillator (DCO) based modulator. In this technique, it is therefore critical to

maintain the tuning range of the oscillator. However, a PLL-based architecture also holds certain

challenges such as the bandwidth limitations, phase noise and the requirement of a pre-

compensation techniques like digital filtering [27].

15

2.2.2 Envelope and phase signal recombination techniques

During the same tenure, significant advancements were made in the envelope and phase signal

recombination techniques of polar transmitters. The most common and frequently used

recombination technique is the supply or drain modulation as shown in Fig. 2.1 and explained in

[20, 21]. Phase of I and Q signals are provided to the input of quadrature modulator to obtain phase

modulated RF signal. The received signal is then further supplied to the input of the RF PA.

Furthermore, amplitude information is inserted by varying the PA’s supply voltage. The insertion

of the amplitude information can either be achieved by using a switching regulator with good

efficiency or by using a DC to DC converter. To achieve high efficiency, switch mode PAs can be

used in saturation as input to the PA is constant envelope signal. However, switch mode PAs are

nonlinear devices and often introduce distortion to the signal. Therefore, architectures that use

switch mode PAs require filtering and predistortion. Hence, a trade-off between efficiency and

linearity exists in such architectures due to which careful designing of supply modulators is

required. Modeling techniques that are used to compensate for the distortions introduced by the

switch mode PAs are detailed in [28]. Moreover, envelope conditioning methods that are used to

address the issue of feed through capacitance are explained in [29, 30].

In another technique [23], Pulse-Width Modulation (PWM) is employed to realize polar

transmitter architecture. To drive multiple class C amplifiers, multiphase pulse-width modulated

signal is used which eventually increases the sampling frequency leading in reduction of out-of-

band emissions and further minimizing the filtering requirements. This work employs vector

modulator to realize phase modulation circuitry. Similarly, interleaved PWM have also been used

to reduce spurs and relieve filtering requirements [24]. Additionally, to increase the efficiency of

PWM, switch mode amplifiers were used as PAs.

16

Additional techniques such as Digital Power Amplifiers (DPAs) have also been employed for

envelope and phase signal recombination without using supply modulation [22, 31, 32, 33].

Although, n number of unit amplifiers which are basically switched as per digital amplitude bits

are supplied with phase modulated RF signal with constant envelope. Complex RF signal is

attained by combining the outputs of these PAs. Also, to reduce the spectral images, oversampling

and interpolation are applied [32]. However, the nonlinearity and power combing challenges are

faced with these architectures [33].

Class D-1 PAs array based polar transmitter architecture has been implemented in [34]. Here,

transformer-based power combining is employed. Initial processing has been performed in Field-

Programmable Gate Array (FPGA). Primary and secondary windings of the transformer are

coupled in series for power combining, whereas, the output of each PA is given to primary

winding. High-efficiency PAs produce distortions to the signal, which makes the system nonlinear.

To mitigate nonlinear effects, Look-Up Table (LUT)-based predistortion and oversampling is used

which reduces the out-of-band noise while the phase modulator section comprises of external

Digital-To-Analog (DAC) and modulator.

In recent studies, Variable Gain Amplifiers (VGAs) have been used for envelope and phase signal

recombination [25, 26]. Amplitude Modulated (AM) signal, also called envelope signal is

generated digitally at the baseband and then fed in to the gain control port of the VGA while the

RF input port of the VGA is fed with the Phase Modulated (PM) signal which has constant

envelope. Thus, by changing the gain as per the gain control signal, the VGA will reconstruct the

amplitude modulation. However, challenges like update rate of the VGA and dynamic range are

faced by such architectures [26].

17

In [35], modified Gilbert cell is used to integrate the phase path with polar transmitter. Unit

amplifiers such as Class D-1 PAs, comprise the amplitude path. Primary and secondary windings

of the transformer are coupled in series for power combining. To achieve higher efficiency, the

impedance is varied and IQ phase interpolator is used to implement the phase modulator. High-

efficiency PAs produce distortions to the signal, which makes the system nonlinear. To mitigate

nonlinear effects, LUT-based predistortion is used. To deal with spurs and noise, Finite Impulse

Response (FIR) interpolation filters and high sampling rate is employed.

2.2.3 Mixerless polar modulator-based transmitter

Recently, a mixerless polar modulator-based transmitter architecture that uses analog RF VGA

and analog phase shifter was proposed and implemented [38, 39]. The mixerless polar modulator-

based transmitter architecture is shown in Fig. 2.2.

Digital Signal

Processing

I Q

EnvelopePhase

Phase Shifter

(Phase Modulator)

LO Variable Gain Amplifier (VGA)

(Amplitude Modulator)

RF

Output

Figure 2.2. Block diagram of mixerless polar modulator-based transmitter.

The term mixerless is used because it translates the baseband phase signal directly to RF without

using mixers and up-converter circuits. Thus, spurs and distortions that are associated with typical

18

analog mixer and up-converters are absent. Furthermore, imperfect bulky filters which limit the

bandwidth of the transmitter are eliminated in this architecture. This, in turn, makes the transmitter

design reconfigurable and more suitable for integration. In this topology, baseband IQ signal is

decomposed into envelope and phase components by using equations (2.1) and (2.2). The VGA

maps the amplitude or the envelope to gain control voltage, while the phase shifter maps the phase

component into phase control voltage. The gain control voltage drives the VGA while the phase

control voltage drives the phase shifter. Furthermore, the RF Continuous Wave (CW) signal with

desired frequency and power level is fed to RF input port of the phase shifter. Apparently, the

output of the phase shifter now has phase modulated RF signal with constant envelope. The RF

phase-modulated signal at the output port of the phase shifter is then fed to RF input port of the

VGA. Through the gain control port of the VGA, the amplitude information is inserted to the phase

modulated RF signal to generate the complex RF signal at the output of the VGA. The polar

modulator-based transmitter topology exhibits good performance for Long Term Evolution (LTE)

signal [38 39]. However, the phase shifter used in the topology has issues with noise and affects

the quality of the RF output signal. The phase shifter is driven by constant control phase voltage.

Over a period, phase shifter exhibits phase variations when constantly driven by control voltage.

These variations were not modeled and compensated by the modified memory polynomial model

proposed by the author. This unconventional behavior is not correlated with the signal, which

makes them appear as phase noise at the output of the transmitter. Furthermore, at the output of

the transmitter architecture, these distortions due to the phase shifter affects the overall quality of

the RF signal.

19

2.3 Summary of transmitter architectures

The various architectures of polar transmitter as well as phase modulation that are explained in

section 2.2 are summarized in Table 2.1.

Table 2.1 Summary of architectures

POLAR TRANSMITTER ARCHITECTURE

Drain Modulation Limited bandwidth

(spectrum growth)

Nonlinearity

issues

Mismatch of delay

between amplitude

and phase path

Supply

modulator

bandwidth

DPA Limited bandwidth

(spectrum growth)

Nonlinearity

issues

Mismatch of delay

between amplitude

and phase path

Power

combining

VGA Limited bandwidth

(spectrum growth)

Nonlinearity

issues

Mismatch of delay

between amplitude

and phase path

Update rate

of VGA

PHASE MODULATION ARCHITECTURES

Quadrature up-

converter Wide bandwidth

Noise and

emissions Filtering requirements

Gilbert cells Wide bandwidth Noise and

emissions Filtering requirements

PLL Low bandwidth Noise Filtering requirements

MIXERLESS POLAR ARCHITECTURE

Mixerless polar

modulator-based

architecture

Wide bandwidth

Phase noise

and

emissions

No filtering requirements

20

2.4 Variable gain amplifier

In the VGA, the gain can be set to a required level simply by adjusting the external control voltage

settings [36, 37]. The VGAs can operate over a wide frequency range from dc to gigahertz (GHz).

VGAs are generally used to control signals exhibiting wide dynamic range of the mobile phone

receivers. Depending on the distance between the base-station and the cellular device, the power

level of the received signal varies drastically. Therefore, a VGA in a mobile phone receiver can

control the level of the signal coming into the device. VGAs are also commonly used to match the

level of input signal to full scale input of a device such as Analog-To-Digital converters (ADCs).

Apart from a wide range of applications in communication systems, VGAs can be useful in

industrial, medical and scientific sectors in measurement equipment. In this work, VGAs are used

as an amplitude modulator.

Gain Control

Port

Input

PortOutput

Port

Figure 2.3. Variable Gain Amplifier (Analog Devices ADL5330).

21

There are mainly two types of VGAs, analog and digital and either one can be used based on the

type of application. In this thesis work, an analog VGA is used. The gain of the analog VGA (in

dB) is the linear function of the gain control voltage and can be represented mathematically as,

( ) ( )Gain dB slope vctrl intercept (2.3)

where, vctrl is the gain control voltage, intercept is the gain of the VGA when vctrl is 0 volts and

slope is given as dB/volt.

In this thesis, three VGA evaluation boards from “Analog Devices”, part number ADL5330 are

used. Fig. 2.3 shows the picture of the VGA’s used while the specifications of ADL5330 are given

in Table 2.2.

Table 2.2 VGA ADL5330 Specifications

SPECIFICATION VALUE

Operating frequency 10 MHz to 3GHz

Gain range 60 dB

Bandwidth on the gain control pin 3 MHz

Control voltage range 0-1.4 V

Linear-in-Db gain control function 20 mv/dB

OIP3 31dBm

In this Table, one can see that the OIP3 of the VGA is 31 dBm which results in the P1dB to be

approximately 20 dBm. From this information, we can conclude that the linear operating range of

the VGA is from 0 dBm to 10 dBm. During our experimentation, the VGA was operated in this

range to avoid its nonlinear behavior. However, as depicted in Fig. 2.5, the AM-AM and AM-PM

22

curves show nonlinear characteristics. This is because the baseband signal provided to the gain

control pin of the VGA has a variation in its amplitude which leads to an overall nonlinear system.

2.4.1 Variable gain amplifier as an amplitude modulator

VGA can be used as an amplitude modulator as shown in Fig. 2.4, where the gain control input

acts as a modulating signal [38, 39]. A CW signal with required frequency and amplitude is fed

into the RF input port of the VGA. The modulating signal at the gain control port of the VGA is

mapped to voltage based on the slope and the intercept of the VGA. According to this voltage, the

gain of the VGA is varied and modulated signal is then attained at the RF output port of the VGA.

Mathematically, it can be represented as [38, 39],

2( ) Re ( ) j ft

in inV t v t e (2.4)

2( ) Re ( ) j ft

out inV t m v t e (2.5)

( )cm v t s (2.6)

where, vc(t) and s are the gain control signal and sensitivity of the VGA, respectively, while Vin(t)

and Vout(t) are the complex RF signals at the input and output of the VGA, respectively.

Gain

Control

Local

OscillatorVGA

Amplitude

Modulated RF

Signal

Figure 2.4. VGA as an amplitude modulator.

23

Envelope information can be expressed in terms of in-phase and quadrature (IQ) signals by the

equation,

2 2env I Q (2.7)

Therefore, mapping from envelope to gain control voltage can be represented mathematically as,

1020 log ( )vctrl a env b (2.8)

where, vctrl is the gain control voltage, env is the envelope signal obtained using (2.7) and the

values of constants a and b are obtained from the DC gain response of the VGA.

2.4.2 Imperfections in VGA

For an ideal VGA, the gain of the device varies linearly with the control voltage. As the signal

propagates through the amplifier, the phase of the RF signal should remain constant. However,

due to the circuit inaccuracy, nonlinearity in phase and gain responses of the VGA are observed.

(a) (b)

Figure 2.5. Characteristics of VGA: (a) AM-PM, (b) AM-AM

24

The nonlinearity in phase and gain responses of the VGA can be seen in Fig. 2.5 and [39]. It depicts

that VGA has both Amplitude Modulation to Phase Modulation (AM-PM) and Amplitude

Modulation to Amplitude Modulation (AM-AM) responses. Like PAs, VGA too exhibits memory

effects [40, 41]. This means that the output of the VGA depends on present and previous input

values. Therefore, these nonlinearity and memory effects affect the quality of the RF modulated

signal at the output of the VGA. Thus, calibration and modeling of the VGA to mitigate the

imperfections is of prime importance.

2.4.3 VGA calibration

As mentioned in the previous section, the VGA exhibits similar memory effects, and nonlinear

gain and phase responses to that of a RF PA. Therefore, memory polynomial [42] can be used to

model and mitigate these effects. A conventional memory polynomial with positive real

coefficients can be represented as,

1

0 1

( ) ( 1) ( )M K

k

mk

m K

y n a x n x n m

(2.9)

where, amk is the real predetermined calibration constant. K is the nonlinearity order and M is the

memory depth of the memory polynomial. Whereas, x(n) and y(n) represent the input and output

envelope signals, respectively. This memory polynomial models the memory effects and

nonlinearity of the VGA in a single step. Least squares technique is used to extract the model

coefficients [45]. These coefficients are used to model the response of the VGA. Here, input to the

forward model is the actual envelope signal and output is the envelope of complex signal captured

at the output of the VGA. However, reverse model of the VGA is obtained by swapping the input

and the output envelopes with each other. This reverse model can be used to estimate the input of

25

the VGA from the output. Therefore, DPD coefficients are extracted through this reverse model

coefficients. Hence, the DPD created through a reverse model is also a memory polynomial model.

Also, modeling and linearization of the gain response of the VGA using memory polynomial is

represented in [38, 39]. The validation was done on the amplitude of the signal where no phase

nonlinearity is considered. Performance of the VGA in [39] is authenticated by using an LTE

signal sampled at a rate of 30.72 Msamples/s. CW or LO signal is kept at 2.2 GHz and has a power

level of -10 dBm. Whereas, LTE signal of 1.4 MHz of bandwidth was used. The Normalized Mean

Square Error (NMSE) before and after Digital Predistortion (DPD) was observed to be -24.51 dB

and -50.04 dB, respectively. Adjacent Channel Leakage Ratio (ACLR) before and after DPD was

observed to be 33.97 dBc and 57.62 dBc, respectively, while keeping nonlinearity order of 5 and

memory depth of 2. The measurement results from [39] shows that the VGA can be used to

implement a highly linear amplitude modulator.

2.5 Mixerless three-way amplitude modulator-based transmitter

2.5.1 Introduction

Another mixerless transmitter topology was developed in [39]. In this work, the baseband IQ signal

is translated to RF domain without mixers, frequency up-converters and phase modulator circuits

such as phase shifters and PLLs. This new transmitter topology, called “The mixerless three-way

amplitude modulation-based transmitter”, is based upon the decomposition of the complex

envelope of the signal into three envelope components using three-coordinate decomposition

algorithm. To translate the baseband signal to a carrier frequency, three VGAs act as envelope

modulators for the three decomposed components. Since, the transmitter is free from phase

modulator circuit, thus, it avoids any issues related to it.

26

2.5.2 Three-way decomposition algorithm

The original Sin1 (IQ) signal can be written in polar format (r, θ1) as rejθ1 where, r is the magnitude

and θ1 is the angle. Equations (2.1) and (2.2) represent r and θ1, respectively. The three-coordinate

decomposition consists of mapping any IQ signal from the two-axis complex plane to a plane of

three positive coordinates, where, each axis is 120º/240º shifted from the other axes. To illustrate

the concept, an example of a complex point, Sin1 (I+jQ), is shown in Fig. 2.6 along with the three-

coordinate (x, y, z) plane. For this point, there is a positive value for the xin,1 component, and a

positive value for yin,1 component, while the zin,1 component is equal to zero. These three vectors

when added result in a vector that represents the complex envelope of the signal. This algorithm

also ensures that the components xin,1, yin,1 and zin,1 are non-negative. The xin,1, yin,1 and zin,1

components are further mapped to control voltages by using equation (2.8).

Y

X

Z

θ1

Sin1(I+jQ)

600

xin,1

yin,1

1200-θ1r

Figure 2.6. Three coordinate based signal decomposition when Sin1 lies in 00-1200 tridant.

27

θ ϕ

a

bc

A B

C

ψ

Figure 2.7. Representation of law of sines.

To better comprehend the decomposition algorithm used in [39], consider triangle ABC with

length of the sides as a, b and c and angles as θ, ϕ and ψ as shown in Fig. 2.7. As per law of sines,

relation between different components can be expressed as,

sin( ) sin( ) sin( )

b a c

(2.10)

From the above relation, value of a can be obtained as,

sin( )

sin( )

ca

(2.11)

Therefore, when Sin1 lies in tridant1 00-1200, values of xin,1, yin,1 and zin,1 components in Fig. 2.6 can

be represented as,

0

1,1 0

sin(120 )

sin(60 )in

rx

(2.12)

1 There is no such word in the English dictionary which refers to one third of a plane. However, in this thesis, tridant

is proposed to get a more accurate appellation to refer one third of a plane. Tridant is derived from the Latin prefix

tri- and suffix ant- like “quadrant”, which refers to quarter of a plane.

28

1,1 0

sin( )

sin(60 )in

ry

(2.13)

In this tridant, the value zin,1 is zero. Thus, value of zin,1 can be calculated when θ1 is greater than

1200.

Similarly, as seen from Fig. 2.8, values of xin,1, yin,1 and zin,1 components when Sin1 lies in tridant

1200-2400 are,

0

1,1 0

sin(120 ')

sin(60 )in

ry

(2.14)

1,1 0

sin( ')

sin(60 )in

rz

(2.15)

where, θ1ʹ = θ1-1200.

The value of xin,1 component is zero in 1200-2400 tridant.

Y

X

Z

θ1

Sin1(I+jQ)

600

yin,1

zin,1

θ1' r

Figure 2.8. Three coordinate based signal decomposition when Sin1 lies in tridant 1200-2400.

29

Likewise, as seen from Fig. 2.9, values of xin,1, yin,1 and zin,1 components when Sin1 lies in tridant

2400-3600 are,

1,1 0

sin( ")

sin(60 )in

rx

(2.16)

0

1,1 0

sin(120 ")

sin(60 )in

rz

(2.17)

where, θ1ʹʹ = θ1-2400.

The value of yin,1 component is zero in 2400-3600 tridant.

Y

X

Z

θ1

Sin1(I+jQ)

600

zin,1

xin,1

θ1''

r

Figure 2.9. Three coordinate based signal decomposition when Sin1 lies in tridant 2400-3600.

Therefore, a complex envelope, Sin1=rejθ1, can be decomposed into three positive real components

xin,1, yin,1 and zin,1 with a phase difference of 120º between them as,

0 0120 240

1 ,1 ,1 ,1

j j

in in in inS x y e z e (2.18)

30

2.5.3 Architecture of mixerless three-way amplitude modulator based transmitter

The high level schematic diagram of the three-way transmitter architecture is shown in Fig. 2.10.

The control voltages act as modulating signal to the LO. The LO signal is fed to RF input port of

each VGA, while control voltages, namely, Xvoltage, Yvoltage and Zvoltage are fed into gain control port

of each VGAx, VGAy and VGAz, respectively. To avoid impairments such as gain and phase

imbalance and delay misalignment between the three branches, the outputs from each VGA are

captured one by one using a Vector Signal Analyzer (VSA). These three outputs, Xout, Yout and Zout

are then processed and added digitally. The processing and combining operation is implemented

in the digital domain to allow for accurate phase rotation of 00, 1200 and 2400 for Xout, Yout and Zout,

respectively, avoiding any phase imbalance. Before combining, the captured signals from the VSA

are also aligned in amplitude to avoid any amplitude imbalance and aligned in delay to avoid any

delay mismatch. Because of this ideal combining in the digital domain, the measurement results

showed excellent linearity performance in [39].

Local

Oscillator

DSPIQ

00

1200

2400

XvoltageZvoltage Yvoltage

VGAY

VGAX

VGAZ

RF

Output

VSA

VSA

VSA

Digital

Splitting Signal

Alignment

Signal

Alignment

Signal

Alignment

Digital

Combining

Figure 2.10. Mixerless three-way transmitter architecture with digital combining.

31

Fig. 2.11 shows the block schematic of the transmitter architecture using digital combining along

with digital signal processing blocks. As mentioned earlier, the measurement is taken for each

branch separately by using only a single DAC. In [39], splitting of LO and combining output from

VGAx, VGAy and VGAz are performed digitally as shown in Fig. 2.10 and Fig. 2.11. The author

does not use any analog splitter, phase shifter and analog combiners. This is not a practical solution

to the problem as the objective is to combine the three signals to generate a RF modulated output

in the analog domain. Moreover, the digital combination is ideal and ignores the gain and phase

imbalance and delay misalignment impairments that exist in practical implementations.

Decomposition

00 + Φx

1200 + Φy

2400 + Φz

Phase

Mapping

Φx,Φy,Φz Filtering and

Compensation

DAC

Iin

Qin

Vx,y,z

xejΦx

yejΦy

zejΦz

Local

Oscillator

VSA

(Agilent E4440A)

Time Delay

Adjustment and

Phase

Compensation

Decomposition

00,1200 ,2400

VGAx/y/z

Frequency

Down-convertorADC

Digital

Demodulator

Iout_x/y/z

Qout_x/y/z

Iin_x/y/z

Qin_x/y/z

Digital Combining

Sout = x+yej120+zej240

Iout

Qout

VGAx

DPD

VGAz

DPD

VGAy

DPD

Voltage

Mapping

x

y

z

Figure 2.11. Block schematic of mixerless three-way amplitude modulator-based

transmitter, digital combining architecture with signal processing.

32

2.5.4 Calibration Technique

As explained in previous section, VGA exhibits nonlinear gain response and memory effects. To

model the nonlinear gain response and memory effects exhibited by the VGA, author uses a

conventional memory polynomial [39] for each of the three branches, which can be represented

as,

1

,1 ,1

0 1

( ) ( ) ( )M K

k

mk in in

m k

y n a x n m x n m

(2.19)

where, amk is the complex model coefficient that can be predetermined from a training signal. K is

the nonlinearity order and M is the memory depth of the memory polynomial model. y(n)

represents the output signal while xin,1(n) represents the input signals of the VGA. To model the

nonlinearity and memory effects of the VGA, a conventional memory polynomial can be used. A

training sequence of 10,000 samples is used to extract model coefficients. Least squares technique

is employed to extract these coefficients [45]. Therefore, by using the original input signal and

extracted coefficients, the complex output signal is estimated. To evaluate the performance of the

model, the measured output signal of the VGA is compared with the estimated output signal using

the NMSE metric. Linearization of the system is achieved by generating reverse model. To obtain

the reverse model of the VGA the input and output signals are swapped. Thus, for the reverse

model, the input is complex and has both the magnitude and phase information, while the output

is real and has only the magnitude component.

This predistortion technique, which uses three digital predistorters to model and mitigate the

nonlinear amplitude and phase response of the three VGAs, requires to have the information of the

input as well as the output of each VGA, which is not feasible in practical implementation when

the signals are combined in analog. Moreover, as seen from Fig. 2.12 (b) the input signal to the

33

forward model has real values while the measured output signal is complex. To obtain the reverse

model of the single VGA the input and output signals are swapped.

Forward

Model

Reverse

Model

Predistorter

DUT

VGA

Input Output

Output

x x'ejΦx

x

xest

x''

(a)

(b)

(c)

(d)

x'ejΦx

est

x'ejΦx

xejΦx

Figure 2.12. Approximation employed in linearization technique [39].

Thus, as seen from Fig. 2.12 (c) input to the reverse model is complex and output is real and has

only the magnitude component. Since the input to the predistorter block should be complex,

therefore the x, y and z component is multiplied with the measured phase error of VGAx, VGAy

and VGAz, respectively as shown in Fig. 2.12 (d). This complex signal is multiplied with the

reverse model coefficients. At the output of the predistorter block, ideally we should obtain a real

valued signal. However, there is some residual phase present. This residual phase is approximated

to zero and only magnitude is considered, since the modulating signal can only have real values.

34

Due to this approximation, small portion of the phase information of the input signal is lost.

Therefore, the modeling approach results in limited accuracy.

2.5.5 Implementation of transmitter architecture

Fig. 2.13 shows the implementation of mixerless three-way amplitude modulator based transmitter

carried out in [39], where the combining of the three branches are done using an ideal phase

splitting and signal combining blocks in the digital domain. In this setup, the three VGAs are

operated separately. The three voltages are generated in MATLAB and fed to the gain control pin

of the VGAs one after the other. LO is given to the RF input port of the VGAs. The RF output of

each VGA is captured separately using power spectrum analyzer and digitized using VSA

software. Time alignment is carried out distinctly on each branch using maximum correlation

technique. Finally, phase rotation and the power combining operations are performed in digital

domain.

Vx/y/z

Data In (xin/yin/zin) Data Out (xout/yout/zout)

ADL 5330 VSA E440A

ESG 4438C

(Local Oscillator)

ESG 4438C

DSP

Figure 2.13. Mixerless three-way amplitude modulator-based transmitter implementation.

35

2.5.6 Measurement results

To validate the proposed transmitter architecture and calibration technique, the author in [39] uses

an LTE signal with Quadrature Phase Shift Keying (QPSK) constellation. The signal is

oversampled by the factor of 16 and the baseband signal consists of 100,000 samples. This

complex signal is decomposed into three gain control voltages. The LO frequency is set to 2.2

GHz with power level of -5 dBm. The measurement results are summarized in Table 2.3.

Measurement results show that the calibration technique works well for the tested architecture.

However, the test has been done with an ideal combiner implemented digitally without considering

any gain and phase imbalance nor any delay misalignment distortions found in a more realistic

implementation.

Table 2.3 Summary of performance evaluation

SPECIFICATION VALUE

Signal bandwidth 1.4 MHz

NMSE before digital predistortion -14.80 dB

NMSE after digital predistortion -40.86 dB

ACLR before digital predistortion 30.83 dBc

ACLR after digital predistortion 54.76 dBc

This thesis takes the work done in [39] closer to realistic implementation by including the hardware

implementation of the analog combing and splitting circuits, which are performed in analog

domain. New forward modeling and digital predistortion approaches are also proposed, which

mitigates the amplitude responses of all the three VGA’s in a single step in addition to the

distortions introduced by the analog combiner, splitter, and phase shifters.

36

2.6 Conclusion

In this chapter, the state-of-the-art research work on polar transmitters is summarized. A

comparison of the different polar architectures, their advantages and drawbacks are given in this

chapter. Also, the need of a mixerless frequency up-converter that is more suitable for integration

and reconfigurability is vindicated. Techniques highlighting state-of-the-art attempts to propose

solutions for these needs using mixerless three way architectures are reviewed profoundly. It was

concluded that a more realistic implementation that considers imbalance and delay misalignment

impairments is needed along with a single step modeling algorithm to consider not only the

amplitude modulators’ nonlinearity but also the analog combining impairments as well.

37

Chapter Three: Forward Behavioral Modeling

3.1 Introduction

In the previous chapter, key components of mixerless three-way amplitude modulator-based

transmitter and the disadvantages associated with the linearization of a non-realistic

implementation of this topology using digital power splitting and combining were detailed. In this

chapter, along with a complete implementation of a wideband mixerless three-way amplitude

modulator-based transmitter ranging from 500 MHz to 3 GHz, integrated with all passive

components, a new model, Triadic Complex Memory Polynomial (TC-MP) is proposed to mimic

the magnitude and phase non-linearities introduced in all the three branches by three VGAs in a

single block. The performance of the modified memory polynomial is tested using Long Term

Evolution (LTE) signal of 1.4 MHz bandwidth.

Local

Oscillator

DSPIQ

00

XvoltageZvoltage Yvoltage

VGAY

VGAX

VGAZ

RF

Output

Analog

splitter

Analog Phase

shifter (1200)

Analog Phase

shifter (2400)

Analog

CombinerPA

Figure 3.1. High level block schematic of mixerless three-way amplitude modulator based

transmitter with analog combining and splitting.

High level block diagram of three-way mixerless amplitude modulator based transmitter with

analog combining and splitting is shown in Fig. 3.1. As seen from the figure, power amplifier (PA)

38

will be required to amplify the RF signal produced at the output of the mixerless transmitter.

However, impairments introduced by PA are not included in this work as the aim is to model and

mitigate the impairments introduced by the three-way amplitude modulator based system. A lot of

work exists on PA’s impairment modeling and the analysis of the three-way amplitude based

transmitter’s modeling, including the PA’s nonlinear effects, is straight forward.

Multi-standard signals are subject to various distortions when passed through different stages of

the transmitter due to the imperfections in the various components of the transmitter. Several

block-based behavioral models such as Wiener Hammerstein, Augmented Weiner, Augmented

Hammerstein, and Memory Polynomial (MP) were proposed for modeling the nonlinear

distortions in the transmitters [46-52]. These methods, however, do not consider the impairments

introduced by the modulator such as In-Phase/Quadrature (I/Q) imbalance and Direct Current (DC)

offset and only lessen the nonlinear distortions introduced by Power Amplifiers (PAs). In

literature, several models such as Volterra series based model, Neural Networks based model, and

variations of memory polynomial models have been proposed to successfully model and alleviate

the impairments introduced by the modulator and the PA [53-58]. However, in this thesis, a new

TC-MP is proposed for modeling of all the three VGA’s amplitude and phase response in a single

step.

3.2 Extended three-way signal decomposition algorithm

As discussed in section 2.5.2, any complex point with a magnitude r and an angle θ1 can be

decomposed into xin,1, yin,1 and zin,1 components. Thus, a complex envelope of a signal is

represented by the addition of three vectors that are obtained by out phasing xin,1, yin,1 and zin,1

components by 00, 1200 and 2400, respectively. The aim of extended three-way decomposition

39

algorithm is to express xin,1, yin,1 and zin,1 as functions of Sin1, Sin1ej120 and Sin1ej240 to further help us

in generating a black box model for modeling and mitigation of the mixerless transmitter

impairments. Also, to simplify the equations, Sin1, Sin1ej120 and Sin1ej240 are represented as S1, S2 and

S3, respectively. Here, S1 can be represented in polar format as rejθ1, S2 can be represented in polar

format as rejθ2 while S3 can be represented in polar format as rejθ3.

From section 2.5.2, we can identify the values of xin,1, yin,1 and zin,1 when S1 lies in 00-1200, 1200-

2400 and 2400-3600, respectively. The values of S1 are summarized in Table 3.1.

Table 3.1 Expressions for xin,1, yin,1 and zin,1 when S1 lies in three different tridants

00-1200 1200-2400 2400-3600

S1 (Sin1)

0

1,1 0

sin(120 )

sin(60 )in

rx

,1 0inx 1

,1 0

sin( ")

sin(60 )in

rx

1,1 0

sin( )

sin(60 )in

ry

0

1,1 0

sin(120 ')

sin(60 )in

ry

,1 0iny

,1 0inz 1,1 0

sin( ')

sin(60 )in

rz

0

1,1 0

sin(120 ")

sin(60 )in

rz

The aim is to find the expressions for S2 (xin,2, yin,2 and zin,2) and S3 (xin,3, yin,3 and zin,3) when S1 lies

in 00-1200 tridant as shown in Fig 3.2. Deriving these expressions will further assist us to derive

the expressions for xin,1, yin,1 and zin,1 as functions of S1, S2 and S3.

From Table 3.1 we can derive the expressions for S2 and S3 in 00-1200. Since all the expressions

are in linear combination, thus, xin,2, yin,2 and zin,2 in 00-1200 will be identical to xin,1, yin,1 and zin,1

in 1200-2400. Thus, xin,2, yin,2 and zin,2 in 00-1200 can be represented as,

40

0

2,2 0

sin(120 ')

sin60in

ry

(3.1)

2,2 0

sin( ')

sin 60in

rz

(3.2)

As we can see from Table 3.1, expression for xin,1 in 1200-2400 is 0 thus expression for xin,2 in 00-

1200 will be 0.

Y

X

Z

rθ1

S1(Sin1)

600

S2(Sin1ej120)

xin,1

yin,1

S3(Sin1ej240)

θ2

θ3

Figure 3.2. Expressing a point, Sin1 in 00-1200.

From Fig. 3.2, we observe that θ2 = θ1+1200. As mentioned in chapter two expressions for θ1ʹ = θ1-

1200. Similarly, θ2ʹ can be written as θ2ʹ = θ2-1200. Therefore, θ2ʹ = θ1. Hence, equations (3.1) and

(3.2) can be written in terms of θ1. Henceforth, xin,2, yin,2 and zin,2 in 00-1200 are depicted in Table

3.2.

Similarly, since all the expressions are in linear combination, thus, xin,3, yin,3 and zin,3 in 00-1200

will be identical to xin,1, yin,1 and zin,1 in 2400-3600. Thus, xin,3, yin,3 and zin,3 in 00-1200 can be

represented as,

41

3,3 0

sin( ")

sin(60 )in

rx

(3.3)

0

3,3 0

sin(120 ")

sin(60 )in

rz

(3.4)

As seen from Table 3.1, expression for yin,1 in 2400-3600 is 0, thus, the expression for yin,3 in 00-

1200 will also be 0. From Fig. 3.2, we can observe that θ3 = θ1+2400. We know that θ1ʹʹ = θ1-2400.

Similarly, θ3ʹʹ can be written as θ3ʹʹ = θ3-2400. Therefore, θ3ʹʹ = θ1. Hence, equations (3.3) and (3.4)

can be written in terms of θ1. Henceforth, xin,3, yin,3 and zin,3 in 00-1200 are depicted in Table 3.2.

Likewise, expressions can be derived for S2 and S3 in 1200-2400 and 2400-3600 when S1 lies in 1200-

2400 and 2400-3600, respectively. All the expressions for S1, S2 and S3 are depicted in Table 3.2.

42

Table 3.2 Expressions for S1, S2 and S3 in three different tridants

00-1200 1200-2400 2400-3600

S1 (Sin1)

0

1,1 0

sin(120 )

sin(60 )in

rx

xin,1=0

1,1 0

sin( ")

sin(60 )in

rx

1,1 0

sin( )

sin(60 )in

ry

0

1,1 0

sin(120 ')

sin(60 )in

ry

yin,1=0

zin,1=0 1

,1 0

sin( ')

sin(60 )in

rz

0

1,1 0

sin(120 ")

sin(60 )in

rz

S2

(Sin1ej120)

xin,2=0 1

,2 0

sin( ')

sin(60 )in

rx

0

1,2 0

sin(120 ")

sin(60 )in

rx

0

1,2 0

sin(120 )

sin(60 )in

ry

yin,2=0

1,2 0

sin( '')

sin(60 )in

ry

1,2 0

sin( )

sin(60 )in

rz

0

1,2 0

sin(120 ')

sin(60 )in

rz

zin,2=0

S3

(Sin1e240)

1,3 0

sin( )

sin(60 )in

rx

0

1,3 0

sin(120 ')

sin(60 )in

rx

xin,3=0

yin,3=0 1

,3 0

sin( ')

sin(60 )in

ry

0

1,3 0

sin(120 '')

sin(60 )in

ry

0

1,3 0

sin(120 )

sin(60 )in

rz

zin,3=0

1,3 0

sin( ")

sin(60 )in

rz

43

3.2.1 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in 00-1200.

Consider a point Sin1 (I+jQ) in 00-1200 tridant as shown in Fig. 3.2. As mentioned earlier, our aim

is to decompose a point Sin1 into xin,1, yin,1 and zin,1 components as functions of S1, S2 and S3. Thus,

xin,1, yin,1 and zin,1 components can be written as functions of S1, S2 and S3 as,

,1 1 1 1 2 1 3inx a S b S c S (3.5)

,1 2 1 2 2 2 3iny a S b S c S (3.6)

,1 3 1 3 2 3 3inz a S b S c S (3.7)

where, a1, b1, c1, a2, b2, c2, a3, b3 and c3 are constants which needs to be derived.

Let us consider equation (3.5) and find out the values for a1, b1 and c1. Component xin,1 can be

derived by summing all the components corresponding to S1, S2 and S3 in 00-1200. The expressions

for xin,1, yin,1, zin,1, xin,2, yin,2, zin,2, xin,3, yin,3 and zin,3 in 00-1200 are characterized in Table 3.2.

Summing these components can be represented as,

0

1 1 1 1,1 0 0

0

1 1 1 11 1 1 2 1 3 ,1 0 0

0

1 1 1 1,1 0 0

sin(120 ) sin( )

sin(60 ) sin(60 )

sin( ) sin(120 )0

sin(60 ) sin(60 )

sin( ) sin(120 )0

sin(60 ) sin(60 )

in

in

in

a r c rx

a r b ra S b S c S y

b r c rz

(3.8)

Since there are three constants and three equations, we need to set any one constant to 1. For the

time being let a1 equals to 1. Hereby, to find the value of component xin,1, equate components yin,1

and zin,1 to 0. By setting components yin,1 and zin,1 to 0 and a1 to 1, the values of constants b1 and c1

can be calculated as,

44

11 0

1

sin( )

sin( 120 )b

(3.9)

2

11 2 0

1

sin ( )

sin ( 120 )c

(3.10)

Henceforth, to compensate for the assumption of setting a1 to 1, let us consider another constant α

which can be represented as,

0 0

,1

0 0 0 0

,1 1 ,3

(0 120 )

(0 120 ) (0 120 )

in

in in

x

x c x

(3.11)

where components xin,1 (00-1200) and xin,3 (00-1200) are represented in Table 3.2, while c1 is

represented in equation (3.10). The expression for α can be represented as,

3 0

1

3 0 3

1 1

sin ( 120 )

sin ( 120 ) sin ( )

(3.12)

Therefore, expression of α is multiplied with a1, b1 and c1 to get new constants A1, B1 and C1,

respectively. These constants can be represented as,

3

11 3 3

1 1

sin ( 120 )

sin ( 120 ) sin ( )A

(3.13)

2

1 11 3 3

1 1

sin ( 120 )sin( )

sin ( 120 ) sin ( )B

(3.14)

2

1 11 3 3

1 1

sin( 120 )sin ( )

sin ( 120 ) sin ( )C

(3.15)

Hence, component xin,1 can be characterized as,

,1 1 1 1 2 1 3inx A S B S C S (3.16)

45

Similarly, expression for component yin,1 can be estimated by summing all the components

corresponding to S1, S2 and S3 in 00-1200. New constants are considered to avoid confusion. Let

these constants be a2, b2 and c2. The expressions for xin,1, yin,1, zin,1, xin,2, yin,2, zin,2, xin,3, yin,3 and zin,3

in 00-1200 are characterized in Table 3.2. Summing these components can be represented as,

0

2 1 2 1,1 0 0

0

2 1 2 12 1 2 2 2 3 ,1 0 0

0

2 1 2 1,1 0 0

sin(120 ) sin( )0

sin(60 ) sin(60 )

sin( ) sin(120 )S S S

sin(60 ) sin(60 )

sin( ) sin(120 )0

sin(60 ) sin(60 )

in

in

in

a r c rx

a r b ra b c y

b r c rz

(3.17)

Again, for the time being let b2 equals to 1. Hereby, to find the value of component yin1, equate

components xin,1 and zin,1 to 0. By setting components xin,1 and zin,1 to 0 and b2 to 1, the values of

constants a2 and c2 can be calculated as,

2

12 2 0

1

sin ( )

sin ( 120 )a

(3.18)

12 0

1

sin( )

sin( 120 )c

(3.19)

Henceforth, to compensate for the assumption of setting b2 to 1, let us consider another constant β

which can be represented as,

0 0

,1

0 0 0 0

,2 2 ,1

(0 120 )

(0 120 ) (0 120 )

in

in in

y

y a y

(3.20)

where components yin,1 (00-1200) and yin,2 (00-1200) are represented in Table 3.2, while a2 is

represented in equation (3.18).

The expression for β can be represented as,

46

2 0

1 1

3 0 3

1 1

sin ( 120 )sin( )

sin ( 120 ) sin ( )

(3.21)

Therefore, expression of β is multiplied with a2, b2 and c2 to get new constants A2, B2 and C2,

respectively. These constants can be represented as,

3

12 3 3

1 1

sin ( )

sin ( 120 ) sin ( )A

(3.22)

2

1 12 3 3

1 1

sin ( 120 )sin( )

sin ( 120 ) sin ( )B

(3.23)

2

1 12 3 3

1 1

sin( 120 )sin ( )

sin ( 120 ) sin ( )C

(3.24)

Therefore, yin,1 can be characterized as,

,1 2 1 2 2 2 3iny A S B S C S (3.25)

The expression of component zin,1 in 00-1200 tridant is 0. Hence, the values of constants A3, B3 and

C3 are also 0.

3.2.2 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in 1200-2400.

Consider a point Sin1 (I+jQ) in 1200-2400 tridant as shown in Fig. 3.3. The components xin,1, yin,1

and zin,1 can be represented as,

,1 4 1 4 2 4 3inx A S B S C S (3.26)

,1 5 1 5 2 5 3iny A S B S C S (3.27)

,1 6 1 6 2 6 3inz A S B S C S (3.28)

47

Y

X

Z

rθ1

S1(Sin1)

600

S2(Sin1ej120)

yin,1

zin,1

S3(Sin1ej240)

θ2

θ3

Figure 3.3. Expressing a point, Sin1 in 1200-2400.

The expressions for xin,1 is 0 when S1 (Sin1) lies in 1200-2400. Therefore, values of A4, B4 and C4

correspond to 0. Whereas, expressions for A5, B5, C5, A6, B6 and C6 can directly be derived from

A1, B1, C1, A2, B2 and C2. From Table 3.2, we can see that expression for xin,1 in 00-1200 correspond

to expression for yin,1 in 1200-2400. Also, expression for yin,1 in 00-1200 correspond to expression

for zin,1 in 1200-2400. From Fig. 3.3 we can see that S1, S2 and S3 lies in 1200-2400, 2400-3600 and

00-1200, respectively. Then constants A1, B1, C1 will correspond to constants C5, A5 and B5,

respectively. Similarly, constants A2, B2, C2 will correspond to constants C6, A6 and B6,

respectively. Therefore, A5, B5, C5, A6, B6 and C6 can be expressed in terms of θ1ʹ as,

2

1 15 3 3

1 1

sin ( ' 120 )sin( ')

sin ( ' 120 ) sin ( ')A

(3.29)

48

2

1 15 3 3

1 1

sin( ' 120 )sin ( ')

sin ( ' 120 ) sin ( ')B

(3.30)

3

15 3 3

1 1

sin ( ' 120 )

sin ( ' 120 ) sin ( ')C

(3.31)

2

1 16 3 3

1 1

sin ( ' 120 )sin( ')

sin ( ' 120 ) sin ( ')A

(3.32)

2

1 16 3 3

1 1

sin( ' 120 )sin ( ')

sin ( ' 120 ) sin ( ')B

(3.33)

3

16 3 3

1 1

sin ( ')

sin ( ' 120 ) sin ( ')C

(3.34)

where, θ1ʹ= θ1-1200. By substituting this value of θ1ʹ in above equations, new expression for A5,

B5, C5, A6, B6 and C6 are derived and represented in Table 3.3.

Y

X

Z

rθ1

S1(Sin1)

600

S2(Sin1ej120)

zin,1

xin,1

S3(Sin1ej240)

θ2

θ3

Figure 3.4. Expressing a point, Sin1 in 2400-3600.

49

3.2.3 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in 2400-3600.

Consider a point Sin1 (I+jQ) in 2400-3600 tridant as shown in Fig. 3.4. The components xin,1, yin,1

and zin,1 can be represented as,

,1 7 1 7 2 7 3inx A S B S C S (3.35)

,1 8 1 8 2 8 3iny A S B S C S (3.36)

,1 9 1 9 2 9 3inz A S B S C S (3.37)

Similarly, the expression for yin,1 is 0 when S1 (Sin1) lies in 2400-3600. Therefore, values of A8, B8

and C8 correspond to 0. Similar to section 3.2.2, expressions for A7, B7, C7, A9, B9 and C9 can

directly be derived from A1, B1, C1, A2, B2 and C2. These expressions can be represented as,

2

1 17 3 3

1 1

sin( '' 120 )sin ( '')

sin ( '' 120 ) sin ( '')A

(3.38)

3

17 3 3

1 1

sin ( '')

sin ( '' 120 ) sin ( '')B

(3.39)

2

1 17 3 3

1 1

sin ( '' 120 )sin( '')

sin ( '' 120 ) sin ( '')C

(3.40)

2

1 19 3 3

1 1

sin( '' 120 )sin ( '')

sin ( '' 120 ) sin ( '')A

(3.41)

3

19 3 3

1 1

sin ( '' 120 )

sin ( '' 120 ) sin ( '')B

(3.42)

2 0

1 19 3 3

1 1

sin ( '' 120 )sin( '')

sin ( '' 120 ) sin ( '')C

(3.43)

where, θ1ʹʹ= θ1-2400. By substituting this value of θ1ʹʹ in above equations, new expression for A7,

B7, C7, A9, B9 and C9 are derived and represented in Table 3.3.

50

Table 3.3 Expressions of constants in different tridants

VALUES OF CONSTANTS IN DIFFERENT TRIDANTS

Values of Constants when Sin1 lies in 00-1200

3

11 3 3

1 1

sin ( 120 )

sin ( 120 ) sin ( )A

3

12 3 3

1 1

sin ( )

sin ( 120 ) sin ( )A

3 0A

2

1 11 3 3

1 1

sin ( 120 )sin( )

sin ( 120 ) sin ( )B

2

1 12 3 3

1 1

sin ( 120 )sin( )

sin ( 120 ) sin ( )B

3 0B

2

1 11 3 3

1 1

sin( 120 )sin ( )

sin ( 120 ) sin ( )C

2

1 12 3 3

1 1

sin( 120 )sin ( )

sin ( 120 ) sin ( )C

3 0C

Values of Constants when Sin1 lies in 1200-2400

4 0A

2

1 15 3 3

1 1

sin ( 240 )sin( 120 )

sin ( 240 ) sin ( 120 )A

2

1 16 3 3

1 1

sin ( 240 )sin( 120 )

sin ( 240 ) sin ( 120 )A

4 0B

2

1 15 3 3

1 1

sin( 240 )sin ( 120 )

sin ( 240 ) sin ( 120 )B

2

1 16 3 3

1 1

sin( 240 )sin ( 120 )

sin ( 240 ) sin ( 120 )B

4 0C

3

15 3 3

1 1

sin ( 240 )

sin ( 240 ) sin ( 120 )C

3

16 3 3

1 1

sin ( 120 )

sin ( 240 ) sin ( 120 )C

Values of Constants when Sin1 lies in 2400-3600

2

1 17 3 3

1 1

sin( 360 )sin ( 240 )

sin ( 360 ) sin ( 240 )A

8 0A

2

1 19 3 3

1 1

sin( 360 )sin ( 240 )

sin ( 360 ) sin ( 240 )A

3

17 3 3

1 1

sin ( 240 )

sin ( 360 ) sin ( 240 )B

8 0B

3

19 3 3

1 1

sin ( 360 )

sin ( 360 ) sin ( 240 )B

2

1 17 3 3

1 1

sin ( 360 )sin( 240 )

sin ( 360 ) sin ( 240 )C

8 0C

2

1 19 3 3

1 1

sin ( 360 )sin( 240 )

sin ( 360 ) sin ( 240 )C

51

3.3 Forward model for mixerless three-way amplitude modulator-based transmitter

As discussed in chapter two, the three-way transmitter architecture consists of three VGAs. Each

VGA has a gain and phase response, which needs to be modeled accurately. Moreover, there are

some limitations associated with the model proposed in [39] for e.g., the use of digital combining

does not compensate for gain and phase imbalance. Furthermore, the residual phase in the

modeling technique utilizes approximation to get real signals at the output of each DPD. In

contrast, the proposed one-box model, the TC-MP, accounts for the above-mentioned limitations.

Briefly, the proposed model compensates for the gain and phase imbalance and accounts for all

the types of distortions in the mixerless three-way amplitude modulator-based transmitter without

making any approximations.

3.3.1 Mathematical analysis for 00-1200

We know, that the output of a single VGAx, VGAy and VGAz can be accurately modeled with a

memory polynomial in the following manner [39],

, ,1

1 0

( ( ))K M

k

out k m in

k m

x h x n m

(3.44)

, ,1

1 0

( ( ))K M

k

out k m in

k m

y h y n m

(3.45)

, ,1

1 0

( ( ))K M

k

out k m in

k m

z h z n m

(3.46)

where, hk,m is the complex model coefficients. xout, yout and zout are the outputs of the VGAx, VGAy

and VGAz, respectively. While, xin,1, yin,1 and zin,1 components are the inputs to the model. K and

52

M are nonlinearity order and memory depth, respectively. From the previous section, we can

conclude that the value of xin,1, yin,1 and zin,1 components, in 00-1200 tridant can be represented as,

120 240

,1 1 1 1 1 1 1

oj j

in in in inx A S B S e C S e (3.47)

120 240

,1 2 1 2 1 2 1

j j

in in in iny A S B S e C S e (3.48)

120 240

,1 3 1 3 1 3 1

j j

in in in inz A S B S e C S e (3.49)

where, A1, B1, C1, A2, B2, C2, A3, B3 and C3 are the constants whose values can be occupied from

Table 3.3 and Sin1 is the complex input signal. For simplicity, in further equations, values of Sin1,

Sin1ej120 and Sin1ej240 are replaced by S1, S2 and S3, respectively. Values of xin,1, yin,1 and zin,1 are

applied in equation (3.44), (3.45) and (3.46), respectively. The resultant equations are then

subjected to binomial theorem and can be represented as,

3 31 2 1 2

1 2 3

1 2 3

, 1 1 1 1 2 3

1 0

K Mi ii i i ix

out k m i i i

k m i i i k

x h A B C S S S

(3.50)

3 31 2 1 2

1 2 3

1 2 3

, 2 2 2 1 2 3

1 0

K Mi ii i i iy

out k m i i i

k m i i i k

y h A B C S S S

(3.51)

3 31 2 1 2

1 2 3

1 2 3

, 3 3 3 1 2 3

1 0

K Mi ii i i iz

out k m i i i

k m i i i k

z h A B C S S S

(3.52)

Value of Sout can be derived by substituting values of xout, yout and zout in equation (2.18) and can

be represented as,

31 2

1 2 3

03 31 2 1 2

1 2 3

1 2 3 031 2

1 2 3

, , 1 1 1

120

, , 2 2 2 1 2 3

1 0240

, , 3 3 3

ii ix

k m i i i

K Mi ii i i iy j

out k m i i i

k m i i i kii iz j

k m i i i

H A B C

S H A B C e S S S

H A B C e

(3.53)

53

where, 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑥 , 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑦 and 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑧 are the complex model coefficients which incorporates

𝛼𝑖1𝑖2𝑖3, 𝛽𝑖1𝑖2𝑖3

and 𝛾𝑖1𝑖2𝑖3, respectively.

As seen from Table 3.3, we know that B1=-B2 and C1=-C2, while values of A1 and A2 are distinct.

We also know that values of A3, B3 and C3 are 0 for this tridant. Therefore, equation (3.53) can be

represented as,

0

3 2 3 32 1 1 1 2

1 2 3 1 2 3

1 2 3

120

1 1 , , 1 , , 2 1 2 3

1 0

( 1)K M

i i i ii i i i ix y j

out k m i i i k m i i i

k m i i i k

S B C H A H A e S S S

(3.54)

Now, by substituting the vales of A1, A2, B1 and C1 from Table 3.3,

2 3 1 2 3

1 2 331 2

01 2 3 2 3

1 2 31 2 3

2 3 2 0

, , 1 1

1 1 2 33 2 2 0 1201 0

, , 1 1

sin ( )sin ( 120 )

( 1) sin ( )sin ( 120 )

i i i i ixK M

k m i i i ii ik

out i i i i ik y jk m i i i k

k m i i i

HS D S S S

H e

(3.55)

where, D1 represents the denominator in 00-1200, and can be represented as,

3 0 3

1 1 1sin ( 120 ) sin ( )D (3.56)

Ultimately, the modified memory polynomial for 0º-120º can be deduced as,

1 2

1 2

1 2

0

1 1out , , , in13 0 3

1 0 3 1 1

sin ( )sin ( 120 )( ) ' ( )

(sin ( 120 ) sin ( ))

j jK Mk

k m j j kk m j j k

S n G S n m

(3.57)

where, 𝐺𝑘,𝑚,𝑗1,𝑗2

′ are the complex predetermined model coefficients which incorporates 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑥 ,

𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑦, constants and all the phase rotations. Sin1(n) and Sout(n) are the complex input and output

signals, respectively. M is the memory depth and K is the nonlinearity order of the modified

memory polynomial.

54

3.3.2 Mathematical analysis for 1200-2400

Similarly, for 120º-240º, the forward behavioral model can be derived. In this tridant value of Sout

can be represented as,

31 2

1 2 3

03 31 2 1 2

1 2 3

1 2 3 031 2

1 2 3

, , 4 4 4

120

, , 5 5 5 1 2 3

1 0240

, , 6 6 6

ii ix

k m i i i

K Mi ii i i iy j

out k m i i i

k m i i i kii iz j

k m i i i

H A B C

S H A B C e S S S

H A B C e

(3.58)

where, 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑥 , 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑦 and 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑧 are the complex model coefficients which incorporates

𝛼𝑖1𝑖2𝑖3, 𝛽𝑖1𝑖2𝑖3

and 𝛾𝑖1𝑖2𝑖3, respectively.

For this tridant, we know that A5=-A6 and B5=-B6, while values of C5 and C6 are distinct. We also

know that values of A4, B4 and C4 are 0 for this tridant. Therefore, equation (3.58) can be

represented as,

0 0

3 3 31 2 1 2 1 2

1 2 3 1 2 3

1 2 3

120 240

5 5 , , 5 , , 6 1 2 3

1 0

( 1)K M

i i ii i i i i iy j z j

out k m i i i k m i i i

k m i i i k

S A B H C e H C e S S S

(3.59)

Now, by substituting the vales of A5, B5, C5 and C6 from Table 3.3,

01 2 3 1 2

1 2 331 2

01 2 31 2

1 2 31 2 3

2 3 20 0 120

, , 1 1

2 1 2 32 32 0 0 240

1 0, , 1 1

sin ( 240 )sin ( 120 )

( 1) sin ( 240 )sin ( 120 )

i i i i iy jK M

k m i i i ii ik

outi i ii ik z j

k m i i i kk m i i i

H eS D S S S

H e

(3.60)

where, D2 represents the denominator in 1200-2400, and can be represented as,

3 0 3 0

2 1 1sin ( 240 ) sin ( 120 )D (3.61)

Ultimately, the modified memory polynomial for 120º-240º can be deduced as,

1 2

1 2

1 2

0 0

1 1, , , in13 0 3 0

1 0 3 1 1

sin ( 120 )sin ( 240 )( ) '' ( )

(sin ( 240 ) sin ( 120 ))

j jK Mk

out k m j j kk m j j k

S n G S n m

(3.62)

55

where, 𝐺𝑘,𝑚,𝑗1,𝑗2

′′ are the complex predetermined model coefficients which incorporates 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑦,

𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑧 , all the constants and phase rotations. Sin1(n) and Sout(n) are the complex input and output

signals, respectively. M is the memory depth and K is the nonlinearity order of the modified

memory polynomial.

3.3.3 Mathematical analysis for 2400-3600

Similarly, for 2400-360º, the forward behavioral model can be derived. In this tridant value of Sout

can be represented as,

31 2

1 2 3

03 31 2 1 2

1 2 3

1 2 3 031 2

1 2 3

, , 7 7 7

120

, , 8 8 8 1 2 3

1 0240

, , 9 9 9

ii ix

k m i i i

K Mi ii i i iy j

out k m i i i

k m i i i kii iz j

k m i i i

H A B C

S H A B C e S S S

H A B C e

(3.63)

where, 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑥 , 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑦 and 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑧 are the complex model coefficients which incorporates

𝛼𝑖1𝑖2𝑖3, 𝛽𝑖1𝑖2𝑖3

and 𝛾𝑖1𝑖2𝑖3, respectively.

For this tridant, we know that A9=-A7 and C9=-C7, while values of B7 and B9 are distinct. We also

know that values of A8, B8 and C8 are 0 for this tridant. Therefore, equation (3.63) can be

represented as,

0

3 1 3 31 2 2 1 2

1 2 3 1 2 3

1 2 3

240

9 9 , , 7 , , 9 1 2 3

1 0

( 1)K M

i i i ii i i i ix z j

out k m i i i k m i i i

k m i i i k

S A C H B H B e S S S

(3.64)

Now, by substituting the vales of B7, A9, B9 and C9 from Table 3.3,

1 2 3 1 3

1 2 331 2

01 3 1 2 3

1 2 31 2 3

2 3 20 0

, , 1 1

3 1 2 32 3 20 0 2401 0

, , 1 1

sin ( 240 )sin ( 360 )( 1)

sin ( 240 )sin ( 360 )

i i i i ix kK M

k m i i i ii ik

out i i i i iz jk m i i i k

k m i i i

HS D S S S

H e

(3.65)

where, D3 represents the denominator in 2400-3600, and can be represented as,

56

3 0 3 0

3 1 1sin ( 360 ) sin ( 240 )D (3.66)

Ultimately, the modified memory polynomial for 240º-360º can be deduced as,

1 2

1 2

1 2

0 0

1 1, , , in13 0 3 0

1 0 3 1 1

sin ( 240 )sin ( 360 )( ) ''' ( )

(sin ( 360 ) sin ( 240 ))

j jK Mk

out k m j j kk m j j k

S n G S n m

(3.67)

where, 𝐺𝑘,𝑚,𝑗1 ,𝑗2

′′′ are the complex predetermined model coefficients which incorporates 𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑥 ,

𝐻𝑘,𝑚,𝑖1𝑖2𝑖3

𝑧 , all the constants and phase rotations. Sin1(n) and Sout(n) are the complex input and output

signals, respectively. As mentioned earlier, M is the memory depth and K is the nonlinearity order

of the modified memory polynomial. The number of coefficients required to generate this model

can be given by: 𝑁𝑡(𝐾×(𝑀 + 1)×(3𝐾 + 1)) where 𝑁𝑡 is the number of tridants. In our case, as

there are three tridants 𝑁𝑡 = 3, K is 3 and M is 2. This leads to the total number of coefficients

being 270.

Decomposition

00 + Φx

1200 + Φy

2400 + Φz

Phase

Mapping

Φx,Φy,Φz Filtering and

Compensation

Voltage

Mapping DAC

DAC

Iin

Qin

DSP

0o

240o

120o

Vx

Vy

Vz

x

y

z

Local

Oscillator

VSA

(Agilent E4440A)

Frequency

Down-convertorADC

Digital

Demodulator

Sout

Time Delay

Adjustment

Iout

Qout

Forward

Model

Iout_ta

Qout_ta

Iest

Qest

DAC

Decomposition

00,1200 ,2400

VGAx

VGAy

VGAz

Figure 3.5. Block schematic of mixerless three-way amplitude modulator-based

transmitter, analog combining architecture with signal processing.

57

Fig. 3.5 shows the block schematic of the transmitter architecture using analog combining along

with the digital signal processing blocks. Training sequence of 10k samples is used to extract the

coefficients using least square technique [45]. Coefficients are then applied to the whole input

sequence of 100k samples to estimate the output. The normalized mean square error (NMSE)

between estimated and measured output is calculated to evaluate the performance of the model.

The NMSE is calculated by using equation (1.5).

3.4 Model Extraction Algorithm

This section describes the steps involved in the calibration technique adopted for modeling all the

impairments of mixerless three-way amplitude modulator based transmitter.

The triadic complex memory polynomial mentioned in equation (3.57) for tridant 00-1200 can be

written as,

1 1

1

t t

out in S S G' (3.68)

Where 𝐒𝒊𝒏𝟏𝒕𝟏

can be represented in matrix form as,

1 2 1 2 1 2

1 2 1 2

0 0 01 11 1 1 1 1 1

1 1 11 1

1 1 1

0 01 11 1 1 1

1 11 1

1 1

sin ( )sin ( 120 ) sin ( )sin ( 120 ) sin ( )sin ( 120 )( ) ... ( ) ... ... ( )

sin ( )sin ( 120 ) sin ( )sin ( 120 )( 1) ... ( 1 ) .

11

j j j j j jK

in in inK

j j j j

in in

S n S n m S n mD D D

S n S n mD D

t

in

S

1 2

1 2 1 2 1 2

0

1 11

1

0 0 01 11 1 1 1 1 1

1 1 11 1

1 1 1

sin ( )sin ( 120 ).. ... ( 1 )

. . . .

. . . .

. . . .

sin ( )sin ( 120 ) sin ( )sin ( 120 ) sin ( )sin ( 120 )( ) ... ( ) ... ... ( )

j jK

inK

j j j j j jK

in in inK

S n mD

S n L S n L m S n L mD D D

(3.69)

Here, 𝐒𝒊𝒏𝟏𝒕𝟏 refers to the input samples and L refers to the training length.

Coefficient vector, Gʹ and output matrix 𝐒𝒐𝒖𝒕𝒕𝟏 for 00-1200can be represented as,

1 2 1 2 1 21,0, , 1, , , , , ,' ... ... ...

T

j j M j j K M j jG G G G (3.70)

58

1 ( ) ... ( 1) ... ... ( )Tt

out out out outS n S n S n L S (3.71)

Similarly, 𝐒𝒊𝒏𝟏𝒕𝟐

for 1200-2400 tridant and 𝐒𝒊𝒏𝟏𝒕𝟑

matrix for 2400-3600 tridant can be obtained.

After obtaining Sin1 matrix for each tridant, the general expression for the complete triadic complex

memory polynomial can be written as,

out in1

S = S ×G (3.72)

This equation can be represented in matrix form as,

0 0

0 0

0 0

1 1

2 2

3 3

t t

out in1

t t

out in1

t t

out in1

S S G'

S = S × G''

S S G'''

(3.73)

Using the Least Squares Estimation technique, the coefficient vector G is obtained as,

LS †

in1 outG S S (3.74)

where, †

in1S is the Moore-Penrose pseudoinverse of Sin1.

The coefficients thus obtained is multiplied with the complete input signal as shown in equation

(3.73) to get estimated output, 𝐒𝐨𝐮𝐭,𝐞𝐬𝐭

out,est in1 LS

S S G (3.75)

This estimated output is then compared to actual or measured output to evaluate the model

performance.

3.5 Implementation of mixerless three-way amplitude modulator-based transmitter

The Mixerless three-way amplitude modulator based transmitter is implemented using three analog

VGAs (ADL5330). The specifications of ADL5330 are given in Table 2.2. The evaluation of all

59

the three boards are depicted in Fig. 3.6. All the VGAs are powered by a 5V DC supply. Advanced

Design System (ADS) is used to generate complex baseband I/Q data. This complex baseband I/Q

signal is decomposed into three envelopes using three-coordinate decomposition algorithm and

then mapped to control voltages in MATLAB as described earlier. The three control voltages are

then downloaded to two different signal generators (ESG4438C) as each signal generator has only

two baseband outputs. Therefore, one signal generator (ESG-1) is used for generation of control

voltages Vx and Vy while the second signal generator (ESG-2) is used for generation of control

voltage Vz. Both signal generators are operated in synchronization. Another signal generator

(ESG4438C) is used as a Local Oscillator (LO). The signal generators and the LO are triggered in

synchronization. The analog gain control voltage Vx at the analog baseband output of ESG-1 is fed

to the gain control pin of VGAx. Similar procedure is used for VGAy and VGAz respectively. The

LO signal is fed to the input of a three-way power-divider (MACOM PN2090-6304-00) which has

loss of 7dB in each of the three branches and has frequency range from 0.5 GHz to 18 GHz. The

LO at the first output port of the power-divider is fed to the RF input port of VGAx. The LO at the

second output port of the power-divider is fed to a first phase shifter (ARRA 9428A) with

frequency range from DC-18 GHz, which rotates the LO by 120º. The output is then fed to the RF

input port of VGAy. The LO at the third output port of the power-divider is fed to a second phase

shifter (ARRA 9428A) which rotates the LO by 240º. The output of the second phase shifter is fed

to RF input port of VGAz. Finally, the RF outputs Xout, Yout and Zout are summed together using

power-combiner (MACOM PN2090-6304-00) to obtain the desired complex modulated RF signal,

which is captured and digitized using Power Spectrum Analyzer (PSA E4440A) and VSA

software, respectively. The time alignment is carried out using maximum correlation technique

[59]. To retrieve I/Q data from the captured signal, further signal processing is carried out in

60

MATLAB. Fig. 3.7 depicts the hardware implementation of mixerless three-way amplitude

modulator-based transmitter.

Figure 3.6. Implementation of mixerless three-way amplitude modulator-based

transmitter.

Figure 3.7. Hardware implementation of the mixerless three-way amplitude modulator-

based transmitter.

61

3.6 Measurement results

A LTE signal of 1.4 MHz bandwidth and Quadrature Phase Shift Keying (QPSK) constellation is

generated using ADS software to validate the proposed modeling technique and to evaluate the

performance of the proposed methodology. The LTE signal is oversampled by a factor of 16 and

the corresponding baseband signal has 100,000 samples which are sampled at a rate of 30.72

Msamples/sec. The complex baseband signal is then subjected to decomposition to a three-

coordinate system according to the three-way decomposition algorithm discussed earlier in this

chapter. Components obtained after decomposition and digital processing are then mapped to

control voltages and fed to the experimental setup described in the previous section. An LO signal

is generated at 2.2 GHz with a power level of -3 dB to feed the three VGA paths. The signal is

captured by a power spectrum analyzer and demodulated by VSA software followed by time

alignment algorithm implemented in MATLAB.

Table 3.4 Summary of performance for digital combining and proposed analog combining

SPECIFICATION IDEAL DIGITAL

COMBINING

PROPOSED ANALOG

COMBINING

Signal bandwidth 1.4 MHz 1.4 MHz

Number of testing samples 100,000 100,000

Number of training samples 10,000 10,000

Testing NMSE -36.41 dB -36.90 dB

Training NMSE -39.56 dB -40.97 dB

Nonlinearity order and Memory depth K=3, M=2 K=3, M=2

62

After capturing the output signal (measured signal) the derived TC-MP is used to estimate the

output signal (estimated signal). The input to the TC-MP model is original complex baseband I/Q

signal and output is the complex signal captured from the output of the transmitter. After obtaining

the required input and output signals, model identification is performed to acquire the modeling

coefficients and finally the modeled output. NMSE is then calculated between modeled output and

measured output signals. The summary of results of the performance evaluation of the tree-way

mixerless amplitude modulator based transmitter with ideal digital combining and the

implemented topology with analog combining is depicted in Table 3.4. These results show that the

proposed TC-MP model can replace the three MP models used in [39] to include the nonlinear

distortion and memory effects of each branch. In addition, this model considers any gain and phase

imbalance between the three different paths generated by the non-ideal analog combiner.

(a) (b)

Figure 3.8. Characteristics of modeled and measured output signals for digital combining

architecture: (a) AM-PM, (b) AM-AM

63

To validate the proposed model, in addition to the NMSE results, the AM-PM and AM-AM of the

modelled output and the measured output signals for the three-way transmitter implemented with

digital combining are demonstrated in Fig. 3.8 and the AM-PM and AM-AM of the modelled

output and measured output signals for the three-way transmitter implemented with analog

combining are shown in Fig. 3.9. The proposed TC-MP model can predict the full transmitter

behavior including nonlinearity and imbalance between the branches.

(a) (b)

Figure 3.9. Characteristics of modeled and measured output signals for analog combining

architecture: (a) AM-PM, (b) AM-AM

Moreover, the spectral representations of the modeled output, the measured output, and the error

signal for the three-way transmitter with digital combing and the three-way transmitter with analog

combining are shown in Fig. 3.10 and Fig. 3.11, respectively. From the graphs, we can conclude

that the proposed forward model works exceptionally well for the three-way transmitter

architecture whether the combining is ideal or implemented in analog. The spectra of the error

64

signals prove that in both cases, the out-of-band (nonlinear) and in-band (linear and nonlinear)

distortions are all modeled accurately.

Figure 3.10. Spectral response of modeled and measured output along with error signal for

the three-way transmitter implementation with digital combining.

Figure 3.11. Spectral response of modeled and measured output along with error signal for

the three-way transmitter implementation with analog combining.

65

3.7 Conclusion

In this chapter, mixerless three-way amplitude modulator-based transmitter ranging from 500 MHz

to 3 GHz is implemented completely using of-the-shelf RF components. Along with the

implementation, a novel TC-MP forward model is proposed to model the characteristics of the

three-way transmitter architecture and is validated using laboratory measurements. Since all the

branches are implemented and modeled simultaneously as a one-box system, the proposed model

considers the amplitude and phase imbalances between different branches. Furthermore, the

performance of the proposed model, evaluated in terms of various figures of merits, shows the

excellent modeling capability.

66

Chapter Four: Reverse Behavioral Modeling

4.1 Introduction

Variable Gain Amplifiers (VGAs) used in the mixerless three-way transmitter topology introduce

nonlinear Amplitude to Amplitude (AM-AM) and Amplitude to Phase (AM-PM) distortions as

shown in chapter two. Digital Predistortion (DPD) is an effective technique to compensate for the

nonlinear effects. Mitigation of nonlinear effects exhibited by VGAs in the mixerless three-way

amplitude modulator based transmitter is challenging because till now no general theory that

defines the relationship between the system’s input and output for such a topology exists [60]. In

addition, the unconventional signal decomposition prevents conventional predistortion algorithms

from performing accurately, especially in the presence of gain and phase imbalance.

VGAs are the primary source of nonlinear distortion in the mixerless three-way transmitter

topology. In general, nonlinearities result in distortions which include adjacent channels

interference caused by the intermodulation distortion that generates spectral regrowth [61], and

distortion of signal’s constellation or Error Vector Magnitude (EVM) degradation [62]. To avoid

these unwanted effects, DPD is widely used in literature to linearize power amplifiers and radio

frequency (RF) transmitters [60-63]. A digital predistorter is a functional block that precedes a

nonlinear Device Under Test (DUT), which in our case is the parallel combination of three VGAs.

A digital predistortor exhibits an inverse nonlinear response to that of the DUT. Digital predistorter

learning architectures for pre-inverse model identification can be classified into direct learning and

indirect learning architectures [63]. Direct learning means that the relation between input and

output of the DUT is estimated, and the predistortion is obtained directly by “pre-inverting” the

DUT characteristics [63]. Indirect learning means that a postdistorter first derives a post-inverse

of the DUT without placing any predistorter in the forward path. The postdistorter computes the

67

coefficients of the post-inverse model of the nonlinear DUT and copies them to the predistorter

with the aim of linearizing the system. In this thesis, digital predistorter based on indirect learning

architecture is used.

Fig. 4.1 shows the Digital Signal Processing (DSP) block of mixerless three-way transmitter and

the principle of implementation and operation of the DPD part, which is based on indirect learning.

Initially, the digital predistorter block is absent as explained earlier. The signal Sin1 is decomposed

into xin,1, yin,1 and zin,1 components along the 0°, 120° and 240° axes using three-way decomposition

algorithm as explained in earlier. An offset value is added to the components to ensure non-zero

values. Then, the components are subjected to digital filtering to avoid any discontinuities. Finally,

the xin,1, yin,1 and zin,1 components are mapped to generate control voltages for the VGA. The inputs

generated is then downloaded into the signal generators, which have built-in digital-to-analog

converters (DACs) and then fed to the gain control pins of the VGAs. The RF output from all the

three VGAs is then summed together to acquire Sout.

Digital

Predistorter

Sin1(n)

Decomposition

(00,120

0,240

0)

Filtering

Compensation

Voltage

Mapping

xin1

yin1

zin1

DACy

DACx

DACz

VGAy

VGAz

VGAx

DUT

`

Sout(n)

Postdistorter

e(n)

Sdpd

g(n)

+

_

Vx

Vy

Vz

Figure 4.1. Block schematic for the operation of digital predistorter based on indirect

learning.

68

As shown in Fig. 4.1, the postdistorter block first computes the post-inverse of the DUT by

identifying the post-inverse modeling coefficients. These coefficients are then copied to the

predistortion block placed before the DUT. The coefficients are updated after each iteration to

linearize the transmitter system.

4.2 Digital predistortion (DPD)

Fig. 4.2 shows the working of DPD technique to linearize the mixerless transmitter architecture.

Sin1

Forward

Model

Reverse

Model

Postdistorter

DUT

DUT

Input Output

Output

Sin1 Sout

Sin1 S'out

Sout S'in1

Sdpd

(a)

(b)

(c)

(d)

Figure 4.2. Predistortion and linearization.

Fig. 4.2 (a) shows that Sin1 acts as the complex input signal to the three-way mixerless transmitter

architecture and Sout acts as the complex output signal. Moreover, as seen from Fig 4.2 (b) for

forward modeling, when the input complex signal Sin1 acts as the input to the model then the output

signal is estimated as Sʹout. The input and output signals are swapped to obtain the reverse model

as explained and proved earlier. Thus, for the reverse model, as shown in Fig. 4.2 (c), when the

69

input is Sout then the output is estimated as Sʹin1. To generate a predistorted (postdistorted in this

case) signal, the reverse model coefficients are multiplied with the input signal as shown in Fig.

4.2 (d) which is then passed to the DUT after the three-way decomposition algorithm to obtain the

linearized signal.

4.3 Reverse model for mixerless three-way amplitude modulator-based transmitter

The nonlinear gain and phase responses of the VGAs and their corresponding memory effects can

be modeled using a TC-MP as shown in chapter three. The following section proves that the TC-

MP model can be successfully used for predistorting the mixerless three-way amplitude

modulator-based transmitter.

4.3.1 Triadic complex memory polynomial calibration

In this section, the aim is to obtain a reverse model by swapping the input and output signals. We

know that a conventional memory polynomial of nonlinearity order K and memory depth M, can

accurately model the nonlinearity and other imperfections of the VGA [38, 39]. Moreover, the

same memory polynomial can also be used to mitigate these imperfections [38, 39]. Consider a

forward model of mixerless transmitter as shown in Fig. 4.3. The conventional memory

polynomial model for VGAx, VGAy and VGAz can be represented as,

, 1

1 0

( ) ( )K M

k

out k m in

k m

x n h x n m

(4.1)

, 1

1 0

( ) ( )K M

k

out k m in

k m

y n h y n m

(4.2)

70

, 1

1 0

( ) ( )K M

k

out k m in

k m

z n h z n m

(4.3)

where, hk,m is the real predetermined calibration constant. M is the memory depth and K is the

nonlinearity order of the memory polynomial. xin,1, yin,1 and zin,1 are the input envelopes to VGAx,

VGAy and VGAz respectively. While, xout, yout and zout are output signals of VGAx, VGAy and

VGAz, respectively.

Figure 4.3. Forward model of the mixerless three-way amplitude modulator-based

transmitter.

From Fig. 4.3, it can be observed that if signal decomposition block is represented by transfer

function T, then the block characterized with dashed line can be represented by T -1 as its function

is opposite to that of signal decomposition block. The relation between decomposed input

components (xin,1, yin,1 and zin,1) and output signal (Sout), can be mathematically represented as,

1

1 ,1 2 ,1 3 ,1T f ( ),f ( ),f ( )out in in inS x y z (4.4)

Signal

Decomposition

VGAx

f1(x)

VGAy

f2(y)

VGAz

f3(z)

Sin1 Sout

xin,1

yin,1

zin,1

ej120

ej240

xout

yout

zout

ej0

T-1

T

T-Transfer Function

T-1- Inverse transfer function

71

where, f1(xin,1), f2(yin,1) and f3(zin,1) are the memory polynomial functions for VGAx, VGAy and

VGAz. Also, xin,1, yin,1 and zin,1 can be represented as a function of Sin1 as,

,1 ,1 ,1 1( , , ) Tin in in inx y z S (4.5)

This implies that the input signal (Sin1) can be translated to the output signal (Sout).

Figure 4.4. Reverse model of mixerless three-way amplitude modulator-based transmitter.

Now, consider a reverse model of a mixerless transmitter as shown in Fig. 4.4. As we can see, the

input and output signals are swapped with each other. Here, the relation between decomposed

input components (xout, yout and zout) and output signal (Sin1), can be mathematically represented as,

1 1 1 1

1 1 2 3T f ( ),f ( ),f ( )in out out outS x y z (4.6)

where, f1−1(𝑥𝑜𝑢𝑡), f2

−1(𝑦𝑜𝑢𝑡) and f3−1(𝑧𝑜𝑢𝑡) are the inverse memory polynomial functions for

VGAx, VGAy and VGAz.

Also, xout, yout and zout can be represented as a function of Sout as,

T-1

Signal

Decomposition

VGAx

f1-1

(x)

VGAy

f2-1

(y)

VGAz

f3-1

(z)

Sin1Sout

xin,1

yin,1

zin,1

ej120

ej240

xout

yout

zout

ej0T

T-Transfer Function

T-1- Inverse transfer function

72

( , , ) Tout out out outx y z S (4.7)

The above equations therefore demonstrate that the input signal (Sout) can be successfully translated

to an output signal (Sin1). However, the reverse model cannot be proven unless the inverse of

memory polynomial function f1(xin,1) is f1−1(xout) for VGAx, f2(yin,1) is f2

−1(yout) for VGAy and

f3(zin,1) is f3−1(zout) for VGAz. The inverse of each memory polynomial function has already been

established and supported by equation (4.1) for VGAx, (4.2) for VGAy and (4.3) for VGAz.

Therefore, the memory polynomial that is used in forward model for VGAx, VGAy and VGAz

should be used VGAx, VGAy and VGAz, respectively, in reverse model. Nonlinearity order might

be different for the memory polynomial used in reverse model. Hence, the reverse model can be

obtained by simply swapping the input and output signals as depicted in Fig. 4.4.

4.4 Implementation of the DPD system

Initial steps for implementation of a DPD system are similar to the implementation of forward

behavioral modeling, explained in section 3.4. As seen from Fig. 3.6 and Fig. 3.7, the RF output

signal is captured and digitized using spectrum analyzer. After capturing the RF output signal,

time delay adjustment is performed between the output signal and the input signal. By using the

input signal and the time adjusted output signal, forward behavioral model is obtained. The input

and output signals are swapped to obtain the reverse model. Therefore, the reverse model, when

00<θ1<1200 can be represented as,

1 2

1 2

1 2

0

1 11 , , , 3 0 3

1 0 3 1 1

sin ( )sin ( 120 )( ) ' ( )

(sin ( 120 ) sin ( ))

j jK Mk

in k m j j outkk m j j k

S n G S n m

(4.8)

Similarly, reverse model, when 1200<θ1<2400 can be represented as,

73

1 2

1 2

1 2

0 0

1 11 , , , 3 0 3 0

1 0 3 1 1

sin ( 120 )sin ( 240 )( ) '' ( )

(sin ( 240 ) sin ( 120 ))

j jK Mk

in k m j j outkk m j j k

S n G S n m

(4.9)

Likewise, reverse model, when 2400< θ1 <3600 can be represented as,

1 2

1 2

1 2

0 0

1 11 , , , 3 0 3 0

1 0 3 1 1

sin ( 240 )sin ( 360 )( ) ''' ( )

(sin ( 360 ) sin ( 240 ))

j jK Mk

in k m j j outkk m j j k

S n G S n m

(4.10)

where, 𝐺𝑘,𝑚,𝑗1 ,𝑗2

′ , 𝐺𝑘,𝑚,𝑗1,𝑗2

′′ and 𝐺𝑘,𝑚,𝑗1 ,𝑗2

′′′ are the complex model coefficients, K and M are the non-

linearity order and memory depth, respectively, Sout(n) is the output of the model and Sin1(n) is the

complex input.

Furthermore, reverse model coefficients are obtained using the least squares [45]. Additionally,

predistorted signal is obtained simply by multiplying reverse model coefficients with the input

signal. Predistorted signal is again decomposed into three branches using three-way decomposition

algorithm. These signals are mapped in control voltages using equation (2.8) and are fed to gain

control port of VGAs. Complex RF output is captured and is compared with the actual input

complex signal. Normalized mean square error (NMSE) is calculated to measure the in-band

performance while adjacent channel leakage ratio (ACLR) is calculated to measure out of band

performance of the mixerless transmitter.

4.5 Measurement results

To validate the proposed calibration technique and to evaluate the performance of the proposed

transmitter architecture, a Long Term Evolution (LTE) signal with Quadrature Phase Shift Keying

(QPSK) constellation is generated using ADS software. The LTE signal is oversampled by 16 and

the baseband signal has 100,000 samples, with a sampling rate of 30.72 Msamples/s. The complex

signal is subjected to decomposition and processing. The components thus obtained are mapped

74

to voltages and sent to the setup as described above. The local oscillator (LO) signal is at 2.2 GHz

and has a power level of -3 dBm. The measurement results are summarized in Table 4.1. The

results obtained show that a high-quality RF signal is produced at the output of the proposed

transmitter architecture. The NMSE value has improved by more than 25 dB after adopting digital

DPD technique. The ACLR value obtained ensures that the signal at the output of transmitter meets

the requirements of the LTE standard [64].

Table 4.1 Summary of performance evaluation of the proposed model

SPECIFICATION VALUE

Signal bandwidth 1.4 MHz

NMSE before digital predistortion -12.23 dB

NMSE after digital predistortion -38.63 dB

ACLR before digital predistortion 34.35 dBc

ACLR after digital predistortion 49.56 dBc

Nonlinearity order and Memory depth K=3, M=2

The spectral response of the LTE signal obtained after recombination is shown in Fig. 4.5. The

distortion in the signal is reduced through DPD. The proposed transmitter has no emissions over a

wide frequency range and does not require any filtering at the output. The VGAs operate over a

wide frequency range and thus the transmitter offers large RF bandwidth from 500MHz to 3GHz

and reconfigurability. The wideband spectral response of the mixerless transmitter architecture is

shown in Fig. 4.6. The LO frequency used in the proposed transmitter was 2.2 GHz. The proposed

75

topology does not have any spurious emissions over a wide frequency range. The second harmonic

of the LO (4.4 GHz) has a very low power. Hence, the mixerless transmitter architecture does not

require any filtering at the output. Therefore, the use of band-specific filters at the output of the

transmitter architecture can be avoided.

Figure 4.5. LTE signal spectrum comparison between input signal, output signal before

DPD and output signal after DPD.

Figure 4.6. Wideband spectral response of the proposed architecture.

-2.8 -1.4 0 1.4 2.8-55

-40

-25

-10

5

Input Power (GHz)

PS

D (

dB

m/H

z)

Input Signal

Output before DPD

Output after DPD

76

4.6 Conclusion

In this chapter, a new calibration technique was proposed to mitigate the significant gain and phase

imperfections introduced by the VGAs. A reverse model based on TC-MP was proposed to

alleviate the response of all the VGAs. The calibration technique was tested using the LTE signal.

The NMSE of the LTE signal obtained after recombination as compared to the original complex

signal was improved from -12 dB to -39 dB using DPD technique. The ACLR was improved to

50 dBc and ensured that the signal at the output of transmitter met the standard ACLR

requirements. Thus, the mixerless transmitter architecture does not have any spurious emissions

over a wide frequency range and does not require any filtering at the output. The large RF

bandwidth of the VGAs and the absence of filters make the transmitter design more reconfigurable

than the conventional topologies.

77

Chapter Five: Conclusion and Future Work

In this thesis, the wideband mixerless three-way amplitude modulator-based transmitter ranging

from 500 MHz to 3GHz was implemented using passive analog components such as power

splitter/combiner and phase shifter in analog domain. Instead of the three memory polynomials

that were used in each branch of the mixerless three-way amplitude modulator based transmitter

with digital combining [39], a one-box model, the triadic complex memory polynomial (TC-MP),

was proposed to imitate the behaviour of all the three variable gain amplifiers (VGAs) along with

passive components. Additionally, predistortion using the TC-MP model was proposed to mitigate

the imperfections in the VGAs. Moreover, low error values were attained when measurements

were performed using long term evolution (LTE) signals. The low error values, thus, ensured the

high-quality performance of the architecture and the digital predistortion technique. The spectral

quality of the radio frequency (RF) signal at the output of the mixerless three-way amplitude-based

modulator transmitter architecture was evaluated using adjacent channel leakage ratio (ACLR)

measurements. Furthermore, the ACLR of LTE signal at the output of the transmitter met the

requirement of the LTE standard. Also, the absence of band limiting filters brought the transmitter

design a step closer to reconfigurable radios. However, as shown in section 3.3, the proposed

modeling technique requires 270 coefficients to generate the model. When compared to other

methods present in literature, which generally require 40 to 50 coefficients to model a complete

transmitter including PA, this is high number of coefficients that leads to an increase in the

processing complexity when implemented on a chip.

78

5.1 Contributions

The contributions of this thesis are,

I. In this thesis, a new transmitter architecture using three-way amplitude modulation has

been implemented with all the components placed in analog domain. Three variable gain

amplifiers act as envelope modulators and translate the baseband IQ complex signal to

RF without using mixers and phase modulator circuits. Apparently, new decomposition

algorithm and forward behavioral model using augmented memory polynomial have been

proposed. The theory of operation, implementation and performance evaluation of this

transmitter architecture have been summarized in a peer reviewed journal, along with the

results and the research findings.

J.Chatrath, M.Aziz and M. Helaoui, “Modeling of Mixerless Three-Way

Amplitude Modulator Based Transmitter using Triadic Complex Memory

Polynomial”, IEEE Trans. Microwave. Theory Tech., 2017, submitted.

II. To model the imperfections of VGA’s and other passive component of mixerless three-

way amplitude modulator-based transmitter, a new calibration technique was proposed.

Furthermore, digital predistortion technique was used to linearize the response of

mixerless three-way amplitude modulator-based transmitter. The research findings and

the measurement results have been summarized in peer reviewed letter.

J.Chatrath, M.Aziz and M. Helaoui, “Reverse Modeling of a Three-Way

Amplitude Modulator Based Transmitter using Triadic Complex Memory

Polynomial”, in preparation.

79

5.2 Future work

Research activities that can be carried out in the future includes;

I. Mixerless three-way amplitude modulator-based transmitter architecture along with all

the passive components in analog domain was implemented in this thesis work. The

forward and reverse model proposed in this thesis uses a new model, the TC-MP model.

While this model performs perfectly, higher number of coefficients is required, which

increases the complexity of implementation and limits the maximum nonlinearity and

memory orders that can be set for the model. Other modelling techniques, such as neural

networks and fuzzy logic, as well as complexity reduction techniques such as sparse

polynomials can be explored to linearize the mixerless transmitter architectures that are

efficient and reliable.

II. During the modeling operation, the values of nonlinearity order (K) and memory depth

(M) were swept for different combinations of K and M. Ideally, those values of K and M

should be selected for which the lowest value of normalized mean square error (NMSE)

between modeling and measured outputs is achieved. Generally, best NMSE is achieved

for higher values of coefficient. However, the higher the values of K and M, the higher

will be the number of modeling coefficients. Therefore, efforts can be made to achieve

best NMSE along with sustaining lower number of coefficients.

80

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