uk asynchronous forum, september 2008 1 synthesis of multiple rail phase encoding circuits andrey...

UK Asynchronous Forum, September 2008

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Synthesis of multiple railSynthesis of multiple railphase encoding circuitsphase encoding circuits

Andrey Mokhov, Crescenzo D’Alessandro, Alex Yakovlev

Microelectronics System Design Group, School of EECE, Newcastle University, UK

{andrey.mokhov, crescenzo.dalessandro, alex.yakovlev} @ ncl.ac.uk


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Outline

Phase encoding Conditional partial order graphs Circuit synthesis

Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder

Conclusions and future work

Outline


3Phase encoding

Phase encoding• Self-synchronous data communication protocol introduced

by D'Alessandro et al [ PATMOS’05 ]PATMOS’05 ] Reliability to single event upsets High information capacity No scalable implementations of multiple rail controllers

‘abdc’ symbol

4-wire channel: 4! = 24 symbols > 24 = 16 binary symbols

log(n!) ≈ n·log(n)

sensitiveinterval


4Phase encoding

Comparison with DI communication protocols


5Phase encoding

n-wire phase encoding channel


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Outline




Outline


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Conditional Partial Order Graphs


[ DATE’08 ]


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Controllers synthesis using CPOGs


• CPOG model can be used for phase encoding controllers specification and synthesis:

– Vertices correspond to the signal transitions in the channel– Conditional arcs determine the order of the transitions

• 2-wire phase encoder specification example:


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Outline




Outline


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Phase detector

• Decodes phase encoded symbols by detecting the relative order between all the pairs of transitions

• Consists of n(n-1)/2 mutual exclusion (mutex) elements

Circuits synthesis


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Outline




Outline


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Matrix phase encoder

• Generates phase encoded symbols given the matrix X = {xkj} of pairwise comparisons of the output transitions

Circuits synthesis

1 → 2 → 31 → 3 → 22 → 1 → 32 → 3 → 13 → 1 → 23 → 2 → 1


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Matrix phase encoder (implementation)

Circuits synthesis


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Matrix phase encoder (implementation)

Circuits synthesis


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Outline




Outline


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One hot phase encoder• Generates phase encoded symbols given one hot data X = {x1…xn!}

Circuits synthesis

# Control signals

Order

1 (1,0,0,0,0,0) a, b, c

2 (0,1,0,0,0,0) a, c, b

3 (0,0,1,0,0,0) b, a, c

4 (0,0,0,1,0,0) b, c, a

5 (0,0,0,0,1,0) c, a, b

6 (0,0,0,0,0,1) c, b, a


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One hot phase encoder (logic optimisation)• The synthesised CPOG can be optimised

Circuits synthesis


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One hot phase encoder (controller)

Circuits synthesis


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Outline




Outline


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Binary phase encoder

Circuits synthesis

• Data is normally given in binary form• Binary phase encoder generates phase encoded

symbols given binary encoded data


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Outline




Outline


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• The work presents a scalable approach for synthesis of multiple rail phase encoding circuits

• The approach uses the CPOG model in order to avoid exponential explosion of STG specifications due to duplication of events

• Phase encoders are synthesised for matrix, one hot, and binary source encodings, but the approach can be easily adapted for the other encodings e.g. m-of-n encoding

• The future work includes the development of automated synthesis tools based on the presented theoretical techniques


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End

Thank you!Questions?


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STG specification explosion

x1 x2 Handshake sequence

1 0 1 -> 2

0 1 2 -> 1


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x1 x2 Handshake sequence

1 0 1 -> 2

0 1 2 -> 1


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First scenario


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First scenario

Second scenario

Event duplication!


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+ Reduces event duplication

+ Can be synthesised

automatically (e.g. Petrify)

– Difficult for manual design

– Not visual

– Contains a lot of additional

places to track the choices

– Very time consuming to

generate


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End

Thank you!More Questions?

uk asynchronous forum, september 2008 1 synthesis of multiple rail phase encoding circuits andrey...

Documents

relative order

hot data x

future workoutlineconclusions

future workthe work

crescenzo dalessandro

dalessandro et

matrix x

binary symbolslogn