Ultra High Speed Digital Down ConverterDesign for Virtex-6 FPGAs

Joachim Meyer∗, Simon Menzel∗, Michael Dreschmann∗, Rene Schmogrow†, David Hillerkuss†,Wolfgang Freude†, Juerg Leuthold† and Juergen Becker∗

∗Institute for Information Processing Technologies†Institute for Institute of Photonics and Quantum Electronics

Karlsruhe Institute of Technology, Karlsruhe, GermanyEmail: joachim.meyer@kit.edu

Abstract— This paper describes the design and optimiza-tion of an ultra- high speed Digital Down Converter (DDC)for a realization by FPGAs. After explaining the generalstructure of the Digital Down converter we describe in detailhow to implement such a design in order to process a digital,massively parallelized signal. The necessary optimizationsto achieve an efficient implementation in state of the artFPGAs are explained and a case study for an FPGA optimizedDigital Down Converter design suitable for OFDMA systemsis presented. The key components of this DDC are highlyparallelized half-band filters which are optimized for Virtex-6 FPGAs and enable the design to decimate a 6 bit wide inputsignal with a sample rate of 25 GS/s into a 16 bit 1.5625 GS/ssignal while achieving an attenuation of around 35 dB. Theresults include the resource consumption of the DDC for aVirtex-6 XC6VHX380T FPGA as well as the filter responseto a chirp test signal.

Index Terms— FPGA; DDC; OFDMA; FIR; Decimator

I. INTRODUCTION

While Orthogonal Frequency Multiplexing (OFDM) isdeployed in many of today’s wireless communicationsystems for years, recently research groups all over theworld started to investigate OFDM for its benefits inoptical communication systems, compare [1]. Especiallythe advantages of Orthogonal Frequency Division Multi-ple Access (OFDMA) seem promising for optical accessnetworks of the future [2].

OFDMA systems can increase the flexibility of band-width allocation by forming independent channels usinga subset of subcarriers. An advantage of this approachis that a receiver might discard all subcarriers he is notinterested in, before he processes the signal. By doing so,successive signal processing stages benefit from relaxeddata rate requirements and therefore reduced costs. Thenecessary preprocessing can either be implemented byanalogue components or digitally by a Digital Down Con-verter (DDC). The advantages of a digital implementationinclude the absence of tolerances as well as the absenceof deterioration.

Using state of the art Analogue-Digital-Converters(ADCs) combined with state of the art Field Pro-grammable Gate Arrays (FPGAs) makes it possible todirectly process optically received OFDM signals. This

paper explains how to optimize the structure and thelow level implementation of a DDC design in order tosuccessfully process optically received OFDM signalswith a sample rate of up to 25GS/s.

II. RELATED WORK

Digital Down Converters can play an important rolein OFDM systems and therefore many research groupsdeal with the efficient design of DDCs for such systems,compare [3] and [4]. A general DDC implementationwith up-to-date FPGAs is described in [5]. However, allof these digital down converters are designed to handlesample rates in the area of several tenths of mega samplesper second. Research results for digital down converterswhich are able to process data rates in the two-digit GS/sdomain are rather rare. The reason for this is the complexand resource intensive design of appropriate ultra-highspeed low pass filters which have to process multiplesample samples per clock cycle since their own operatingfrequency is much lower than the sample frequencies.

In [6], Dinechin et al. demonstrated an approach for a20 GS/s ultra-high speed FIR filter based on two hardwareimplementations of the (i)FFT algorithm. While achievinggood results, they needed almost all resources providedby the biggest high-end Stratix 4 FPGA of the GX-Family (100% of the DSP resources, 100% of the M9Kresources, and 92% of the logic resources). Thereforeit gets obvious that this approach cannot be used ina DDC since there would be no resources left to addthe remaining components of a DDC, e.g. numericallycontrolled oscillators. Integrating even more than one ofsuch filters into a single FPGA is out of question.

III. IMPLEMENTATION

Digital Down Converters (DDC) are used in electricalcommunication systems in order to translate a real signalwhich is centered at an intermediate frequency, into acomplex signal, centered around baseband. To achievethis, a DDC consists of three stages. Stage one is formedby Numerically Controlled Oscillators and digital mixers.They are used to multiply the received signal with the

output of the NCO in order to shift the signal spectrum tobaseband. In Stage two appropriate digital low pass filtersremove frequencies higher than the highest frequencyof the signal of interest. Finally the last stage usuallyreduces the sample rate in order to relax processingspeed requirements for the successive signal processingcomponents. Compare figure 1.

NCO

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Fig. 1. Block diagram of a Digital Down Converetr (DDC)

A. Digital Filter and DecimationIn order to design a filter which is capable of processing

data in parallel to achieve very high data rates, the filterhas to be realized as a polyphase filter. While usually Cas-caded Integrator-Comb (CIC) filters are a good choice dueto their linear phase response and their resource efficientimplementation without requiring multipliers, their recur-sive design inhibits an efficient polyphase implementation.A parallel implementation would require a high numberof additional register chains to store intermediate feedbackterms. Since this would result in inacceptable resourceconsumption, we decided to use a polyphase FIR-filterapproach for the DDC.

When designing the filter it is possible exploit thatthe signal will be downsampled after the filter anyway.By moving this decimation into the filter, it is possibleto remove several processing paths leading to sampleswhich will be removed. The analysis of different mul-tistage polyphase FIR filter decimators lead us to a four-stage half-band filter decimator structure. Half-band filtersprovide a linear phase response and can be implementedvery efficiently [7]. On one hand the first stages of half-band filters can be applied resource friendly with largerripple and less complexity since the passband-to-samplingfrequency ratio is relatively small. On the other hand,since half of the coefficients are zero and the other half issymmetric, even high order half-band filters require onlya small amount of resource intensive multiplications.

B. Mixing StageFor a complete parallel working ultra-high speed DDC,

in addition to the filters, it is required to parallelize theNumerically Controlled Oscillators (NCO) in the mixingstage. In this configuration an NCO does not accumulatethe phase difference between two samples of the target fre-quency but the phase difference times the number of NCOcollaborating. By starting every NCO with an aligned butdifferent offset, the NCOs generate a frequency higherthan their own clock frequency.

C. Efficient usage of FPGA resources

To implement a DDC efficiently in modern Virtex-5or Virtex-6 FPGAs, it is required to make sure to mapthe operations efficiently on appropriate elements of theFPGA, especially for those of the multistage polyphaseFIR Filter decimator. One optimization is the proper usageof ternary adders. In modern Virtex FPGAs, the 6-inputLUT architecture can efficiently create an addition of 3numbers using the same amount of logic resources asa simple 2-input addition [8]. This becomes very usefulfor the adder trees of digital filters which add up all thesingle results. Additionally such ternary adders can beused to build the low-complexity half-band filters of thefirst stages without multiplications and without utilizingthe native Digital Signal Processing (DSP48E1) elementsin order to save them up for the complex latter stage half-band filters.

Fig. 2. Block diagram for an 19th-order FIR filter

Another critical optimization is the proper usage of theDSP48E1 slices in modern FPGAs [8]. Those slices con-tain a 25x18 bit multiplier, as well as a pre-adder, a post-adder and several registers which can become very usefulto achieve high clock rates via pipelining. The coefficientsof FIR filters with a linear phase response (e.g. halfbandfilters) are symmetric and therefore every coefficient existstwice in the system (with the exception of the middlecoefficient for an odd number of coefficients). While thepre-adders can now be used to combine both sampleswhich will be multiplied by the same coefficient, postadders can be used to already implement the first stage ofthe adder tree for the system. Figure 2 shows an example

implementation of an ordinary 19th-order FIR filter. Thefilter can be implemented by a combination of DSPs andtheir pre-/post-adders (add mul and add mul add), ternaryadders (tern add) and flip-flops (reg bal) for pipelining thefilter.

IV. EXPERIMENTS AND RESULTS

In our case study, we want to implement at least twofull DDCs in a single Virtex-6 XC6VHX380T FPGA. Theinput data arrives at 25 GS/s from the analogue digitalconverter (e.g. Vega ADC 30 from Micram). The systemclock of the FPGA was chosen to be 195.3125 MHz,therefore it is required to process 128 samples per clockcycle. A DDC should implement a decimation of the factorof 16, from 25 GS/s to 1.5625 GS/s, while the minimumattenuation of the stop-band should be 30 dB.

Fig. 3. Block diagram of the implemented ultra-high speed DDC

The complete DDC design consists of a NCO which isimplemented 128x parallel, an in-phase path as well as aquadrature-phase path. Each path contains 128 multiplierto multiply the output NCOs with the input signal and a4-stage polyphase half-band filter, compare figure 3.

The order of each single halfband filter of each stagewas determined with the methods described in [7]. Forthe filters of the first two stages, the attenuation of low-complexity 3-tap halfband filters is sufficient. Such filterscan be implemented very efficiently by ternary adders andtherefore utilizing only basic logic blocks of the FPGA,compare figure 4).

Fig. 4. The low-complexity 3-tap halfband filters can be implementedresource efficiently by the use of a ternary adder

For the third-stage a 7-tap filter is required in order tofulfill the attenuation requirements. When using scaling tonormalize the middle coefficient to one, such a filter can

be implemented by two DSP48E slices and few registers,compare figure 5. All coefficients have a resolution of sixbits.

Fig. 5. By exploiting the pre-adder and post-adder of DSP48E slices,the 7-tap halfband filter can be implemented without using additionaladder trees

The fourth and last stage implements the most complexhalfband filter. This is necessary since the size of thetransition band should be as small as possible. In ourdesign we created a filter of the order 30 by usingthe equiripple method [9]. The coefficients are storedwith a resolution of 8 bit, the structure of the FPGAimplementation is shown in figure 6.

Fig. 6. The 30th-order halfband filter of the last stage is the mostcomplex filter in the design

In order to verify and test the filter we ran simulationsusing Modelsim, a HDL Simulator from Mentor Graphics,in combination with Matlab. A chirp signal from 0-12.5GHz was generated in Matlab and exported into Modelsimwhich was used to simulate our decimator. Afterwards, theresults were imported by Matlab for verification. Figure7 shows the filter response to the chirp signal. It is easyto identify the stop-bands of the different filter stages.The attenuation of the stop-band for the complete filter isaround 35 dB.

Figure 8, 9, 10 and 11 show the spectra of each of thecreated halfband filters. The passband and the stopbandare highlighted for each implementation. It is importantthat the filters provide a good attenuation for these areas.

Fig. 7. The filter response of the 4-stage polyphase halfband filter to chirp signal 0-12.5 GHz cosimulated using Matlab and Modelsim.

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Fig. 9. Spectra of the 2nd-order halfband filter used in stage 2. Whilethe filter is basically the same as in the first stage it differs by thecoefficients.

While for the first filter stages it is very easy to fulfillthis requirement, it gets harder with every stage. Thefrequencies are normalized to 16 GHz in order to illustratethe decimation rate of 16 for the combined filter.

Table I compares the resource consumption of onecomplete digital down converter to the resources availablein a Virtex-6 XC6VHX380T device. As you can see,the resource consumption of DSP48E slices and ordinaryslices, representing the most critical resources for digitalfilters, is very balanced. This ensures to avoid a situationwhere the lack of one specific resource type prevents fromimplementing further digital down converters in the sameFPGA. We were able to place and route three complete

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Fig. 11. Spectra of the high complexity 30th-order halfband filterdeployed in the last stage.

DDCs (including in-phase and quadrature-phase path) ina single Virtex-6 XC6VHX380T device and still meet thetiming-constraints. While theoretically there are enoughresources to implement a fourth DDC, such a design isnot routable.

V. CONCLUSION

In this work we describe the implementation of an ultra-high speed digital down converters on modern Field Pro-grammable Gate Arrays in order to enable the deploymentin OFDMA-based communication systems. We explainhow to efficiently build a massively parallelized designusing multistage polyphase halfband filters and we show

TABLE IRESOURCES UTILISATION FOR A COMPLETE DIGITAL DOWN

CONVERTER

Resource Type One DDC Design XC6VHX380T %

LUT 29 424 239 040 12 %Register 40 654 478 080 8 %Slices 13 853 59 760 23 %

DSP48E1 192 864 22 %

in detail, how to optimize the critical components for up-to-date FPGA technology.

While most other systems are capable of handling datarates of several MS/s, our results show that it is possible touse a design like described in this work to build systemswith the capability of processing data rates of up to25GS/s. Additionally the developed digital down converteris designed in a way, allowing to implement up to threeof them into one single device.

ACKNOWLEDGMENT

The authors acknowledge support from the BMBFjoint project CONDOR, the EU research project ACCOR-DANCE, and the Xilinx University Program (XUP).

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