Ultra Low-Power Full-Adder for Biomedical ApplicationsEng Sue Chew, Myint Wai Phyu, and Wang Ling Goh*

Abstract-Addition is an essential function in fundamentalarithmetic operations. It is also the most copiously usedoperation in application-specific processors and digital signalprocessing application (DSP). In this paper, we propose a novel17-transistors full-adder based on the N-12T full-adder, whichhas a maximum of one threshold voltage (~) degradation foroutput voltage levels. The performance of the proposed full­adder is compared against other low-power full-adder viaextensive HSPICE simulation using 100 random input vectors.The simulation results show that the proposed design permitsthe use of lower operating voltage to derive lower powerconsumption and hence, the power delay product (PDP). Theadvantages of the proposed full-adder has been evaluated byintegrating the proposed full-adder into a multiplier-less finiteimpulse response (FIR) filter that is commonly used in themultirate filter bank for biomedical applications.

I. INTRODUCTION

Integrated circuits (ICs), particularly the complementarymetal oxide semiconductor (CMOS) ICs, are playing an ever­increasing role in implantable biomedical systems. ICs mustbe designed to satisfy rigorous reliability and redundancy, notforgetting the error-checking requirements that are associatedwith life-sustaining medical devices. Both the low-voltageand low-power operations are also obligatory for battery­powered systems that may be implanted for as long as tenyears.

The equipments used in biomedical signal processingare often influenced by noise. Hence, the resulting imagesmay not provide the quality needed for desire analysis.Digital linear filtering is the method used to removedisturbances in real time. Full-adder with low operatingpower and low power consumption is important in thewavelet filter bank implementation since addition is one ofthe main operations in the fmite impulse response (FIR) filter.

The major components of power consumption in digitalCMOS VLSI circuits are:• Switching power - consumed in charging and discharging

of the circuit capacitances during transistor switching [1].• Short-Circuit power - caused by short-circuit current

switching transient [1].

The switching power and short circuit power arecollectively called the dynamic power, which contributemainly to the total power consumption in the digital VLSIsystem, and can be defmed as that shown in Equation (1) [1].

*emai1: ewlgoh@ntu.edu.sg

where V DD is power supply voltage, Vswing is the voltageswing of the output which is ideally equal to V DD , C10ad isload capacitance at output node V out, f is system clockfrequency, a is switching activity at node V out, and I sc is short­circuit current at node V out• The summation seen in Equation(1) refers to all the node capacitances of the circuit [1].

(7)

(8)

(4)(5)

(6)

(2)

(3)

Y=A~B

Sum = YE9Cin

c; =A·B+Cin·Y

Sum =H ·C; '+H'· C;

c: =A·H'+Cin·H

Sum =(A ~ Cin)·CouT +(A ~Cin)·B

Cout =(A~Cin)·B+(A~Cin)·A

The ultra low-power full-adder (ULPFA) [4] is based onthe 4-transistor low-power XOR gate and ultra low-power(ULP) diode. Low-logic level ultra low-power (ULP) dioderestorer is used to restore the weak logic 0 for the inputsignals with combination of (0, 0). The leakage current of thestandard diode is reduced when the transistors are reversedbiased and operate with negative Vgs voltages.

The output of Complementary and level restoring carrylogic (CLRCL) [5] full-adder is shown as below:

Hybrid full-adder [3] can also be divided into three sub­modules. The intermediate XOR and XNOR functions aregenerated separately using different sets of transistors so as toreduce the probability of producing spurious switching andglitches. Weak logic signal caused by the transistors isrestored by the two complementary feedback transistors. Thelogical expressions for the intermediate signals and output aregiven as below:

II. REVIEW OF EXISTING LOW-POWER I-BIT FULL-ADDER

Several full-adder circuits featuring low-voltage and low­power have been published. The Sumeer Goel's full-adder[2], which is designed using the hybrid-CMOS design style,provides freedom in the selection of modules within a circuit,depending on application. It can be broken down into threemodules: the XOR and XNOR intermediate signals areproduced in Module I and are passed on to Module II andModule III for the generation of the Sum and Cout outputs.The Sum and Cout outputs are formed using the followingexpressions [2]:

(1)~otal =Pswitching + ~hort

=f ·C10ad L i Vswing • a, ·VDD + VDD L i Isc

*Assoc Pro/Wang Ling Goh is with the School o/EEE, NanyangTechnological University, Singapore.

978-1-4244-4298-0/09/$25.00 ©2009 IEEE115

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The CLRCL full-adder [5] is a low complexity circuit , soas to achieve faster cascade operation. Proper level restoringtechnique with the inverter is used to solve the multiplethreshold voltage fit losses problem in the carry propagatechain.

The N-12T full-adder [6] generates its Sum and COUI

outputs using the pass-transistor logic style. The advantage ofthis full-adder is that the fit loss does not propagate to theoutput even if the inputs of the XNOR gates suffer a fit losswhen it is applied to input B. Circuit diagrams of the full­adder just described are all presented in Figure I .

A

B~:::::'--=L--W-W

(e) N-I2T Full-adder [6]

Figure I. Low-power full-adder cells .

Sum

IV. SIMULATION RESULTS AND DISCUSSION

The circuit simulation works are carried out using 100random input vectors with HSPICE simulator. The sizes of allthe transistors in the circuits discussed are optimized suchthat the circuits dissipate the lowest power. The simulationsetup is shown in Figure 3. Worst-case delay, average powerconsumption, power-delay product (PDP) and comersimulation are used to evaluate the performance of thecircuits .

Figure 4 illustrates the power consumptions of the full­adder at different supply voltages . At 1.8 V, the proposedfull-adder consumes approximately 23%, 36%, 60% , 13%less power than the Sumeer Goel's full-adder, hybrid full­adder , ULPFA and CLRCL full-adder, respectively, but 34%more than the N-12T full-adder . However, at a power supplyof 1.2 V, the proposed full-adder dissipates about 20% and

III. PROPOSED FULL-ADDER

Previous N-12T full-adder does not operate correctly at lowpower supply due to the accumulation of VI losses. Here, wepresent a solution by modifying the N-12T full-adder so thatfor the worst-case scenario where A = ' I' and B = 'I ', XNORoutput is able to achieve full-swing instead of having VixrV»By connecting the gate of the level restoring pMOS to theoutput of XOR function, for every XNOR output with a VIloss, the logic '0 ' of XOR will tum on the pMOS and pull thedegraded XNOR output to VD[).

The Sum output of N-12T full-adder has a maximum ofone fit loss. The pass transistor logic is substitute by thetransmission gate so to ensure full voltage swing at the sumoutput. These modifications have increased the total numberof transistors to 17 (see Figure 2).

Figure 2. Proposed full-adder .

Sum

Sum

SumB--t-r--t

A

(c) ULPFA [4]

(b) Hybrid full-adder [3]

A -I---.......---f

Cin _r--------.

B--t:==~

B ---.....,..-..... L.-+---COUI

L __--.J===:f---- COUI

(a) Sumeer Goers full-adder [21

B--t:==~

(d) CLRCL full-adder [5]

A,-------,.~"'--I_

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24% less power if compared to the Sumeer Goel's full-adderand hybrid full-adder, respectively.

Randominput

genera tor

A Sum

Figure 6 shows that proposed full-adder can achieve thelowest PDP at 1.2 V. The proposed full-adder exhibits animprovement of 20% and 22% of PDP than Sumeer Goel'sfull-adder and hybrid full-adder, respectively, at 1.2 V. At 1.5V, the proposed full-adder demonstrates 57% and 14% lowerPDP than the ULPFA, CLRCL full-adder, respectively, but38% higher than the N-12T full-adder.

PDP results in the I -bit full-adder200

Power co nswnp no n results in the l·b it full-adder

100

150

Figure 6. PDP results in full-adder.

1.8V l .5V 1.2VS unulv veItaee

DSum eer Goel's FA E1H ybridFA ~ULPFA

rnCLRCLFA DN-12T FA faPropo sedFA

50

o20

15

10

5

o

25tF ~

Figure 3. Simulation testbench.

1.8V I .5V 1.2VSupp I}' voltage

DSumeer Go el's FA ~HybridFA i1iIULPFA

rnCLRCLFA IIJN-1 2T FA f2Propo sedFA

Figure 4. Power results in the full-adders at different supply voltage.

The cell delay is measured at the instant when the inputreaches 50% of the voltage supply level (after the inputbuffers) to the same 50% voltage level of either the Sum orC aul signals, whichever the later (before the output buffers)[2]. Figure 5 depicts the delays of the variants full-adders atpower supplies of 1.8 V, 1.5 V and 1.2 V. When operated at1.2 V, the proposed full-adder illustrates an increment ofroughly 1% and 2% in delay when compared to the SumeerGoel 's full-adder and hybrid full-adder, respectively.

Deb. results in the I-bit full-adder

10.610.510.4

10.3

10.210.1

109.9

Comer simulations are used to investigate the differencesdue to process inaccuracies, temperature and other parametervariations. Hence, comers simulation is essential to check theinfluence of the parameter variations on IC. In the MOSFETmodel library, comers such as Fast nMOS Fast pMOS, SlownMOS Slow pMOS, Fast nMOS Slow pMOS, Slow nMOSFast pMOS and typical nMOS typical pMOS are included inthe process kit. Table I tabulated the power consumption ofFast nMOS Fast pMOS, Slow nMOS Slow pMOS and typicalnMOS typical pMOS comers of the proposed full-adderrespectively. At a power supply of 1.2 V, the proposed full­adder shows difference of 3.46% and 8.05% between FastpMOS Fast nMOS to typical nMOS typical pMOS and SlownMOS Slow pMOS to typical nMOS typical pMOS.

V. IMPLEMENTATION INTO THE FIR FITLER

To evaluate the effectiveness of the proposed full-adder,the proposed design has been embedded into a wavelet filterbank. The proposed full-adder is designed in the form of soft­macro. Filter's constant coefficient multipliers are usuallyimplemented in hardware using a sequence of shift and addoperations, where the multiplication operations can be avoidedsince the filter coefficients can be represented as numbers ofpower of two. From [7], the coefficients of the low-pass andhigh-pass filters can be reproduced as shown in Equations (9)and (10).

1.8V

OSumeerGoel' s FA

rn CLRCLFA

1.5VSupplyvultage

E3H ybridFA

QlN-I2TFA

1.2V

lSlULPFA

C!:lProposedFA

LPF :H(z)=!..+~Z-1 +~Z-2 +!"Z-38 8 8 8

LPF:G(z)= 2-2r l

(9)

(10)

Figure 5. Delay results in full-adders of different supply voltages.

PDP is the product of average power consumption andworst case delay of the full-adder, and is used to demonstratethe trade-off between the power consumption and delay .

Presented in Figure 7 is the wavelet filter bank that fmdsmany applications in biomedical signal and image processing.The main idea of using the filter banks is to separate thefrequency domain of the signal under consideration, into twoor more signals, or to combine two or more different signals

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into single signal. Filter circuits engaged within the waveletfilter bank are illustrated in Figure 8 [7].

TABLE 1.RE SULTS OF CORNERS SIMULAnONS OF THE FULL-ADDERS .

The proposed full-adder is implemented into the waveletfilter bank so to explore its advantage in the battery-poweredportable biomedical applications. By incorporating the

Power consumption (IlW)Full-adder 1.8 V 1.5 V 1.2 V

TVD. SS FF TVD. SS FF TVD. SS FFSumeer Goel's FA 8.58 7.54 11.2 5.25 4.71 6.29 3.07 3.19 3.20

Hvbrid FA 10.3 8.59 11.3 6.09 5.06 7.18 3.20 3.07 3.68CLRCLFA 16.6 1.39 2.08 9.30 7.74 1.23 N.A. N.A. N.A.

ULPFA 7.61 7.05 8.79 4.66 4.45 5.27 N.A. N.A. N.A.N-I2T FA 4.92 4.10 5.97 2.98 2.80 3.27 N.A. N.A. N.A.

Proposed FA 6.61 5.83 7.68 4.06 4.04 4.31 2.45 2.64 2.53

WFz

1---------------+ WFl

Figure 7: Wavelet filter bank [7].

(a) Low pass filter

(b) High pass filter

Figure 8: Filter inside wavelet filter bank circuits [7].

The proposed full-adder is implemented into the FIR filterand the design dissipated an average power consumption of25.2 J.lW at a frequency of 50 MHz. As shown in Table II,this design shows an improvement of 36.7% in powerconsumption when compared to the multiplier-less FIR filterusing Sumeer Goel's full-adder.

CONCLUSION

In this paper, we proposed a 17-transistor full-adder that isable to operate at 1.2 V power supply. The performance ofthe full-adders is compared and the simulation results provedthat proposed full-adder dissipate the lowest powerconsumption and lowest PDP.

118

proposed full-adder, the multiplier-less FIR filter can achievean improvement of 36.7% in power consumption whencompared to the Sumeer Goel's full-adder.

Table Il, Power consumption comparisons of multiplier-less FIR filter .

Multiplier-less FIR filter using Power consumption (J.lW)(iiJ50 MHz

Sumeer Goel's FA 39.8Proposed FA 25.2

ACKNOWLEDGMENT

This work is partially supported by the Agency forScience Technology and Research Institute ofMicroelectronics (A*STAR IME) and NanyangTechnological University (NTU).

REFERENCES

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