.

ULTRATHIN DIELECTRICS ON SiGe/SiGeCLAYERS FOR HETEROSTRUCTURE

MOSFET APPLICATIONS

A thesis submitted to the

Indian Institute of Technology, Kharagpur

for the award of the degree

of

Doctor of Philosophy

by

SIDDHESWAR MAIKAP

Department of Physics and Meteorology

Indian Institute of Technology

Kharagpur-721302, India

August 2001

.

Dedicated to my Father

.

August 21, 2001

Certi¯cate

This is to certify that the thesis entitled \Ultrathin Dielectrics on SiGe/SiGeC

Layers for Heterostructure MOSFET Applications" submitted by Mr. Siddheswar

Maikap for the award of the degree of Doctor of Philosophy (Ph.D) of this Institute,

is a record of bona¯de research work carried out by him in the Department of Physics

& Meteorology and Department of Electronics & ECE under our supervision. He

has worked as a research scholar in the Institute for about four years and in our

opinion this thesis is of the standard required for the award of the Ph.D degree of

this Institute. The results embodied in this thesis have not been submitted for the

award of any other degree or diploma.

(Chinmay K Maiti) (S K Ray)

. Professor Associate Professor

. Dept. of E & ECE Dept. of Physics & Meteorology

Acknowledgements

This is, indeed, a great pleasure for me to express my deep sense of appreciation

and gratitude to my supervisors Dr. S. K. Ray, Dept. of Physics and Meteorology, IIT

Kharagpur and Prof. C. K. Maiti, Dept. of Electronics & Electrical Communication

Engineering, IIT Kharagpur for their valuable guidance and advice. As my research

supervisors, their patience, dedication, inspiration and enthusiasm have helped me a

lot at all the stages of my research work.

I am grateful to Prof. S. K. Banerjee of the University of Texas at Austin and

Prof. Y. Shiraki of the University of Tokyo for providing the experimental facilities

for the preparation of Si Ge and Si Ge C heterolayers.1¡x x 1¡x¡y x y

I wish to express my sincere thanks to Prof. N. B. Chakrabarti for his kind interest

througout the progress of this work and Prof. S. K. Lahiri, Dept. of E & ECE for

extending the Microelectronics facilities. I would like to acknowledge Prof. B. K.

Mathur, Dept. of Physics and Meteorology for his kind co-operation in my thesis

progress.

I gratefully acknowledge the help obtained at various stages of the experimental

work from all the members of the Microelectronics family and Microscience Labo-

ratory, Dept. of Physics and Meteorology. I am also grateful to the Head, Dept.

of Physics and Meteorology for providing me all types of other facilities. I wish to

express thanks to all of my friends their help towards the completion of the work.

Financial support from the DRDO, New Delhi for the entire period of my research,

is gratefully acknowledged.

IIT Kharagpur

. August 2001 (Siddheswar Maikap)

BIODATA

S. Maikap, son of Late Sarbeswar Maikap and Mrs. Jayanti Maikap, received

his Master's degree in Physics with specialization in Solid State Physics in 1995

from Vidyasagar University, Midnapore. In 1996, he joined as a Project Assistant

in Cryogenic Engineering Center at IIT Kharagpur. In 1997, he joined as a Project

Sta® in a DRDO sponsored project in the area of silicon-germanium heterostructures

in the Dept. of E & ECE. He became as a Research Fellow of the Dept. of Physics

and Meteorology in 1998. His current research interests include microwave plasma

processing for VLSI/ULSI applications, ultrathin stacked dielectric ¯lms on group-IV

layers, and applications of Si-based alloy layers for heterostructure MOSFETs in Si

technology.

List of Publications and Presentations

Journal Publications

² S. Maikap, L. K. Bera, S. K. Ray and C. K. Maiti, \NO/O /NO plasma-grown2

oxynitride ¯lms on strained-Si Ge ",Electron. Lett., vol.35, pp. 1202-1203, 1999.1¡x x

² S. Maikap, L. K. Bera, S. K. Ray, S. John, S. K. Banerjee and C. K. Maiti, \

Electrical characterization of Si/Si Ge /Si quantum well heterostructures using a1¡x x

MOS capacitor",Solid-State Electron., vol. 44, pp. 1029-1034, 2000.

² S. Maikap, S. K. Ray, S. John, S. K. Banerjee and C. K. Maiti, \Electrical

characterization of ultra-thin gate oxides on Si/Si Ge C /Si quantum well het-1¡x¡y x y

erostructures",Semicond. Sci. Technol., vol. 15, pp. 761-765, 2000.

² S. Maikap, S. K. Ray, S. K. Banerjee and C. K. Maiti, \Electrical properties of

O /NO-plasma grown oxynitride ¯lms on partially strain compensated Si/Si Ge C -2 1¡x¡y x y

/Si heterolayers", Semicond. Sci. Technol., vol. 16, pp. 160-163, 2001

² S. Maikap, B. Senapati and C. K. Maiti, \Technology CAD of SiGe-HFETs",

Def. Sci. J., vol. 51, pp. 195-197, 2001.

v

² S. K. Ray, S. Maikap, S. K. Samanta, S. K. Banerjee and C. K. Maiti, \ Charge

trapping characteristics of ultrathin oxynitrides on Si/Si Ge C /Si heterolayers",1¡x¡y x y

Solid-State Electron., in press.

² C. K. Maiti, L. K. Bera, S. Maikap, S. K. Ray, R. Kesavan, V. Kumar and N.

B. Chakrabarti, \ Growth of silicon-germanium alloy layers", Def. Sci. J., vol. 50,

pp. 299-315, 2000.

² L. K. Bera, B. Senapati, S. Maikap and C. K. Maiti, \E®ets of O /N O-2 2

plasma treatment on nitride ¯lms on strained-Si", Solid-State Electron., vol. 44, pp.

1533-1536, 2000

² B. Senapati, S. Samanta, S. Maikap, L. K. Bera and C. K. Maiti, \E®ects of

NO-plasma treatment on the electrical properties of TEOS-deposited silicon dioxides

on strained-Si Ge layers", Appl. Phys. Lett., vol. 77, pp. 1840-1842, 20001¡x x

² L. K. Bera, B. Senapati, S. Maikap, and C. K. Maiti, \Determination of trap

density in the dielectric ¯lms on strained-Si", Solid-State Electron., vol. 45, pp. 379-

383, 2001.

² S. K. Samanta, S. Maikap, L. K. Bera, H. D. Banerjee and C. K. Maiti,

\E®ect of post-oxidation annealing on the electrical properties of deposited oxide and

oxynitride ¯lms on strained-Si Ge layers", Semicond. Sci. Technol., in press.0:82 0:18

Conference Presentations

² S. Maikap, S. K. Ray and C. K. Maiti, \NO/O /NO plasma grown oxynitride2

¯lms on silicon", in the proc. of 10th Int'l Workshop on Physics of Semiconductor

Devices, New Delhi, pp. 411-414, 1999.

² B. Senapati, S. Maikap, L. K. Bera and C. K. Maiti, \ Deposition of sto-

ichiometric SiO on silicon-germanium strained layers", in the proc. of 10th Int'l2

Workshop on Physics of Semiconductor Devices, New Delhi, pp. 448-451, 1999.

²G. S. Kar, S. Maikap, A. Dhar and S. K. Ray, \ Schottky diode on Si/Si Ge -1¡x¡y x

C /Si quantum well heterostructures for long wavelength IR detector, in the proc. ofy

"Photonics-2000", Calcutta, pp. 107-110, 2000.

vi

Abstract

Very exciting and promising results from the group-IV alloy layers have led to

the belief that silicon-germanium (SiGe) based devices will open up an entirely new

dimension in VLSI/ULSI Si technology. Strained Si Ge and strain compensated1¡x x

Si Ge C o®er many desirable electronic and optical properties due to favorable1¡x¡y x y

band alignment and strain-induced modi¯cation of band structure, e®ective mass and

optical transitions. Growth of gate quality ultrathin oxide/stacked oxynitride ¯lms

is a key technology issue in device scaling e®orts since they form the `heart' of n-

and p-channel MOSFETs in CMOS technology and largely determine the transis-

tor's performance. Low-temperature growth of ultrathin dielectrics on SiGe/SiGeC

layers are attractive for device applications since strained SiGe and partially strainocompensated SiGeC layers (typically grown at »550 C) are metastable in nature.

The present research study is concerned with the investigation on Si Ge and1¡x x

Si Ge C heterolayers for high performance p-MOSFET applications. The fol-1¡x¡y x y

lowing studies have been carried out in detail:

² Heterostructures Si Ge and Si Ge C layers have been grown using GSMBE1¡x x 1¡x¡y x y

and UHVCVD. Microstructural characterization of the ¯lms have been performed us-

ing RBS, SIMS, HRXRD and AFM techniques.

² Hole con¯nement in SiGe/SiGeC well has been used to determine the valence bando®set and threshold voltages at surface and buried channels of a MOS capacitor. Mi-

nority carrier generation lifetime of binary and ternary alloy layers has been measured

from transient response of a MOS capacitor.

º² Growth of ultrathin oxide (<100 A) on SiGe/SiGeC layers has been performed us-ing microwave plasma at a low temperature.

² Stacked oxynitride ¯lms (viz., NH /NO, O /NO/O , NO/O /NO and O /NH /NO)3 2 2 2 2 3

grown using plasma process exhibit improved electrical, interfacial, charge trapping

and reliability properties.

² Design and simulation of heterostructure SiGe-channel p-MOSFETs on modulation-doped layer and SIMOX substrates have been carried out using 1-D Poisson solver,

analytical model and Silvaco-ATLAS device simulation tool.

vii

Contents

1 Introduction 1

1.1 Motivation : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 1

1.2 Critical Thickness of Strained Layers : : : : : : : : : : : : : : : : : : 4

1.3 Strain Compensation : : : : : : : : : : : : : : : : : : : : : : : : : : : 6

1.4 Band Alignment : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8

1.5 Oxide and Oxynitride Films on Strained

Layers : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 9

1.6 Design and Material Parameters of

p-MOSFETs : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 12

1.7 Organization of the Thesis : : : : : : : : : : : : : : : : : : : : : : : : 15

2 Growth and Characterization of Group-IV Alloy Layers 17

2.1 Strained Layer Epitaxy : : : : : : : : : : : : : : : : : : : : : : : : : : 18

2.2 Growth of Si Ge and Si Ge C Films : : : : : : : : : : : : : : 211¡x x 1¡x¡y x y

2.3 Structural Characterization : : : : : : : : : : : : : : : : : : : : : : : 24

2.3.1 Rutherford Backscattering : : : : : : : : : : : : : : : : : : : : 25

2.3.2 Secondary Ion Mass Spectroscopy : : : : : : : : : : : : : : : 25

2.3.3 High Resolution X-ray Di®raction : : : : : : : : : : : : : : : 26

2.3.4 Atomic Force Microscopy : : : : : : : : : : : : : : : : : : : : : 28

2.4 Electrical Characterization : : : : : : : : : : : : : : : : : : : : : : : 31

2.4.1 MOS Capacitor Fabrication : : : : : : : : : : : : : : : : : : : 31

2.4.2 Capacitance-Voltage Characteristics : : : : : : : : : : : : : : : 31

2.4.3 Extraction of Si-cap Layer Thickness : : : : : : : : : : : : : : 33

2.4.4 Extraction of Threshold Voltages of Strained Layers : : : : : : 34

2.4.5 Extraction of Valence Band O®set (¢E ) : : : : : : : : : : : : 36v

2.4.6 Generation Lifetime (¿ ) of Alloy Layer : : : : : : : : : : : : : 40g

viii

2.5 Summary : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 43

3 Ultrathin Gate Oxides on SiGe/SiGeC Layers 44

3.1 Oxidation of SiGe/SiGeC Films : : : : : : : : : : : : : : : : : : : : : 45

3.1.1 Thermal Oxidation : : : : : : : : : : : : : : : : : : : : : : : : 45

3.1.2 Low-Temperature Oxidation : : : : : : : : : : : : : : : : : : : 47

3.2 Experimental Setup : : : : : : : : : : : : : : : : : : : : : : : : : : : : 49

3.3 Sample Preparation : : : : : : : : : : : : : : : : : : : : : : : : : : : 50

3.4 Oxide Films on Partially Strained SiGeC

Layers : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 52

3.4.1 High Resolution X-ray Di®raction : : : : : : : : : : : : : : : 53

3.4.2 Fourier Transform Infrared Spectroscopy : : : : : : : : : : : : 54

3.5 Electrical and Interfacial Characteristics : : : : : : : : : : : : : : : : 55

3.5.1 The MOS Capacitor : : : : : : : : : : : : : : : : : : : : : : : 55

3.5.2 Determination of Trap Charges : : : : : : : : : : : : : : : : : 57

3.5.3 Oxide Charge and Interface State Density : : : : : : : : : : : 59

3.5.4 I-V Characteristics : : : : : : : : : : : : : : : : : : : : : : : : 62

3.5.5 Charge Trapping Behavior : : : : : : : : : : : : : : : : : : : : 63

3.5.6 Breakdown Characteristics : : : : : : : : : : : : : : : : : : : : 65

3.6 Summary : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 66

4 Oxynitride Films on SiGe/SiGeC Layers 67

4.1 Oxynitride Films on Strained SiGe Layers : : : : : : : : : : : : : : : 70

4.1.1 X-ray Photoelectron Spectroscopy : : : : : : : : : : : : : : : 71

4.1.2 Interface Properties : : : : : : : : : : : : : : : : : : : : : : : : 72

4.1.3 Charge Trapping Characteristics : : : : : : : : : : : : : : : : : 74

4.1.4 Border Trap Density : : : : : : : : : : : : : : : : : : : : : : : 75

4.1.5 Breakdown Characteristics : : : : : : : : : : : : : : : : : : : : 77

4.2 Oxynitride Films on Partially Strained SiGeC Layers : : : : : : : : : 79

4.2.1 Fourier Transform Infrared Spectroscopy : : : : : : : : : : : : 80

4.2.2 Fixed Charge Density : : : : : : : : : : : : : : : : : : : : : : 81

4.2.3 I-V Characteristics : : : : : : : : : : : : : : : : : : : : : : : : 82

4.2.4 Trapping Behavior Under Static Stress : : : : : : : : : : : : : 84

4.2.5 Trapped Charge and Charge Centroid under Dynamic Stress : 87

4.2.6 Charge-to-Breakdown Characteristics : : : : : : : : : : : : : : 91

ix

4.3 Summary : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 92

5 Design and Simulation of SiGe p-MOSFETs 94

5.1 Review on Previous Work : : : : : : : : : : : : : : : : : : : : : : : : 98

5.1.1 Simulation of SiGe-channel p-MOSFETs : : : : : : : : : : : : 98

5.1.2 p-MOSFETs on SIMOX : : : : : : : : : : : : : : : : : : : : : 99

5.2 Simulation of SiGe p-MOSFETs : : : : : : : : : : : : : : : : : : : : : 101

5.2.1 Hole Density in the SiGe-well : : : : : : : : : : : : : : : : : : 103

5.2.2 Hole Density in Si-cap : : : : : : : : : : : : : : : : : : : : : : 104

5.3 Design of SiGe p-MOSFETs : : : : : : : : : : : : : : : : : : : : : : : 106

5.3.1 Choice of Gate Material : : : : : : : : : : : : : : : : : : : : : 106

5.3.2 E®ect of Ge Concentration : : : : : : : : : : : : : : : : : : : : 108

5.3.3 E®ect of SiGe-well and Si-cap Layer Thickness : : : : : : : : : 111

5.3.4 SiGe-channel p-MOSFETs with ±-doping Spike : : : : : : : : 115

5.4 SiGe-channel p-MOSFETs on SIMOX : : : : : : : : : : : : : : : : : : 120

5.5 Summary : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 126

6 Conclusion 128

6.1 Contributions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 128

6.2 Suggestions for Future Work : : : : : : : : : : : : : : : : : : : : : : : 129

x

Chapter 1

Introduction

1.1 Motivation

Silicon technology dominates the present semiconductor market with more than 98%

of all sales compared to III-V semiconductor products which demonstrates its superi-

ority. There are many reasons, one may argue for this position of Si but the dominant

factor is low cost. The fabrication process and device performance rely heavily on

a number of properties of Si but, more importantly, the insulators of Si. SiO and2

Si N have allowed Si to dominate over other materials such as GaAs and InP which3 4

as yet have not reached the phenomenal yields achievable on a Si chip.

The aggressive scaling down of semiconductor devices following Moore's law is

presented in ¯gure 1.1. The gate length for both central processing units (CPUs) and

dynamic random access memories (DRAMs) is being scaled down accordingly. Pre-

diction of technology direction by the Semiconductor Industry Association Roadmap

[1] is shown in Table 1.1. The exponential decrease in gate length is expected to

continue until about 2010 and CMOS is therefore expected to be dominant until at

least 2010.

Scaling down of device dimensions is desirable to obtain higher levels of integration

on a chip, which leads to a higher on-chip functionality in logic applications and

a higher storage capacity in memory applications. Scaling approach demands the

reduction in channel length accompanied by a proportional reduction in gate oxide

thickness. This requirement is essential primarily to minimize the short channel

e®ects. By scaling the oxide thickness, the MOSFET can be made to behave like a

long channel one [2]. In addition, scaling down the oxide thickness contributes to an

1

increase in current drive capability, necessary for faster switching applications. The

reduction in oxide thickness is currently being slowed down because of the di±culty

of producing satisfactory ¯lms of ultrathin SiO . Process and electrical stress induced2

defects pose an ultimate limit.

Figure 1.1: Moore's law: the gate length and cost of production lines as a function

of time. Source: National Technology Roadmap for Semiconductors, Semiconductor

Industry Association, San Jose, USA, 1997. (After D. J. Paul, Adv. Mater., vol. 11,

1997 p. 191).

A major issue for the device designers is to achieve symmetrical electrical operation

from equivalently sized n- and p-MOSFETs for increased packing density in CMOS

circuits. However, the p-channel (p-MOS) devices are inferior to the n-channel (n-

MOS) ones in terms of current drive capability and speed performance. This is a

consequence of lower mobility of holes compared to that of electrons in Si. Thus, size

of the p-MOS device is made 2-3 times larger compared with n-MOS device, thereby

a®ecting the integration density and speed. A higher mobility in the channel of a p-

MOSFET will improve both circuit speed and the level of integration in CMOS. One

possibility is to fabricate Si heterostructure devices using group-IV semiconductor

materials on Si substrates.

2

Table 1.1: Selected data from the Semiconductor Industry Association Roadmap

Year 1998 2001 2004 2007 2010

Memories, DRAM

Bits per chip 256 M 1 G 4 G 16 G 64 G

Cost per chip (US$) 18 30 40 80 1302Die size (mm ) 280 420 640 960 1400

Logic, Microprocessors3Transistors (/cm ) 7 M 13 M 25 M 50 M 90 M

Cost per transistor (millicent) 0.5 0.2 0.1 0.05 0.02

Power supply (V) 2.5 1.8 1.5 1.2 0.9

Parameters

Channel length (¹m) 0.2 0.14 0.1 < 0.1 <0.07

Wafer size (inch) 8 12 12 16 182Defect density (/m ) 160 140 120 100 25

Oxide thickness (nm) 4-6 4-5 4-5 <4 <4

Clock high performance (MHz) 450 600 800 1000 1100

Germanium (Ge) and carbon (C) are widely used heterojunction partners with

Si. The lattice mismatch between Ge and Si, and Si and C is approximately 4.2%

and 52%, respectively. There is a signi¯cant band gap di®erence between Si (1.12

eV), Ge (0.67 eV) and C (5.5 eV) which allows the possibility of bandgap engineering

in group-IV alloys. SiGe is a Si-based alloy, which has been widely studied in the

last decade. Strained Si/Si Ge /Si heterojunctions and quantum wells have been1¡x x

employed in manufacturing many microelectronic and optoelectronic devices, such as

heterojunction bipolar transistors, MOSFETs infrared photodetectors, and optical

waveguide devices. In all these applications, the heterointerface between Si and SiGe

plays a crucial role. The addition of C has demonstrated further modi¯cation of the

electronic and optical properties of Si/SiGe alloys. Carbon varies the degree of strain

in the Si/SiGe system, an important parameter in the optoelectronic properties and

thermal stability of the alloy.

3

1.2 Critical Thickness of Strained Layers

E. Kasper and his co-workers at AEG (now Daimler-Chrysler) ¯rst demonstrated

the growth of high quality lattice-matched or pseudomorphic Si Ge ¯lms by molec-1¡x x

ular beam epitaxy (MBE) on Si substrates [3]. Due to the lattice mismatch between

Si and Ge, there is some di±culty in growing a Ge ¯lm directly upon Si. The lattice

Figure 1.2: Schematic diagram of strained and relaxed epilayer on a Si substrate. In

the relaxed layer, many dislocations are seen at the epi/substrate interface (After D.

J. Paul, Adv. Mater., vol. 11, 1997 p. 191).

constant of Si Ge alloys changes monotonically, obeying Vegard's law as1¡x x

a (x) = a + x(a ¡ a ) (1.1)SiGe Si Ge Si

for low Ge fraction. When the SiGe alloy layer is grown on a thick Si substrate, the

mismatch is accommodated in either of the two ways:

i) tetragonal distortion of the cubic lattice which is given by standard elastic-

ity theory [4] for biaxial stress, in which the linear strain (") between epilayer and

4

substrate is de¯ned by

"¼(a ¡ a )=a (1.2)e s s

where a and a are the free in-plane lattice parameters of epilayer and substrate unite s

cells, respectively. Figure 1.2(a) depicts the lattice mismatch between bulk Si and

Si Ge crystals. Provided, only a thin layer of Si Ge is grown pseudomorphically1¡x x 1¡x x

(lattice matched) on bulk Si, the layer is strained and the symmetry changes from

cubic to tetragonal as shown in ¯gure 1.2(b).

Figure 1.3: Critical layer thickness of Si Ge layers as a function of Ge mole fraction.1¡x x

Lines show theoretical kinetic model for various growth temperature. Figure is after

D. C. Houghton, J. Appl. Phys., vol. 70, 1991, p. 2136.

ii) generation of mis¯t dislocations at the interface gives rise to relaxed or un-

strained growth (¯gure 1.2(c)). Mis¯t dislocations are undesirable since the formation

of e±cient generation-recombination center degrades device performance and intro-

duces noise. For thin layers of Si Ge grown on bulk Si, there exists a maximum1¡x x

thickness called the critical thickness above which the strain relaxes through the prop-

agation of mis¯t dislocations. Pseudomorphic or commensurate ¯lm is grown below

the critical layer thickness. Strained-layer structures o®er the advantage of signi¯-

5

cant modi¯cation in bandstructures providing an additional °exibility in the design

of electronic and optical devices.

The thickness of the group-IV epilayer is one of the most important device design

parameters. Extensive studies have been performed to determine the critical thickness

in the strained material. The concept of critical thickness was ¯rst introduced by

Frank and Van der Merwe [5, 6] who de¯ned critical thickness (h ) as \the ¯lmc

thickness below which it was energetically favorable to contain the mis¯t by elastic

energy stored in the distorted crystal and above which it was favorable to store

part of the energy in mis¯t dislocations at the heterointerface". Van der Merwe

[6] calculated the critical thickness as a function of increased lattice mismatch by

minimizing the sum of the interfacial and strain energy. However, most of the recently

published literature has embraced the mechanical equilibrium theory of Matthews

and Blakeslee [7, 8] as de¯ning the transition from the stable to metastable regimes.

Figure 1.3 shows three regimes in the plot of Si Ge layer thickness on Si vs. Ge1¡x x

concentration (x) under di®erent growth conditions. The Ge concentration is directly

related to the lattice mismatch according to Vegard's law. Bean et al. [9] depositedostrained layers by molecular beam epitaxy (MBE) at 550 C with a thickness an order

of magnitude or more above the Matthews-Blakeslee curve as shown by the solid data

points in ¯gure 1.3. The critical thickness (h ) depends on growth temperature andc

growth rate; h increases with decreasing substrate temperature [10, 11]. Between thec

solid mechanical equilibrium line and the dotted MBE data points, layers are labeled

metastable. Layers in the metastable regime are strained even though the layers are

above the Matthews-Blakeslee critical thickness. However, metastable layers relax on

subsequent annealing. The layers above the dotted line are relaxed containing mis¯t

dislocations. People and Bean [12] proposed a nonequilibrium model for critical

thickness based on energy balance theory, which represents a metastable condition

for the epilayer. However, experimental observation is limited by the measurement

techniques used.

1.3 Strain Compensation

The fundamental limitation of SiGe alloy ¯lms on Si substrate is the lattice mis-

match between the ¯lm and substrate, especially for Si Ge with high Ge content.1¡x x

The constrain in critical layer thickness of strained Si Ge layers has imposed se-1¡x x

6

vere limitations on device structures, restricting their application only for low Ge

concentration, thin active layer and relatively low process temperature windows. An

Figure 1.4: Critical layer thickness of Si Ge C as a function of Ge and C con-1¡x¡y x y

centration. Figure is after Amour et al., Thin Solid Film., vol. 294, 1997, p. 112.

interesting approach that has been used is the addition of small amount of C in SiGe

¯lms to perform strain engineering [13]. Since C is a much smaller atom than Si,

while Ge is larger, C provides dilational strain which compensates the compressive

strain provided by Ge and hence increases the critical thickness as shown in ¯gure

1.4. Estimates of how much C is needed for complete strain compensation in SiGe

¯lms range from Ge-to-C ratios of 8:1 to 13:1, with a gradual consensus building up

at a Ge-to-C ratio of 8.5:1 [14]. Therefore, incorporating relatively small sized car-

bon atoms substitutionally into SiGe system enables one to compensate the strain,

allowing more °exibility in strain and bandgap engineering.

7

1.4 Band Alignment

Strain induced modi¯cation of band structure of heterolayers is found to have

a signi¯cant impact on the optical transitions and carrier transport. An accurate

knowledge of band alignment in a heterojunction is essential for device design and

performance analysis. The fundamental band gap of SiGe is lower compared to pure

Si. Strain in pseudomorphic layer modi¯es the band structure which includes the split-

ting of degenerate valence and conduction bands [15], resulting in a stronger bandgap

reduction in the strained SiGe alloy. The strain-split heavy hole band determines the

smallest gap [16, 17].

Figure 1.5: Band alignments between Si and Si Ge on two substrates: (a) Si0:70 0:30

and (b) relaxed Si Ge .0:70 0:30

Several authors reported the e®ect of compressive and tensile strain on the valence

band line-up [18, 19]. In both cases, the degeneracy between the heavy hole (HH) and

light hole (LH) bands is lifted, and the valence band maximum is higher in energy

as compared to the unstrained case. Strain also reduces the in-plane e®ective mass

of the hole. The lifting of degeneracy, smaller e®ective mass of conduction holes, and

reduced scattering rates increase the hole mobility for strained SiGe over unstrained

bulk-Si. Calculated results by Hinckley and Singh [18] and Manku and Nathan [19]

for strained SiGe show an increase in the drift mobility of hole relative to that of Si.

Figure 1.5(a) shows the band o®set between a strained Si Ge ¯lm grown on0:7 0:3

Si. This is known as the type-I band alignment where the entire band o®set occurs

in valence band while the band o®set in conduction band is very small. This type

8

of structure is favorable for hole con¯nement and has been exploited in several het-

erostructure devices viz., buried channel p-MOSFETs, p-MODFETs and HBTs (see

for example, a recent review by Maiti et al. [20] ). On the contrary, ¯gure 1.5(b)

shows the band o®set for a strained-Si epilayer grown on relaxed Si Ge . In this0:70 0:30

case, type-II band o®set occurs and the structure has several advantages over the

more common type-I band alignment, as a large band o®set is obtained in both the

conduction and valence bands, relative to the relaxed Si Ge layer [12].1¡x x

Theoretical calculations based on the electronic structure of heterointerfaces, in-

volving a variety of SiGe layers on Si substrates, have been employed to predict band

o®set [21]. However, empirical rules, derived from experimental results, give better

estimates. Several authors reported the valence band o®set for strained Si Ge het-1¡x x

erolayers using di®erent methods [22, 23, 24, 25, 26]. The results for the Si Ge /Si1¡x x

system agrees well with the theoretical prediction of ¢E =740x meV, where x is thev

Ge fraction.

Unlike Ge, because of the large di®erence in lattice constant, C presents a strong

perturbation to the Si lattice and drastically a®ects the validity of the virtual crystal

approximation [27]. Initial work by Soref [28], using interpolation techniques, seemed

to predict an increase in the bandgap with increasing C for Si Ge C alloy. Pho-1¡x¡y x y

toluminescence (PL) work has indicated an increase in the bandgap upon the addition

of C (¢E /¢y = +21 eV/% C). The blue shift in the PL spectra is smaller than theg

strain relief as observed through X-ray di®raction [29]. More recent PL work has

con¯rmed these results and also shown that fully strain compensated Si Ge C1¡x¡y x y

layers on Si (001) should have a lower bandgap than that of Si [30]. The valence

band o®set in SiGe on Si is reported to decrease by 25 meV to 30 meV for 1% C.

[31]. Several authors reported the valence band o®set of Si/SiGe and Si/SiGeC het-

erostructures but their results are di®erent. Therefore, there exists considerable scope

on experimental determination of valence band o®set in SiGe and SiGeC systems.

1.5 Oxide and Oxynitride Films on Strained

Layers

The quality of gate oxide is extremely important since it forms the `heart' of n-

and p-channel MOSFETs in CMOS technology and largely determines the transistor's

ºperformance. Gate oxides are getting thinner as device dimensions shrink (<100 A).

9

Use of thinner gate oxides are preferred to maximize the transistor drain current and

to reduce the power supply voltage, the lower limit being mainly governed by tun-

neling and reliability issues. The requirements of ultrathin oxide ¯lms that are being

used for gate, tunnel and storage applications are to have high dielectric strength,

low defect and interface state density, high immunity to hot carrier degradation, good

radiation hardness, high di®usion resistance and minimum charge trapping.

The growth of a high quality oxide on SiGe and SiGeC is key processing step

for device applications. However, the conventional thermal oxidation at a high tem-

perature causes serious problems in case of group-IV alloys due to Ge segregation,

C precipitation and strain relaxation of pseudomorphic layers. Several results have

been reported on thermal oxidation of Si Ge /Si and Si Ge C /Si heterolayers1¡x x 1¡x¡y x y

accompanied by strain relaxation [32, 33, 34, 35, 36, 37]. These deal mostly with the

wet oxidation of SiGe and SiGeC performed in conventional furnaces and for thicker

oxide layers. The results of rapid thermal oxidation of SiGe in the very thin oxide

regime have been presented by Nayak et al. [38]. It has been shown that rapid ther-

mal oxidation (RTO) is preferred because it provides a good control for growth of

thin oxides, and it produces a good quality oxide when compared to furnace oxidation

[39]. RTO also minimizes strain relaxation and interdi®usion in the SiGe or SiGeC

epilayers. [37]. But it was found that Ge segregation could not be prevented at the

oxide/Si interface. Thus, low temperature oxidation of SiGe and SiGeC heterolayers

is essential to grow a high quality oxide layer without Ge segregation and carbon

precipitation while maintaining the pseudomorphic nature of the alloy. Several alter-

native methods have been investigated to grow gate oxide on alloy layers at a low

temperature using plasma [40, 41], UV and ion beam [42, 43].

Oxynitride ¯lms are potential alternatives to SiO as gate dielectrics in VLSI/ULSI2

technology. Several studies [44, 45, 46, 47, 48, 49] have demonstrated that an appre-

ciable amount of N in the oxide near the boron-doped polysilicon gate/oxide interface

increases the di®usion barrier to boron penetration towards the active region of the

semiconductor device, whereas comparable (ideally, somehow smaller) concentration

of N at and near the oxide/Si interface helps to improve resistance to hot electron

degradation [50]. Therefore, nitrogen incorporated oxide (hereafter termed as oxyni-

tride) ¯lms containing adequate amount of N near the two interfaces are attractive,

preserving the advantages of the oxide/Si interface, with the additional bene¯ts due

to the presence of N.

Di®erent process sequences containing various N sources may be used to obtain

10

desired nitrogen pro¯le in oxynitride ¯lms: (i) N peak located at the SiO /Si interface2

generated by growing oxide in pure O ambient followed by a short NO anneal, (ii)2

N peak at the poly/SiO interface, generated by N implantation, followed by N2 2

anneal to drive-in the N at the desired interface, and (iii) N peaks at both interfaces,

generated by a combination of the two methods mentioned above [51]. The boron

trapping behavior of the above three cases is schematically shown in ¯gure 1.6. It

has been proposed that double wall `N' barrier (cf. ¯gure 1.6(d)) may lead to the

Figure 1.6: The impact on B penetration into gate oxides: (a) without any interface

layers, (b) with N at the SiO /Si interface, (c) with N at the poly/SiO interface2 2 2 2

and (d) N at both interfaces (After G. D. Leonarduzzi and D. L. Kwong, Semicond.2

Int'l., July 1998, p. 225).

signi¯cant improvement of gate dielectric properties over single wall `N' and pure oxide

¯lms [52]. Therefore, it is of scienti¯c and technological interest to investigate the

characteristics of stacked oxynitride ¯lms grown with di®erent process sequences using

a combination of NH , NO, O and H on Si Ge and Si Ge C heterolayers.3 2 2 1¡x x 1¡x¡y x y

11

1.6 Design and Material Parameters of

p-MOSFETs

Transport properties of holes in Si Ge and Si Ge C heterolayers have1¡x x 1¡x¡y x y

been reported by several authors [53, 54, 55, 56]. Carns et al. [53] reported Hall

mobility in compressively strained p-type Si Ge layers. The Hall mobility was1¡x x

found to decrease with increasing Ge content at all doping levels. Duschl et al. [55]

studied the hole mobility for ternary alloys only up to a Ge concentration of 6%

without observing any improvement on C addition. The Hall mobility was found to2decrease with C and Ge alloy concentration compared to pure Si from 180 cm /V.s

2to 120 cm /V.s, which was explained by the increasing alloy scattering and enhanced

scattering due to optical phonons. Osten and Gaworzewski [54] reported the Hall

mobilities of holes in compressively strained Si Ge C (200 nm thick) layers with1¡x¡y x y

higher Ge and C fractions. Their reported results indicate that electrically active de-

fects are formed with the addition of carbon. These defects are presumably connected

with carbon/Si interstitials or other C-related complexes. Kar et al. [56] reported

that the Hall mobility of holes for ternary alloy is enhanced as compared to binary

SiGe due to the modi¯cation of Hall scattering factor. Joelsson et al. [57] reported

that depending on the doping concentration, the ¯eld-e®ect mobility can be higher

for strained layers containing Ge. Ray et al. [58] reported the enhancement of the2linear region ¯eld-e®ect mobility for Si Ge C (209 cm /V.s) in comparison to0:793 0:2 0:007

2140 cm /V.s for a Si Ge p-MOSFET device.0:8 0:2

Si/SiGe heterojunction p-MOSFETs have attracted much attention because of

their potentially high hole mobility and ease of integration into conventional Si pro-

cessing technology. Table 1.2 presents a summary of p-MOSFET device results fab-

ricated using strained SiGe alloys. The improved carrier mobility is attributed to

the isolation of the conduction channel from surface and ionized impurities so that

surface and impurity scattering are signi¯cantly reduced. When holes are con¯ned in

the SiGe-channel, the hole mobility is expected to be higher than that in comparable

Si p-MOSFET's [59, 60]. To reduce the hole population in the surface channel (Si-

cap) and scattering due to ionized impurities, several researchers [61, 62] proposed a

±-doping spike below the SiGe layer separated by a thin Si spacer layer. The ±-doping

spike plays two important functions:

a) it suppresses source/drain leakage current (threshold voltage adjustment) and

12

b) it improves device transconductance by con¯ning the hole at the SiGe-well.

Table 1.2: Reported characteristics of SiGe-channel p-MOSFETs. Value of a param-

eter not quoted in the original paper is indicated by a dash. Ge concentration x=0

indicates Si control p-MOSFET.

L t t t Ge, x N g at 300 K ¹ Ref.eff ox well cap d m

¡3 ¡2º º º¹m (A) (A) (A) (cm ) (mS/mm) (cm /V.s)

- 35 - - 0.0 - 80 122 [63]171.0 100 1000 - 0.15 2£10 45 - [64]151.25 50 150 70 0.2 5£10 64.4 155 [59]1697 125 100 100 0.3 1£10 - 290 [60]15- 210 75 70 0-0.4 1£10 - 150 [65]

0.1 40 1000 - 0.14 - 190 - [66]170.6 38 10 50 0.25 1£10 15 - [67]170.8 80 400 50 0.2 1£10 5.7 209 [58]160.2 70 80 50 0.25-0.45 5£10 0.25 220 [68]

0.1 50 40 100 0.2-0.3 - 320 - [69]

1.0 - 150 200 0.4 - 68 - [70]

State of the art VLSI/ULSI technology requires deep submicron MOS transistors

to achieve higher packing density and high cut-o® frequency with minimum power

consumption. As the device dimensions penetrate into the deep micrometer regime,

conventional MOSFET scaling rules lead to excessively high channel doping require-

ments, causing undesirable large junction capacitance and degraded mobility [71].

The use of silicon-on-insulator (SOI) devices removes these di±culties, where un-

derlying oxide provides dielectric isolation and the implantation of source and drain

regions entirely through Si to the oxide substrate results in a vertical junction which

reduces junction area and improves the speed [72].

MOSFET devices on SOI substrates o®er superior characteristics over bulk MOS

devices such as reduced junction capacitance, suppressed short channel e®ect, low-

power consumption, better subthreshold swing, increased saturation current and

transconductance, and reduction in hot electron e®ect [73, 74]. Due to the pres-

ence of a thick buried oxide layer in a fully-depleted SOI device, the vertical electric

¯eld and the band bending at the Si surface are signi¯cantly reduced compared to

13

that of a bulk Si device [75]. Based on the property of reduced band bending of a SOI

structure, improved hole con¯nement in the buried SiGe quantum well on implanted

oxygen (SIMOX) substrate is possible and has been experimentally demonstrated by

Nayak et al. [73]. They showed the PL intensity of SiGe quantum well on SIMOX

substrate to be signi¯cantly higher than that of SiGe quantum well on bulk Si [76]

(in ¯gure 1.7).

ºFigure 1.7: (a) Schematic band diagram of a SiGe quantum well (34 A) grown on

SIMOX substrate. (b) Comparison of PL spectra of the Si/Si Ge /Si quantum0:82 0:18

wells grown on SIMOX and Si substrates at the same excitation power of 20 mW.

Electron-hole-droplets (EHDs) are readily formed in SIMOX substrate (After D. K.

Nayak et al., J. Appl. Phys., vol. 81, 1997, p. 3484).

14

Several authors have demonstrated the enhanced performance of Si Ge p-1¡x x

MOSFETs using ±-doped injecting layers and SOI substrates. For prediction of de-

vice performance and analysis, it is important to design and simulate SiGe-channel

p-MOSFETs. Systematic analytical and numerical simulations are needed to explore

the impact of design parameters such as threshold voltage adjustment, e®ect of oxide

thickness, Si-cap, SiGe-well thickness, Ge concentration and the role of modulation-

doping and SOI substrates on the heterostructure MOS device characteristics.

1.7 Organization of the Thesis

On the basis of foregoing discussions, it is felt, signi¯cant research is still necessary

to fully understand the behavior of C-containing SiGe alloys and the design issues of

buried channel SiGe MOSFET. This dissertation contains 6 chapters with a focus on

some of the above issues.

In Chapter 2, the growth methodology of strained SiGe and SiGeC layers using gas

source MBE and ultra-high-vacuum CVD is described. The results of characterization

of the epitaxial ¯lms using RBS, SIMS, high resolution X-ray di®raction, and atomic

force microscopy are presented. MOS capacitors on SiGe and SiGeC heterolayers

have been used as a test vehicle to determine the material parameters such as valence

band o®set, doping pro¯le and threshold voltages of surface and buried channels. The

generation lifetime of binary and ternary alloy layers has been extracted using Zerbst

technique.

Low-temperature oxidation of partially strain compensated Si Ge C ¯lms1¡x¡y x y

using thermal and microwave plasma process is presented in Chapter 3. The experi-

mental setup and oxide characterization techniques are described. The electrical and

interfacial properties of ultrathin gate oxides grown on SiGeC heterolayers using both

the thermal and plasma techniques are presented.

In Chapter 4, the growth of oxynitride ¯lms on SiGe and SiGeC layers using

di®erent combinations of O -, H -, NH - and NO-plasma are described. The trapping2 2 3

behavior under Fowler-Nordheim (F-N) constant current stressing, trapped charge

and charge centroid under static and dynamic stress, breakdown characteristics under

constant current (voltage) stressing for di®erent oxynitride ¯lms are presented and

compared.

A charge control model for heterostructure MOSFET that has been developed to

15

calculate the hole density at the Si-cap and SiGe-well with and without ±-doping spike

is discussed in Chapter 5. The analysis of ±-doped and SIMOX SiGe p-MOSFETs in

terms of hole population in surface and buried channels, threshold voltages and cross-

over voltage as a function of material parameters are presented. A 2-D device simu-

lator (Silvaco-ATLAS) has been used to simulate the SiGe-channel p-MOSFET with

and without ±-doping spike. The linear transconductance and output characteristics

extracted using Silvaco-ATLAS simulator for SIMOX, SiGe-bulk and SiGe-SIMOX

devices are also presented in this chapter.

Chapter 6 outlines the conclusion of the present study and recommendations for

future investigations.

16

Chapter 2

Growth and Characterization of

Group-IV Alloy Layers

Several growth techniques, such as molecular beam epitaxy (MBE), rapid thermal

chemical vapor deposition (RTCVD), and ultra-high-vacuum chemical vapor deposi-

tion (UHVCVD) have enabled ultrathin epitaxial semiconductor layers to be routinely

grown with monolayer precision in thickness and composition control to about 1 at.%.

Over the last two decades, increasing focus has been placed upon lattice mismatched

heteroepitaxy as biaxially strained layers o®er unique prospects, such as the use of

strain to modify electronic and optical properties. In this regard, alloys of group-IV

elements using Si, Ge and C have been actively pursued for use in heterojunction

devices compatible with conventional Si-processing technology. Signi¯cant advances

have been made in binary Si Ge and ternary Si Ge C alloys, where the built-1¡x x 1¡x¡y x y

in strain and the composition of pseudomorphic alloy layers on Si substrate modify

the band structure, energy gap as well as the band o®set.

An accurate knowledge of band alignment is essential for heterojunction device

design and performance analysis. Theoretical calculations based on the electronic

structures of heterointerfaces, involving a variety of SiGe layers on Si and Ge sub-

strates, have been employed to predict band o®set [12, 21]. However, empirical rules,

derived from experimental results, give better estimates. Experimental determination

of the valence band o®set (¢E ) between strained Si Ge and Si has been reportedv 1¡x x

by several workers using X-ray photoelectron spectroscopy (XPS) [22, 77]. MOS

capacitor structure has been used to evaluate the ¢E of group-IV alloy heterostruc-v

ture by several researchers [25, 78, 79]. Other methods such as capacitance-voltage

17

and temperature dependent current-voltage (I-V) characteristics have been used to

determine the ¢E at the Si/Si Ge interface [23, 24, 80].v 1¡x x

The measurement of Si/Si Ge C valence band o®set was performed by Rim1¡x¡y x y

et al. [81] using MOS capacitors. According to the study, Si/SiGeC valence band

o®sets decreased with increasing carbon in SiGeC. However, for a given lattice mis-

match to Si, the o®set for Si/Si Ge C was found to be larger than that for1¡x¡y x y

Si/Si Ge . This suggests that strain compensated thick SiGeC layers can be grown1¡x x

while maintaining a valence band o®set to Si. Extensive work on the e®ect of C

on band o®sets and fundamental band gap of Si Ge C alloys (under tensile or1¡x¡y x y

compressive strain) on Si (001) has been presented theoretically by Osten et al. [82].

The calculated results agree very well with the experimental data for the e®ect of C

on band structure in Si Ge C .1¡x¡y x y

Kolodzey et al. [83] reported the conduction and valence band o®sets in thick,

relaxed Ge-rich Si Ge C alloys grown by GSMBE using X-ray photoemission1¡x¡y x y

spectroscopy. Authors showed that C increased the valence band maximum of SiGeC

by +48 meV/%C as compared to Si. Chang et al. [84] studied the e®ect of substitu-+tional carbon on the valence band o®set of compressively strained p -Si Ge /(100)1¡x x

¡p -Si using optical absorption measurements. The valence band o®set of Si Ge /Si1¡x x

was reported to be reduced on incorporation of C with a negligible e®ect on the

conduction band alignment.

In this chapter, we ¯rst brie°y review the growth of strained Si Ge and par-1¡x x

tially strain compensated Si Ge C epitaxial layers using various techniques. The1¡x¡y x y

results of our study on the growth and characterization of Si Ge and Si Ge C1¡x x 1¡x¡y x y

layers using GSMBE and UHVCVD system are then presented. Material parameters

such as valence band o®set, doping pro¯le and generation lifetime of SiGe and SiGeC

heterolayers have been studied using MOS capacitor measurements.

2.1 Strained Layer Epitaxy

Several growth techniques including nonequilibrium ones have been employed to

grow ultrathin pseudomorphic group-IV alloy layers on Si. These can be categorized

as physical and chemical deposition techniques. A common physical deposition tech-

nique is molecular beam epitaxy which o®ers excellent control over the deposition

as it is possible to monitor the growth on the level of a monolayer. The ¯rst e®ort

18

oof Si Ge growth on Si was made by Kasper et al. [3] using MBE at 750 C. As1¡x x

the temperature was high, three dimensional growth took place and islanding was

observed. The ¯rst commensurate growth of Si Ge layer on Si was reported by1¡x x

oBean et al. [9], who used a low growth temperature (550 C). Eberl et al. [13] studied

the growth of Si Ge C on Si using solid source MBE at substrate temperatures1¡x¡y x y

o oof 450 C and 480 C with C incorporation varying from 0.08% to 0.76%. They used

pyrolytic graphite ¯lament as sublimation source for carbon in a Si MBE system. Os-

ten et al. [85]] reported the use of relaxed Si Ge bu®er layer to grow Si Ge C1¡x x 1¡x¡y x y

strained layer on Si by solid source MBE with low threading dislocation density. The

substitutional incorporation of carbon during growth of SiGeC strained layer by MBE

has been shown by Liu et al. [86]. Akane et al. [87] reported the formation of high

quality SiGeC heterostructure with sharp interface using gas source MBE (GSMBE).oThe growth temperature ranged from 550 to 700 C and the gas sources were Si H2 6

(99.99%) for Si, GeH (99.999%) for Ge and CH SiH (99% up) for C.4 3 3

The second method used to grow epitaxial ¯lms is chemical vapor deposition

(CVD). In conventional CVD, the processing is performed with partial pressures of¡3water vapor and oxygen greater than 10 Torr. The majority of this water vapor

and oxygen is due to outgassing from the walls of the chamber. Contaminants such

as oxygen and H O lead to precipitates that can result in extended lattice defects and2

increased surface roughness. This limits the temperature at which a good epitaxialo¯lm can be deposited at around 1000 C because at lower temperatures, lower growth

rates result in high contaminant incorporation. The UHVCVD system, which was¡9developed by Meyerson and his coworkers [88], uses base pressure of 1-5£10 Torr,

ogrowth pressure of 1 mTorr, and a growth temperature as low as 500 C. This system,

however, has a few limitations. As the source gas °ow is increased (at a constant

temperature) to increase the Ge concentration during a Si Ge layer growth, the1¡x x

growth rate increases. The deposition pressure is about 1-2 mTorr with deposition

ºrates around 10-20 A/min. Because of the low deposition pressure, gas depletion does

not occur as in a standard low pressure CVD reactor. In situ doping of both types is

possible and boron dopant content in the ¯lm is linear.

Another variant of low thermal budget growth of pseudomorphic alloy layer is

rapid thermal chemical vapor deposition (RTCVD). Using RTCVD growth technique,o ¡7Si Ge ¯lms have been grown at 900 C [89] at a base pressure of 10 Torr. Si Ge1¡x x 1¡x x

layers need to be deposited at lower temperatures to avoid relaxation and three di-

19

omensional growth. So the deposition temperature was reduced down to 625 C foroSi Ge and increased back to 850 C for Si-cap layers. Enhancement of Si Ge1¡x x 1¡x x

growth rate with increasing GeH is similar to the UHVCVD result [90, 91]. The4

maximum Ge incorporation before three dimensional growth from MBE study does

not seem to apply to LRPCVD/RTCVD. Layers with up to 45% germanium wereodeposited at 630 C [91]. One of the major problems with reducing the temperature

is increased oxygen incorporation in the Si Ge layers. The contamination source1¡x x

was traced to high oxygen content in SiH Cl . SiH does not have the same problem2 2 4

because the gas with much higher purity is available [92]. The oxygen incorporation

problem is avoided by the use of a load-lock and point-of-use ¯ltration of SiH Cl .2 2

RTCVD has been used and demonstrated for the growth of good quality SiGeC

¯lms [30, 93]. Growth of the epilayer can be controlled by both lamp or gas switchingoarrangements. It o®ers a wide range of control of growth temperature (600-900 C).

Liu et al. [94] reported a maximum carbon reduction of 0.013 by interstitial Si injec-otion for RTCVD grown SiGeC samples annealed below 1000 C in nitrogen ambient.

Epitaxial SiGeC alloys can also be deposited by chemical vapor deposition (CVD).

Atzmon et al. [95] reported good crystalline quality SiGeC alloy layers grown ato625 C using CVD technique when the Ge:C ratio of the deposited layer is higher

than 8.5:1. They also reported that the grown layer will be defective when Ge:C

<3:1, an amorphous layer will be formed eventually. Remote plasma enhanced chem-

ical vapor deposition (RPCVD) has also been used for the growth of Si and Si Ge1¡x x

epitaxy [96].

High quality metastable SiGeC ¯lm has been obtained by Strane et al. [97]] on Si

(x=0.14, y=0.007, and 0.014) by carbon implantation into preamorphized Si Ge1¡x x

ofollowed by solid phase epitaxy (SPE) at a temperature of 700 C for 30 min. In

all cases carbon regrows into substitutional lattice sites. The incorporation of car-

bon into substitutional sites occurs at concentrations about 3 orders of magnitude

above the equilibrium solid solubility without precipitating as carbides. The pulsed

laser induced epitaxy (PLIE) is an alternative technique for growing epitaxial thin

¯lms under thermal non equilibrium conditions, based on the fast melting induced

solidi¯cation process as reported by Finkman et al. [98].

20

2.2 Growth of Si Ge and Si Ge C Films1¡x x 1¡x¡y x y

Gas-Source MBE:

An abrupt compositional transience of the SiGe/Si interface is expected in gas-

source molecular beam epitaxy (GSMBE) grown layers, owing to the reduced Ge

segregation at the hetero-interface [99], than in those grown by solid source GSMBE

where Ge segregation has been recognized as an important issue. Another advantage

of GSMBE is that uniform thickness and composition can be obtained without sample

rotation. However, GSMBE is associated with autodoping of gas impurities, which

may a®ect the device characteristics.

Samples used in the present study were grown by custom built gas source MBE

(Diado-Hoxan-VCE-S2020) at the Research Center for Advanced Science and Tech-

nology (RCAST) Japan. The chamber size is about 70 cm in height and 45 cm in

diameter [100]. The distance from the gas valves to gas outlet nozzles in the growth¡10chamber is about 100 cm. The base and operating pressures were ¼3£10 and

¡64£10 Torr, respectively. Prior to growth, p-type Si (100) substrate with a resis-

tivity of about 10 ­-cm was chemically cleaned by brie°y dipping in a 2.5 wt% HF

solution for 15 sec followed by rinsing in running DI water. The substrate was then

introduced into the growth chamber immediately through a vacuum load lock andoºa nominally undoped Si bu®er layer of thickness 500 A was grown at 800 C with-

out substrate rotation. Nominally undoped strained Si Ge layer with x = 0.26 of1¡x x

ºthickness 300 A was grown using disilane (99.99% pure) and germane (99.99% pure).

ºThe growth rate was 5.7 and 9.6 A/sec for SiGe and Si layers, respectively. After theogrowth, the gas inlet valves were closed immediately at 800 C, and then the wafer

owas cooled down to below 350 C in an about 30 min while in vacuum, and ¯nally

withdrawn into the introduction chamber for unloading. The chamber pressure dur-¡7 ¡8ing the cooling down process was kept at about 10 - 10 Torr, and the cooling

rate was about 0.7 -1.0 K/sec for the ¯rst 5 min.

UHVCVD:

The characteristics that make the CVD process attractive when applied to com-

mercial ¯lm growth are excellent ¯lm uniformity, conformality, compatibility with

large area processing and relatively low apparatus costs. As a departure from con-

ventional chemical vapor deposition, ultra-high-vacuum chemical vapor deposition

21

has been developed to grow pseudomorphic alloy ¯lms at a very low substrate tem-

perature.

Figure 2.1: UHVCVD growth system.

Epitaxial Si Ge and Si Ge C ¯lms used in the present study were grown1¡x x 1¡x¡y x y

by UHVCVD system developed in the University of Texas at Austin. The deposition

system, shown in ¯gure 2.1, consists of two chambers constructed of 304L stainless

steel. A turbo pump backed by a mechanical pump is used to bring the load lock¡7chamber to pressures of 1£10 Torr or lower before transferring the wafer to the

main chamber. An 8-inch gate valve accomplishes isolation of the load-lock chamber

from the growth chamber. The growth chamber is pumped to a base pressure of

22

¡105£10 Torr using a turbomolecular pump. The substrate heater is attached to the

top of the chamber through a rod that is welded to a linear motion feed-through on

the top °ange of the chamber. The growth chamber consists of two in-situ analysis

facility: one is re°ection high-energy electron di®raction (RHEED) and another is

residual gas analyzer (RGA).

Table 2.1: Detail of Si Ge and Si Ge C ¯lms grown by GSMBE and1¡x x 1¡x¡y x y

UHVCVD.

Sample Description Si-cap Well Growth technique

º ºt (A) t (A)cap well

SG1 Si Ge 70 400 UHVCVD0:8 0:2

SG2 Si Ge 0 300 GSMBE0:74 0:26

SG3 Si Ge 50 400 UHVCVD0:6 0:4

SGC1 Si Ge C 70 " "0:795 0:2 0:005

SGC2 Si Ge C 70 " "0:69 0:3 0:01

SGC3 Si Ge C 0 " "0:69 0:3 0:01

SGC4 Si Ge C 70 " "0:685 0:3 0:015

SGC5 Si Ge C 0 " "0:685 0:3 0:015

SGC6 Si Ge C 50 " "0:56 0:4 0:04

Ex-situ cleaning of Si (100) substrate was done by using a 1:2, H O :H SO so-2 2 2 4

lution followed by a 20:1, HF (49%): DI-H O dip for native oxide removal and the2

surface was hydrogen passivated. The wafers were loaded into the load-lock cham-¡7ber which was pumped to about 1£10 Torr before transferring to the deposition

chamber. Samples were heated in the growth chamber from room temperature to the

deposition temperature within 5 min when the gas °ow was initiated. Although no18 3in-situ cleaning was employed, only low levels (<2£10 atoms/cm ) of oxygen was

detected at the epi-substrate interface by secondary ion mass spectroscopy (SIMS).18 3A carbon peak with concentration of 4£10 atoms/cm was also detected. 100%

disilane (Si H ), 10% germane (GeH ) diluted with helium and 20% methylsilane2 6 4

(CH SiH ) in helium were supplied to the deposition chamber through the mass °ow3 4

control systems. The gas °ows were adjusted to obtain the appropriate concentra-

tions of Ge and C within the ¯lm. The substrate was heated by infrared radiation

through a graphite chuck coated with pyrolytic boron nitride and the temperature

23

was controlled by a feedback technique through a pyrometer. The total pressure dur-

ing the deposition was kept constant in the range of 1 to 10 mTorr. The SiGe/SiGeCo ºsamples used in our study were grown at 550 C and consists of a 500 A Si bu®er layer,

ºfollowed by a »400 A SiGe/SiGeC layer. Completely strained Si Ge and partially1¡x x

strain compensated Si Ge C samples with controlled Ge-to-C ratios were used1¡x¡y x y

for the investigation. The crystallinity of the samples was monitored using re°ected

high energy electron di®raction immediately after or during deposition.

Properties of the Si Ge and Si Ge C ¯lms grown by GSMBE and UHVCVD1¡x x 1¡x¡y x y

are listed in Table 2.1.

2.3 Structural Characterization

The ¯lms have been characterized by Rutherford backscattering (RBS), secondary

ion mass spectroscopy (SIMS), high-resolution X-ray di®raction (HRXRD) and atomic

force microscopy (AFM).

Figure 2.2: Rutherford backscattering spectra of Si Ge (sample: SG2) ¯lm.0:74 0:26

24

2.3.1 Rutherford Backscattering

Rutherford backscattering analysis was carried out to estimate the composition

and thickness of the ¯lms. RBS is used for depth pro¯ling and layer removal of

¯lms by sputtering as used in SIMS, is not involved. However, damage or defects

are produced in the exposed ¯lms for RBS characterization. Figure 2.2 shows a+2typical RBS spectrum for a Si Ge ¯lm. The scattered He from the SiGe bu®er0:74 0:26

layer appears at higher energies while those from Si ¯lm and from the Si substrate

appear at lower energies. Simulation for this sample is also shown in ¯gure 2.2.

ºThe concentration of Ge and the thickness of SiGe are found to be 25% and 300 A,

respectively.

2.3.2 Secondary Ion Mass Spectroscopy

Secondary ion mass spectroscopy is a highly sensitive technique for determining

the concentration of di®erent elements of atomic number down to Z=1 with very low

Figure 2.3: SIMS depth pro¯le from Si Ge C (sample: SGC2) ¯lm.0:69 0:3 0:01

25

detection limit. In SIMS, an energetic beam of focused ions is directed to the sample

surface in a high or ultra-high-vacuum environment. The technique uses a primary ion

beam which bombards the surface of a sample, and the resulting sputtered secondary

ions are mass analyzed using a double focussing mass spectrometer or an energy

¯ltered quadruple mass spectrometer and detected. This method can be used to

acquire a variety of information about the surface, near surface, or bulk composition

of the sample, depending on the instrumental parameter. Since in SIMS technique

the specimen is etched layer by layer by an ion beam, the simultaneous detection of

secondary ions gives the depth pro¯le of the chemical species.

In the present investigation, SIMS analysis has been used to ¯nd out the Ge,

C and B concentration and to obtain the compositional pro¯le of UHVCVD grown

pseudomorphic Si Ge C ¯lm. Figure 2.3 shows a typical SIMS pro¯le of a1¡x¡y x y

Si Ge C ¯lm (SGC2). This spectrum shows a major C peak corresponding to0:69 0:3 0:01

»1%C and a Ge °at pro¯le corresponding to »30% Ge. The doping concentration in17 3the ¯lm is found to be 1-2£10 /cm . According to the SIMS depth calibration the

ºthickness of the active Si Ge C and Si-cap layers are observed to be »400 A1¡x¡y x y

ºand »70 A, respectively, in close agreement with the thickness calibrated by growthexperiment. The SIMS spectra show the presence of a low amount of oxygen in the

¯lm. It also shows the presence of C and O at the Si bu®er-layer/substrate interface

due to surface contamination before the growth. An in-situ cleaning of Si substrate

prior to growth is required to remove the undesired C and O contaminations.

2.3.3 High Resolution X-ray Di®raction

High resolution X-ray di®raction (HRXRD) provides a reliable, quantitative method

to study the e®ect of C on modifying the strain of Si Ge layer. The di®raction1¡x x

from a plane of atoms can be described using Bragg's law,∙ ¸¸¡1£ = sin (2.1)B2d

where, £ is the Bragg's angle at which a peak in the di®raction spectra occurs forB

a particular lattice spacing of d and ¸ is the wavelength of the X-ray. The measure-

ments were made relative to the substrate peak at (004) di®racting planes in the form

of intensity versus ¢£ using Cu-K radiation. The angular position of this peak can®

be compared to the position of the corresponding peak from a Si Ge /Si Ge C1¡x x 1¡x¡y x y

26

grown layer upon the substrate to determine the lattice mismatch to Si. According

to Vegard's rule, the lattice constant of Si Ge C ¯lms is written as1¡x¡y x y

a = a + x(a ¡ a ) + y(a ¡ a ) (2.2)SiGeC Si Ge Si C Si

ºwhere a is the lattice constant (5.431 A) of Si, a is the lattice constant (5.658Si Ge

º ºA) of Ge atoms and a is the lattice constant (3.546 A) of carbon atoms. FromC

Eqn. (1.1), increasing Ge fraction leads to a larger lattice constant of Si Ge1¡x x

system which causes the strain relaxation. On the other hand (cf. Eqn. (2.2)),

incorporation of lower lattice constant carbon atom (a <a <a ) in Si Ge alloyC Si Ge 1¡x x

leads to a decrease in lattice constant resulting in a strain compensated Si Ge C1¡x¡y x y

¯lm. But the amount of strain compensation due to C is in question and varies from

1:8.2 to about 1:12 in the literature. Considering the complete incorporation of C

in the substitutional site for low C concentration, SiGeC ¯lms show that 1% carbon

compensates the strain equivalent to »10% Ge.

Figure 2.4: (004) HRXRD spectra from Si Ge (sample: SG1) and Si Ge C0:8 0:2 0:69 0:3 0:01

(sample: SGC2) ¯lms.

Figure 2.4 shows a typical HRXRD spectra for Si Ge and Si Ge C ¯lms0:8 0:2 0:69 0:3 0:01

from the (004) plane. The strongest peaks at ¢µ = 0 correspond to di®raction from

27

the Si substrate. The increased perpendicular lattice constant in a compressively

strained Si Ge ¯lm causes a shift in the X-ray peak by ¢µ= -2129.2 arcsec with0:8 0:2

respect to the substrate (004) peak. The alloy peak for the partially strain com-

pensated Si Ge C ¯lm is found to be at -2127 arcsec. The e®ective strain in0:69 0:3 0:01

the ternary alloys was calculated using both symmetric (004) and asymmetric (224)

di®raction spectra [101]. The lattice parameter (a ) of the relaxed layer is given byr

[101]a + 2(C =C )a? 12 11 k

a = (2.3)r1 + 2(C =C )12 11

where a and a are the perpendicular and the in-plane lattice constants of the? ktetragonal structure, respectively and C (Si: 165.77 GPa and Ge: 128.53 GPa) and11

C (Si: 62.93 GPa and Ge: 48.26 GPa) are the corresponding elastic constants. A12

linear interpolation between Si and Ge has been used to calculate the elastic constant

of SiGe alloy. The e®ective strain factor (S) of a lattice mismatched ¯lm is given by

[101]

S = (a ¡ a )=(a ¡ a ) (2.4)r r ok

where, a is the bulk Si lattice parameter. Substituting various lattice parametero

values in Eqn. (2.4), e®ective strain factors are found to be 1.0 and 0.983 for sample

Si Ge and Si Ge C , respectively. This indicates that the binary Si Ge0:8 0:2 0:69 0:3 0:01 0:8 0:2

is fully strained where as ternary alloy is strain compensated due to C incorporation.

The full-width-half-maxima (FWHM) of Si Ge and Si Ge C ¯lms are found0:8 0:2 0:69 0:3 0:01

to be 342 and 499 arcsec, respectively. The crystalline quality of the ternary alloy

¯lm is found to degrade with higher Ge and C concentrations.

2.3.4 Atomic Force Microscopy

Semiconductor surface roughness is one of the important parameters which can

adversely a®ect the performance and reliability of devices. Available optical tech-

niques are often limited to 1-D quantitative analysis of roughness. However, atomic

force microscopy has the capability of acquiring 3-D topographs over an extended

scale with a high resolution. It requires minimal sample preparation, and can be used

for a wide range of materials in di®erent ambients. The digitized surface topography

is represented by a 2-D array whose elements express the height information at each

28

point of the 2-D scanned image grid. A typical measure of surface roughness is the

root mean squared (rms) roughness, Z , which is de¯ned as [102]rmssP2(Z ¡ Z )i avg

Z = (2.5)rmsN

where, Z is the height at the i-th sampling point (x,y), N is the number of datai

points and Z is the average Z . Atomic force microscope (Digital Instrumentsavg i

Nanoscope II) under tapping mode was used to study the surface morphology of the

¯lms. The variation of the surface morphology of epitaxial Si Ge C ¯lms as a1¡x¡y x y

function of Ge and C concentration has been studied.

Figure 2.5: 5¹m x 5¹m AFM scan of ¯lm surface. (a) Si Ge sample (SG3),0:6 0:4

º ºroughness»22 A rms, (b) Si Ge C sample (SGC6), roughness»1.3 A rms.0:56 0:4 0:04

Figures 2.5(a) and (b) are atomic force micrographs of Si Ge and Si Ge C0:6 0:4 0:56 0:4 0:04

º¯lms (400 A). The scan was taken on a 5¹m x 5¹m area where each data point rep-

resents the average height of a 10 nm x 10 nm area. Figure 2.5(a) shows the surface

undulations due to strain ¯elds from underlying mis¯t dislocations in the relaxed

ºSi Ge ¯lm. A smoother topography (»1.3 A rms roughness) is observed from0:6 0:4

¯gure 2.5(b) for a Si Ge C ¯lm showing the e®ect of carbon addition in im-0:56 0:4 0:04

proving the surface roughness by strain compensation. The above result con¯rms that

29

addition of only a small amount of carbon in higher Ge content binary ¯lms (above

the critical thickness) may lead to the formation of relatively improved quality par-

tially strain compensated Si Ge C ¯lms. Figure 2.6 shows an AFM image of1¡x¡y x y

ºSi Ge C ¯lm with rms roughness of 11.8 A. The Z values for several samples0:69 0:3 0:01 rms

are listed in Table 2.2. It is noted that the value of Z for Si Ge C samplerms 0:69 0:3 0:01

is slightly higher compared to Si Ge . The surface roughness of pseudomorphic0:74 0:26

¯lm is found to increase slightly with increase of either Ge or C concentration.

Figure 2.6: A typical AFM topograph of Si Ge C (SGC2) showing the improve-0:69 0:3 0:01

ºment in surface roughness due to carbon incorporation (roughness»11.8 A rms).

Table 2.2: Surface roughness of SiGe and SiGeC ¯lms

ºSample Z (A)rms

Si Ge 220:6 0:4

Si Ge C 1.30:56 0:4 0:04

Si Ge 7.580:74 0:26

Si Ge C 11.80:69 0:3 0:01

30

2.4 Electrical Characterization

Metal-oxide-semiconductor (MOS) capacitor structure has been used to study

the hole con¯nement characteristics in SiGe and SiGeC layers. Valence band o®set,

doping pro¯le, unconsumed Si-cap layer thickness, threshold voltage, and generation

lifetime of SiGe and SiGeC heterolayers have been studied by the electrical measure-

ments of test capacitors.

2.4.1 MOS Capacitor Fabrication

MOS capacitor structures were fabricated on SiGe and SiGeC epitaxial layers

ºby depositing aluminum dots of typically 1000-2000 A thick on gate oxide through

a metal mask to form gate electrodes of 0.5 mm in diameter. Back contact (Al)

was formed on the crystalline Si substrate. Sample cleaning, oxidation setup and

oxide growth process will be described in Chapter 3. Oxide growth conditions for

the formation of test capacitors for the present study are listed in Table 2.3. MOS

structures were used to measure the capacitance-voltage (C-V) and capacitance-time

(C-t) characteristics for studying the electronic properties of SiGe and SiGeC ¯lms.

Table 2.3: Processing condition for the oxide growth

Sample Group-IV alloy Oxidation

SG1N Si Ge NO-plasma 2 min0:8 0:2

SGC1O Si Ge C O -plasma 2 min0:795 0:2 0:005 2

SGC2O Si Ge C "0:69 0:3 0:01

SGC4O Si Ge C "0:685 0:3 0:015

2.4.2 Capacitance-Voltage Characteristics

Figure 2.7 shows the MOS capacitor structure used for the characterization of

Si/Si Ge /Si quantum wells. The valence band energy diagram (not to the scale)1¡x x

is also presented showing the formation of a well in the valence band. Typical high

frequency (1 MHz) C-V characteristics of a MOS capacitor fabricated using plasma

grown oxide (SG1N) is shown in ¯gure 2.8. The plateau in accumulation region

31

clearly shows the hole con¯nement at the Si/Si Ge interface at a lower gate bias1¡x x

value. When the capacitors are driven from deep depletion, accumulated holes reside

initially in the Si Ge layer and the MOS structure exhibits a lower capacitance1¡x x

Figure 2.7: Schematic diagram of a Si/Si Ge /Si MOS capacitor.1¡x x

Figure 2.8: High frequency (1 MHz) C-V (HFCV) characteristics of a MOS capacitor

(sample: SG1N). Simulated HF and low frequency C-V (LFCV) characteristics are

also shown.

32

due to hole con¯nement at SiGe layers giving rise to the plateau. As the structure

is biased more negatively, the capacitance saturates to the oxide capacitance in the

accumulation region. The simulated high frequency and low frequency characteristics

using 1-D Poisson solver are also shown in ¯gure 2.8. Experimentally measured

structural and material parameters used in simulation were: interface state density11 ¡2 ¡1 17º(6.0 £10 cm eV ), oxide thickness (90 A), and a doping concentration (1£10

¡3cm ). As seen from the ¯gure 2.8, a moderately good ¯t is obtained between the

experiment and simulated capacitance characteristics.

2.4.3 Extraction of Si-cap Layer Thickness

MOS C-V characteristics of Si/Si Ge heterostructure, presented in ¯gure 2.8,1¡x x

have been used to extract the apparent doping pro¯le and the unconsumed Si-cap

layer thickness. During oxidation, Si from the wafer is consumed by the growing

oxide, resulting in a loss of approximately 0.44t of Si where t is the oxide thickness.ox ox

Figure 2.9: Apparent doping concentration vs. distance from the Si/SiO interface.2

From the high frequency capacitance-voltage characteristics presented in ¯gure

2.8, the depletion depth (X ) and apparent doping (N ) as a function of applieddHF appHF

33

gate potential (V ) are obtained as [23, 26]G

∙ ¸1 1

X (V ) = ² ¢ ¡ (2.6)dHF G SiC (V ) CHF G ox

and ∙ ¸1± 2C (V )1 q² GSi HF

= ¢ (2.7)N (V ) 2 ±VappHF G G

where ² is the Si permittivity, C is the gate oxide capacitance per unit area,Si ox

C (V ) is the voltage dependent capacitance per unit area of the heterostructures,HF G

and q is the electronic charge.

Using Eqns, (2.6) and (2.7), the computed apparent doping as a function of de-

pletion depth is shown in ¯gure 2.9. The apparent doping pro¯le plot exhibits three

peaks (from left to right) corresponding to: (a) accumulation of mobile holes at the

Si/SiO interface (at distance, X =0), (b) accumulation of holes at the Si/Si Ge2 dHF 1¡x x

ºheterojunction at X =30 A (shown at the inset of the ¯gure 2.9), and (c) the maxi-dHF

ºmum depletion depth (at X =816 A), where the change in sign of apparent dopingdHF

16 ¡3occurs. Substrate doping concentration (N » 4 £ 10 cm ) is also obtained fromB

the plot of N vs. X as shown in ¯gure 2.9. The thickness of the unconsumedappHF dHF

ºSi-cap layer is found to be » 30 A as shown in ¯gure 2.9 (inset).

2.4.4 Extraction of Threshold Voltages of Strained Layers

Both buried and surface channel co-exist in a heterostructure MOS capacitor with

a Si-cap layer [103]. Estimation of the threshold voltage of the individual channel in

such a structure is important for the device and circuit design. Threshold voltages

of the SiGe-well at Si/Si Ge interface (V ) and the Si-cap at Si/SiO interface1¡x x T H 2

(V ) have been extracted from the C-V characteristics (¯gure 2.8) and from the plotT S

of N vs. V (¯gure 2.10). The measured values of V and V are found toappHF G T H T S

be 0.7 V and {0.8 V, respectively, and have been veri¯ed using 1-D Poisson solver.

Gate voltage dependence of hole charge in the buried (Q ) and surface channel (Q )H S

of the heterostructure MOS capacitor has been simulated and is shown in ¯gure 2.11.

The plot indicates values for V (0.5 V) and V ({0.75 V) in agreement withT H T S

the measured values. Figure 2.11 shows charge screening e®ect associated with a

34

buried channel structure. The saturation of the SiGe-channel hole density can be

explained as follows; once a large number of holes °ows in the Si-cap layer, the

Figure 2.10: Experimental apparent doping vs. gate voltage characteristics for a

Si/Si Ge /Si MOS capacitor.1¡x x

Figure 2.11: 1-D numerical simulation of hole charge in buried channel (Q , SiGe)H

and in surface channel (Q , Si-cap) as a function of gate voltage. The thresholdS

voltages V and V are indicated.T H T S

35

charge screens the gate potential and fewer holes are added to the SiGe-channel with

increasing gate voltage, limiting the maximum concentration of high-mobility holes

[104, 105, 106]. In the present case, a gate bias beyond V={2.25 V results in the

saturation of hole population in Si Ge quantum well while carrier population in1¡x x

the Si-cap continues to increase. This leads to a continuous increase in the potential

at the surface (Ã ), keeping the potential at the top Si Ge /Si hetero-interfaceS 1¡x x

(Ã ) almost constant. That is why number of holes increases in the Si-cap layer thanH

in the SiGe-channel with increasing gate voltage. The point at which the number of

holes in the Si Ge well equals the number in the Si-cap is called the \cross-over1¡x x

voltage". The dependence of the cross-over voltage on di®erent parameters will be

treated in detail in Chapter 5.

2.4.5 Extraction of Valence Band O®set (¢E )v

To determine the valence band o®set, an analytical model that relates the V andT H

¢E has been proposed in the literature [107]. The buried channel threshold voltagev

(V ) and the surface channel threshold voltage (V ) depend on the structuralT H T S

parameters of the capacitor and are given by [107]

∙ ¸t tcap ox

V = V + Ã ¡ qN X + (2.8)T H F B T H B dm² ²Si ox

and

qqN XB dmV = V + Ã ¡ 1 +H(Ã ) (2.9)T S F B T S H

Cox

where

∙ ¸Ã ¡ ÃT H H

H(Ã ) = h exp (2.10)H okT=q

¢Evà = 2Á + (2.11)T H F

q

and

2h = 2² N kT=(qN X ) (2.12)o SiGe B B dm

36

where, V is the °atband voltage, Ã is the potential at threshold at the topF B T H

Si/SiGe interface, Ã is the potential at threshold at the Si/SiO interface, N is theT S 2 B

e®ective doping concentration in the bulk of the semiconductor, X is the maximumdm

depletion layer width in strong inversion, t is the Si-cap layer thickness, t is thecap ox

oxide thickness, ² is the oxide permittivity, ² is the Si permittivity, k is theox SiGe

Boltzmann constant, and T is the absolute temperature.

By subtracting Egn. (2.8) from Eqn. (2.9) and rearranging, a system of two

nonlinear Eqns. (2.13) and (2.14) with ¢E and à as unknown are obtained [23, 26]:v H

t C (¢V +¢E )cap ox v∙ ¸2T[1 + C + ] ¡ 1oxkT ² qN XSi B dm¢E = Ã ¡ 2Á + ln (2.13)v H Fq ho

and

² (à ¡2Á ) 2Si H F∙ ¸[ ] ¡ 1kT qN X tcapB dmà = à ¡ ln (2.14)H T Hq ho

where, Á is the Fermi potential, Ã is the potential at the Si/SiGe interface, andF H

¢V = V - V (the gate voltage window). Valence band o®sets calculated forT T H T S

SiGe and SiGeC layers using this technique are presented below.

a) Valence Band O®set: Si Ge1¡x x

Valence band o®set of the Si/Si Ge interface has been evaluated using the1¡x x

experimental and simulated C-V characteristics. The experimental and simulated

valence band o®set values of 157 meV and 140 meV, respectively, for Si/Si Ge0:8 0:2

heterostructure have been obtained by iterating Eqns. (2.13) and (2.14). Doping

concentration and threshold voltages values obtained from ¯gures 2.9, 2.10 and 2.11,

respectively, were used in simulation. Figure 2.12 shows a comparison of measured

¢E as a function of Ge concentration. When compared with the reported exper-v

imental ¢E values [80, 108, 109, 110, 111, 112], it is seen that the agreement isv

fairly good for Ge mole fraction in the range 0<x<0.25. The data from Iyer et al.

[110] was obtained on graded-base Si/SiGe heterojunction bipolar transistors and is

indicated by the space enclosed by the broken lines in ¯gure 2.12. A larger value of

¢E , reported by Nauka et al. [78], may be attributed to their assumption that thev

position of Fermi energy (E ) is estimated at 0 K without any consideration of theF

band bending of the Si barrier region [79]. On the other hand, ¢E evaluated by Luv

37

et al. [79], who included the e®ect of the band bending near the hetero-interface on

E , resulted in a smaller value. This was ascribed to the partial relaxation of strainF

in the Si Ge . The above band bending was introduced to satisfy charge neutrality,1¡x x

since carriers are transferred to the semiconductor with lower band-edge energy level

at the hetero-interface, and in°uence the position of E .F

Figure 2.12: Summary of experimentally measured ¢E in strained Si/Si Ge onv 1¡x x

(100) Si.

b) Valence Band O®set: Si Ge C1¡x¡y x y

To determine the valence band o®set for Si/Si Ge C heterostructure with1¡x¡y x y

di®erent carbon concentrations, C-V characteristics of ternary alloy MOS capacitors

have been used. The extracted experimental ¢E of 201 meV for Si Ge Cv 0:69 0:3 0:01

(187 meV for Si Ge C ) is obtained by iterating Eqns. (2.13) and (2.14) using0:685 0:3 0:015

the measured values of doping concentration and threshold voltages. The results are

presented in ¯gure 2.13. When compared to reported experimental [81, 84, 113] and

38

computed values [82], for similar types of heterolayers, it is seen that the agreement

is fairly good. Solid line in ¯gure 2.13 represents ¢E for fully strained Si Ge asv 1¡x x

a function of Ge concentration using the empirical prediction of 0.74x eV, where x

Figure 2.13: Summary of experimental measurements and computed values (open

square) of ¢E in partially strain-compensated Si/Si Ge C on (100) Si (Dottedv 1¡x¡y x y

line is to guide the eye for the experimental points of partially strained Si Ge C .1¡x¡y x y

is the Ge mole fraction. According to Vegard's rule, 1% C compensates the strain

equivalent to 8.5-10% Ge. The e®ective Ge concentration in ternary sample presented

in ¯gure 2.13 is based on the assumption of strain compensation ratio of 1:10 due to

the incorporation of C. Hence the e®ective Ge concentration for Si Ge C and0:69 0:3 0:01

Si Ge C samples are 20 and 15%, respectively. Experimental ¢E values of0:685 0:3 0:015 v

Si Ge C samples with two di®erent C concentrations are shown in ¯gure 2.13.1¡x¡y x y

From the ¯gure, it is noted that as the carbon content is increased the lattice mismatch

decreases for SiGeC and so also the band o®set. However, for a given mismatch to

Si, the band o®set values for SiGeC samples are larger than the measured values

39

for strained SiGe. Our measurements show 24§3 meV reduction in valence band

discontinuity for 1% C incorporation. This observation is in agreement with the

results reported by Chang et al. [31] from the photoluminescence studies on ternary

alloys.

2.4.6 Generation Lifetime (¿ ) of Alloy Layerg

Generation lifetime is an important parameter for the determination of the qual-

ity of a epilayer/heterolayer or a device and re°ects the e®ect of deep-center levels

caused by defects and impurities introduced during device processing. A long life-

time is essential to make low leakage junctions as needed for heterojunction bipolar

Figure 2.14: Schematic band diagram for generation of hole-electron pairs in the

depletion region of a MOS capacitor.

transistors and p-i-n photodiodes. A schematic band diagram for generation of hole-

electron pairs in the depletion region of a MOS capacitor is shown in ¯gure 2.14.

Initially, a large depletion region forms in the semiconductor. As minority carriers

are generated in the depletion region, they are swept to the Si/SiO interface where2

40

they accumulate in an inversion layer. The majority carriers generated °ow to the

edge of the depletion region where some of them neutralize the ionized impurity sites

reducing the width of the depletion region. Thus, the width of the depletion region

relaxes as the inversion layer forms until an equilibrium is reached. So the MOS ca-

pacitance changes with time due to the change in depletion region width. There are

several methods available for the determination of minority carrier generation lifetime

[114, 115, 116, 117], a popular method is Zerbst technique. It is based on the C-t

(high frequency capacitance vs. time) transient measurements at a ¯xed gate voltage

after pulsing the MOS capacitor into deep depletion [118].

Figure 2.15: Transient response of capacitance-time plot for a partially strained

Si Ge C MOS capacitor. Zerbst plot of the capacitor has been shown (inset).0:795 0:2 0:005

Slope yields generation lifetime of 1.2 ¹s.

An important feature of the Zerbst technique is the linear dependence between

the minority carrier generation rate and generation volume in the semiconductor

depletion region and the slope of the plot yields the generation lifetime. Generation

lifetime for Si Ge C sample extracted from the C-t characteristics, is shown0:795 0:2 0:005

41

in ¯gure 2.15. The procedure used to determine lifetime is to record normalized MOS

capacitance (C) versus time (t) after the application of a large depleting voltage step

(accumulation voltage = -1.5 V and depletion voltage = 1.5 V). It is observed that

the values of C (minimum capacitance) and C (¯nal capacitance) are 0.42 Cmin fin ox

and 0.52 C , respectively, where C is the oxide capacitance. The correspondingox ox

plot of generation rate vs. generation volume is shown in the inset of ¯gure 2.15.

Lower bandgap of Si Ge C (compared to Si) layer results in a larger intrinsic0:795 0:2 0:005

carrier concentration [119]. For Si/Si Ge C /Si sample, a bandgap reduction0:795 0:2 0:005

of 155.5 meV [31] is used in our analysis with calculated intrinsic carrier concentration11 ¡3(n (Si)exp(155.5/2kT) = 2.9£10 cm ) at room temperature. A generation lifetimei

of 1.2 ¹s is found for Si Ge C ¯lm. According to Shivaram et al. [120] the0:795 0:2 0:005

generation lifetime does not degrade due to the addition of C to SiGe system. On

the other hand, ¿ of SiGeC is found to be lower than that of Si Ge [119] due tog 0:82 0:18

C incorporation in SiGe strained layers [121, 122]. The results indicate that carbon,

Table 2.4: Minority carrier lifetime in Si, SiGe, and SiGeC heterolayers.

Sample Doping ¿g

¡3(cm ) (¹s)15< 100 >CZ Si [119] 5£10 9

15Bulk Si [123] 2.6£10 515Control Si (this work) 5£10 5.617Si Ge [119] 3£10 1.450:82 0:18

17Si Ge [122] 5£10 1.60:82 0:18

17Si Ge [124] 2.5£10 2.60:9 0:1

17Si Ge (this work) 2£10 1.40:8 0:2

17Si Ge C [122] 5£10 0.120:8 0:18 0:02

17Si Ge C (this work) 2£10 1.20:795 0:2 0:005

which creates a strong perturbation in the SiGe lattice, may produce some localized

trap centers to degrade the lifetime and carrier transport characteristics. Several

reported ¿ values for Si, SiGe and SiGeC ¯lms are compared in Table 2.4.g

42

2.5 Summary

High quality strained Si Ge and partially strain compensated Si Ge C1¡x x 1¡x¡y x y

layers have been grown using molecular beam epitaxy and ultra-high-vacuum chemical

vapor deposition system. The concentration of Ge and C, layer thicknesses and the

strain state of grown ¯lms have been determined by RBS, SIMS and high resolution X-

ray di®raction study. The AFM study has revealed the improvement of rms roughness

on incorporation of a small amount of C.

High frequency capacitance-voltage pro¯ling has been used to measure the appar-

ent carrier concentration and unconsumed Si-cap layer thickness. Poisson simulation

of MOS capacitors has been used to determine hole densities in the Si-cap and the

SiGe/SiGeC-channel. Measured threshold voltages of MOS capacitors have been

used to determine the valence band o®sets in binary and ternary heterostructures.

Extracted valence band o®sets are found to be in good agreement with the values

reported in the literature.

Incorporation of C lowers the valence band o®set of the ternary alloy compared

to those in Si Ge with the same Ge mole fraction. On the other hand, for a given1¡x x

lattice mismatch to Si, valence band o®sets for the SiGeC samples are larger than

the measured values for strained SiGe. A reduction of valence band o®set of 24§3meV/%C is obtained in ternary alloy as compared to SiGe alloy. Minority carrier

generation lifetime in partially strain compensated Si Ge C ¯lms grown by0:795 0:2 0:005

UHVCVD has been found to be 1.2 ¹s using Zerbst technique.

43

Chapter 3

Ultrathin Gate Oxides on

SiGe/SiGeC Layers

A critical step for the device fabrication is to grow a high quality oxide layer which

could be used for gate, mask and device isolation. Formation of high quality gate

oxide is the key to the fabrication of high-speed metal oxide semiconductor devices.

ºThe requirements for ultrathin gate oxides (< 100 A) in VLSI/ULSI MOS are: high

quality Si/SiO interface, low defect density, good barrier properties against impurity2

di®usion, stability under hot carrier stress and radiation, low thermal budget and

manufacturability. Grunthaner et al. [125] showed that the transition region between

Si and SiO comprises of a non-stoichiometric layer which contains species such as2

ºSi O and Si O followed by a 10-40 A strained SiO . The non-stoichiometric layer2 2 2 2

results primarily from incomplete oxidation. Also, an intrinsic stress arises from a

molar volume expansion (causing a compressive stress in SiO and tensile stress in2

Si at the interface) which occurs due to the structural di®erences in SiO and Si2

when Si is transformed into SiO [126, 127]. Strained region at the interface makes2

the interface susceptible to defect formation under hot carrier stress and exposure to

ionizing radiation. The growth of gate-quality oxides on binary/ternary alloys is a

challenging issue. A brief review of oxidation studies made on SiGe and SiGeC ¯lms

is presented below.

44

3.1 Oxidation of SiGe/SiGeC Films

3.1.1 Thermal Oxidation

Considerable work has been done on the thermal oxidation of strained Si Ge1¡x x

and partially strained Si Ge C alloys in order to get a high quality oxide/semi-1¡x¡y x y

conductor interface. Thermal oxidation of binary SiGe and ternary SiGeC alloy

gives rise to selective oxidation of Si, resulting in Ge pile-up [37, 128] at the ox-

ide/semiconductor interface.

Oxidation of SiGe Films:

Several research groups have reported oxidation of strained SiGe ¯lms at di®erent

temperatures [32, 33, 35, 36, 128, 129, 130, 131]. Fathy et al. [129] and Nayak et al.

[128] have studied the wet oxidation behavior of Ge implanted n-Si(100) with di®erento oGe concentrations between 900 C and 1000 C for di®erent oxidation times. The Ge

pile-up, due to the rejection of Ge from the oxidation front, led to the formation of

a Ge-rich layer at the oxide-substrate interface. A further study on Ge implanted Si

[132] con¯rmed the above results on steam oxidation. LeGoues et al. [32] observed

di®erent oxidation rates of epitaxial SiGe ¯lm in dry and wet ambients. Results

showed the enhancement of wet oxidation rate in the presence of Ge at the Si/SiO2

interface. However, the rate of dry oxidation remained una®ected. The authors

proposed that Ge acted like a catalytic agent. It was also shown that the wet oxidation

rate of undoped Si Ge layer was 2-4 times higher than that of bulk-Si. In both0:8 0:2

processes, Ge did not di®use into the substrate but found to pile-up at the interface

during oxidation.

Liou et al. [133] extended the study of binary alloy oxidation for varying Ge con-ocentrations up to 50%. Oxide grown at 880 C was studied using Auger spectroscopy.

Ge concentration in the SiGe layer was found to play an important role in the for-

mation of Ge-rich oxide layer. For SiGe with Ge concentration below 50%, Si was

selectively oxidized and only one Ge-rich layer was formed at the oxide/substrate in-

terface. On the other hand, for SiGe with Ge concentration above 50%, two Ge-rich

layers were formed after oxidation with one at the oxide/substrate interface and the

other at the oxide surface. Ahn et al. [131] and Kar et al. [35] also studied theo owet and dry oxidation behaviors at temperatures of 900 C and 1100 C, respectively.

45

The Ge pile-up into deep levels was observed accompanied by strain relaxation in

pseudomorphic SiGe heterolayers.oWu et al. [134] reported the growth of oxides by dry oxidation at 900 C with

high Ge content (Si Ge ). Thin oxides grown at a high temperature on Si Ge0:3 0:7 0:3 0:7

showed a strong dependence on oxide thickness and as thickness was reduced from 50

º ºA to 30 A, oxide quality improved. This was attributed to the formation of relaxed

Si Ge layer which remained stable during oxidation. The possible reason for strong0:3 0:7

ºthickness dependence may be due to lower GeO content formed in thinner (30 A)2

oxide rather than strain relaxation related to surface roughness or defects.

Oxidation of SiGeC Films:

Bair et al. [34] and Atzmon et al. [135] carried out the wet oxidation on amorphousoand crystalline SiGeC layers at the temperature range 700-950 C. The ¯lm areal den-

sities and microstructure were assessed using Rutherford backscattering spectroscopy

and transmission electron microscopy (TEM). A nearly pure layer of SiO with ap-2

proximately 1 at% carbon was formed, with Ge being rejected from the oxide at all

temperatures. At low temperatures, the oxide formed was very thin, Ge piled up

at the oxide/¯lm interface. At higher temperatures, a network of nanocrystals was

observed which was believed to provide a grain boundary di®usion path redistributed

throughout the remaining layer. It was proposed that the Ge layer had inhibited

oxidation at lower temperatures, whereas its removal resulted in increased oxidation

rates at higher temperatures.

Liu et al. [94] reported the oxidation of Si Ge C alloys giving rise to Ge-1¡x¡y x y

enriched Si Ge layer and the formation of 3C carbide precipitate as observed1¡x x

by Fourier transform infrared spectroscopy. Bera et al. [37] reported the oxida-

tion on Si Ge C ¯lms by rapid thermal oxidation process at a temperature of1¡x¡y x y

o1000 C. X-ray photoelectron spectroscopy results indicate the segregation of Ge at the

SiO /Si Ge C interface, a thin GeO layer at the oxide surface, and elemental2 1¡x¡y x y 2

Ge in the oxide. Cuadras et al. [136] investigated the thermal oxidation of strained

Si Ge C layers and the in°uence of the thermal process on the structure of the1¡x¡y x y

layers. Ge pile-up was found in the epitaxial layer near the oxide-layer interface by

XPS and SIMS depth pro¯le measurements.

In general, most of the studies reported Ge pile-up and the formation of a Ge-rich

layer at the oxide/substrate interface due to the rejection of Ge and the reduction

46

of substitutional carbon from the oxidation front in case of a SiGeC layer. In view

of the above problems faced by conventional high temperature oxidation, there is a

need for low thermal budget processing of strained SiGe and SiGeC layers for device

applications.

3.1.2 Low-Temperature Oxidation

To prevent Ge segregation, researchers have explored low-temperature processing

using ion beam [42, 137], rf oxygen plasma [138], ECR-plasma [139, 140], UV [43, 141]

for growing ultrathin gate oxides on strained Si Ge [142, 143]. Agarwal et al. [144]1¡x x

showed the formation of two phase oxides consisting of SiO and GeO using UV light2 2

in air at room temperature. The increased oxidation rate (by a factor of ¼2) withincreasing Ge content is attributed to weak Si-Ge bond energy in comparison with

Si-Si bond energy. Chen et al. [145] have investigated UV O assisted oxidation3

oof Si Ge ¯lms at 200 C and reported that Ge is incorporated in the growing0:84 0:16

oxide and does not segregate at the oxide/SiGe interface. However, Craciun et al.o[146] have reported that the oxide layer grown at 550 C contains SiO with some2

Ge incorporated (» 8%) in the oxide and the majority of Ge forms a Ge-rich layer

directly beneath the oxide layer. Madsen et al. [43] have reported ozone/atomic

oxygen assisted direct oxidation of SiGe. XPS studies on samples processed in theotemperature range 125-530 C indicate that Ge is incorporated into the growing oxide

as GeO . Increase in the oxidation temperature causes a decrease in Ge incorporation2

in the growing oxide and the ¯lm becomes Si-rich.

Low-temperature oxidation of SiGe without any Ge pile-up has been reported

using ion beam [42] and ECR plasma [139]. Oxides with low leakage current, interface

state density and ¯xed oxide charge density have been grown using ECR microwave

(250 W at 2.45 GHz) plasma discharge at di®erent substrate temperatures [140].

Low energy ion beam oxidation with energies ranging from 100 eV to 1 keV has

been shown to result in a fully oxidized SiGe layer at room temperature. Due to

preferential sputtering and decomposition, the oxide ¯lms show lower Ge content

than in the SiGe alloy and the Ge content approaches the bulk content at lowest ion

energies. The range of ion energies used might often be very crucial as high energy

results in damage or defect on the surface.

Plasma processing, now being routinely used in the device fabrication, is an al-

47

ternative technique for low-temperature oxidation. Riley et al. [142] studied the

oxide growth by plasma anodization of Si Ge alloy. X-ray photoelectron spec-0:84 0:16

tra revealed the absence of Ge segregation during thin oxide growth with the onset

of partial segregation occurring for thicker oxides. Depth pro¯ling shows that the

plasma oxide is stoichiometric in form with the exception of a small percentage of Ge

atoms left in their unoxidized state. Rappich et al. [143] reported the existence of

SiO and Si-O-Ge phases for anodic oxides through the study of X-ray, photoelectron,2

Auger and FTIR spectra. Plasma anodization led to a decrease of defect states at

the oxide/SiGe interface.

Table 3.1: Electrical and interfacial properties of di®erent oxides on SiGe and SiGeC

alloy layers.

Oxidation Sub. temp. Group-IV Ge Q /q Df it

o ¡2 ¡2 ¡1technique ( C) alloy pile-up (cm ) (cm eV )11 12Rapid 905-1010 Si Ge [128] Yes -7.5£10 2£100:78 0:22

thermal11 12" 1000 Si Ge C [37] Yes -9.5£10 3.6£100:8738 0:113 0:0132

12 13Thermal 900 Si Ge [131] Yes -2.86£10 1.51£100:9 0:1

10 10" 900 Si Ge [36] No -5.6£10 5.9£100:3 0:7

UV 550 Si Ge [141] No - -0:8 0:2

" 400 Si Ge [43] Yes - -0:85 0:15

11 11ECR 400 Si Ge [139] No -1.5£10 9.2£100:8 0:2

10 11" 300 Si Ge [140] No -5.0£10 1.5£100:85 0:15

11Anodic 100 Si Ge [124] No - 4.6£100:9 0:1

oxidation

" 450 Si Ge [143] No - -0:74 0:26

RF plasma 200 Si Ge [147] No - -0:975 0:025

10 11Microwave 150-200 Si Ge [148] No 2.45£10 3.1£100:74 0:26

plasma11 11" " Si Ge C [149] No 3.7£10 5.0£100:69 0:3 0:01

Mukhopadhyay et al. [148] demonstrated that SiGe ¯lms can be oxidized at a

48

otemperature as low as 200 C using microwave oxygen plasma. While thermally oxi-

dized sample showed the formation of an intermediate oxidation state for Ge at the

interface, plasma oxidation resulted in complete oxidation of Ge to GeO . The elec-2

trical properties of the oxide after post-oxidation and post-metal annealing indicated

moderately low values of ¯xed oxide charge and interface trap densities. From the

above discussions, it is clear that a low temperature oxidation of strained SiGe ¯lm

is essential to achieve a high quality gate oxide while maintaining the pseudomor-

phic nature of the ¯lm. The ¯xed oxide charge densities (Q /q) and the mid-gapf

interface state densities (D ) of oxides grown by di®erent methods on Si Ge andit 1¡x x

Si Ge C heterolayers are listed in Table 3.1.1¡x¡y x y

It is evident from Table 3.1 that though a lot of work has been done on the low

temperature oxidation of binary SiGe alloy, not much attention has been paid on the

oxidation of ternary SiGeC alloys. In the following sections, the results of studies on

low temperature microwave plasma oxidation of Si Ge C alloys are presented.1¡x¡y x y

The electrical and interfacial properties of oxides such as charge-to-breakdown, ¯xed

oxide charge density and interface state density have been characterized and compared

to those of thermally grown oxide ¯lms.

3.2 Experimental Setup

The experimental setup of microwave plasma cavity discharge system used for the

low-temperature growth of oxide ¯lms is shown in ¯gure 3.1. The setup was built by

modifying a commercial microwave oven. The system comprises a microwave cavity3(37x37x26 cm ) with a magnetron of power 700 W at a frequency 2.45 GHz. The

power is transported to the cavity through a rectangular waveguide with built-in

isolators. The reactor consist of two parts, viz., a high purity quartz beljar and a

stainless steel base plate with gas and vacuum connections, with substrate holder and

a thermocouple for measuring the substrate temperature. It is placed inside the cavity

for an exposure to the microwave energy. The dimensions of the quartz chamber are

as follows: 78 mm in outer diameter, 74 mm inner diameter and approximately 120

mm in height. In order to °ow the gas uniformly inside the chamber to improve the

uniformity of growth, tiny holes were drilled on the closed end of the inlet tube. The

stainless steel pedestal which was projected out from the center of the base plate to

a height of 40 mm acted as the substrate holder. A thermocouple attached to the

49

pedestal was used for monitoring the substrate temperature. A mechanical rotary

pump was used to evacuate the chamber and a thermocouple gauge was used to

monitor the pressure.

Figure 3.1: Microwave plasma cavity discharge system.

3.3 Sample Preparation

Electrical characteristics of the oxide ¯lms grown on partially strain compensated

Si Ge C were measured using MOS structures. The samples were subjected to1¡x¡y x y

standard cleaning schedule followed by a dip in dilute HF, prior to loading into the

chamber. The chamber base pressure was kept at 1 mTorr. Samples were oxidized

in an oxygen plasma at a pressure of 1.0 Torr with 12 sccm O °ow for 2 mins. Ex-2

ternal biasing and heating of the substrate were not employed in the experiment; theo odischarge itself produced a temperature in the range of 150 -200 C, resulting in self-

ºlimited growth of oxide ¯lms of 80§10 A in all cases. Oxide ¯lms on partially strainedSi Ge C layers were also grown using conventional thermal dry oxidation at 700-1¡x¡y x y

o750 C (100-140 min). Oxide thicknesses, measured using a single wavelength (6328

50

ºA) ellipsometer (Gaertner L-117) and also calculated from the oxide capacitance in

ºaccumulation, were in the range of 75-100 A. Aluminum (»3% Si), typically 1000-

º2000 A thick, was evaporated through a metal mask to form electrodes with diameter

of 0.5 mm. The composition of the samples used for oxidation is listed in Table 3.2.

Table 3.2: Processing conditions for oxide ¯lms on capped- and uncapped-

Si Ge C heterolayers1¡x¡y x y

Sample Si and SiGeC ¯lm Oxidation Temperature Timeoprocess ( C) (min)

STO1 Si thermal 900 140

SGC2TO2 Si Ge C (cap) " 700 "0:69 0:3 0:01

SGC3TO3 Si Ge C (uncap) " " "0:69 0:3 0:01

SGC5TO4 Si Ge C (uncap) " " "0:685 0:3 0:015

SGC5TO5 Si Ge C (uncap) " 750 1000:685 0:3 0:015

SGC2PO1 Si Ge C (cap) plasma 150-200 20:69 0:3 0:01

SGC3PO2 Si Ge C (uncap) " " "0:69 0:3 0:01

SGC4PO3 Si Ge C (cap) " " "0:685 0:3 0:015

SGC5PO4 Si Ge C (uncap) " " "0:685 0:3 0:015

The dc I-V characteristics of MOS capacitors were studied to evaluate oxide re-

sistivity and breakdown strength. Electrical measurements on MOS structures were

made with the experimental setup shown in ¯gure 3.2. The HP-4061A semicon-

ductor component test system consisting of a desktop computer (HP-9836CS) as a

controller, a multi frequency LCR meter (HP-4275A), a pA meter/DC voltage source

(HP-4140B) and a switching subsystem (HP-4083A or HP-16057A) were used for

electrical characterization. The LCR meter was used to measure the capacitance

(resolution 0.01 fF) and conductance of the MOS capacitors at a selectable test fre-

quency from 10 kHz to 10 MHz. The HP-4140B pA meter/DC voltage source, which¡15comprises of a high stability pA meter (highest resolution of 10 A) coupled with

two programmable DC voltage sources, was used to measure the I-V characteristics

and breakdown ¯eld strength of the oxide ¯lms. HP-4145B semiconductor parameter

analyzer was used to perform the characteristics under constant current (voltage)

51

stressing and time-dependent dielectric breakdown (TDDB) experiments.

Figure 3.2: A schematic diagram of the automatic MOS characterization setup.

3.4 Oxide Films on Partially Strained SiGeC

Layers

To become a key process in very large scale integrated fabrication, the quality

of the microwave plasma grown oxide should be comparable to that of conventional

thermal oxide. The properties are strongly related to ¯lm density, defects, porosity

and stoichiometry. The quality of plasma grown oxide was evaluated by performing

various structural characterization. The refractive index of the oxide was measured

with an ellipsometer (Gaertner L-117) incorporating a He-Ne laser light of wavelength

º6328 A. A variation of refractive index from 1.45 to 1.47 was observed in the grown

oxides. The physical properties of the oxides have been characterized by high res-

olution X-ray di®raction analysis and Fourier transform infrared spectroscopy, the

results of which are presented below.

52

3.4.1 High Resolution X-ray Di®raction

The strain state and crystalline quality of partially strain compensated SiGeCo¯lms after plasma and thermal oxidation (750 C, 100 mins) have been investigated.

Figure 3.3 shows high resolution X-ray di®raction spectra of Si (004) re°ection for

Figure 3.3: High resolution X-ray di®raction characteristics for (a) as-grown (sam-

ple: SGC5), (b) plasma grown oxide (sample: SGC5PO4) and (c) thermal (sample:

SGC5TO5) oxides on Si Ge C samples.0:685 0:3 0:015

as-grown and oxidized Si Ge C ¯lms. The occurrence of the alloy peak on0:685 0:3 0:015

the left to the Si (004) peak suggests that the ¯lms are strained compressively, though

partially strain compensated compared to the binary Si Ge . The full-width-half-0:7 0:3

maximum (FWHM) value is high for thermally oxidized ¯lms [¯gure 3.3(c)] compared

to as-grown and plasma oxidized ¯lms [curves 3.3(a) and 3.3(b)]. It is observed from

¯gure 3.3(b) that, no degradation in FWHM and shift of alloy peak have taken place

in plasma oxidized Si Ge C sample. However, strain relaxation is strongly0:685 0:3 0:015

53

evident in thermally oxidized Si Ge C ¯lm [¯gure 3.3(c)] with signi¯cant0:685 0:3 0:015

broadening and shift of the alloy peak. Thus low temperature plasma oxidation is

desirable for growing oxide on ternary alloy layers as thermal oxidation, even at aotemperature as low as 750 C, gives rise to signi¯cant strain relaxation.

3.4.2 Fourier Transform Infrared Spectroscopy

The infrared absorption spectra of the grown oxides have been analyzed to obtain

information regarding the local bonding arrangements of the constituent atoms in

the oxide ¯lms. The measurements were made with an FTIR spectrophotometer in¡1the wave-number (º) range 200-4000 cm . Figure 3.4 shows the FTIR transmis-osion spectra of plasma and thermal (700 C) oxides grown on Si Ge C . The0:685 0:3 0:015

Figure 3.4: Fourier transform infrared spectra for (a) thermal (sample: SGC5TO4)

and (b) plasma grown (sample: SGC5PO4) oxide ¯lms on Si Ge C .0:685 0:3 0:015

absorption due to the bending motion of oxygen atoms was negligible. The domi-

nant features of the FTIR absorption spectra for both the thermal and plasma grown

54

oxides were associated with the stretching mode vibration of Si-O bonds. The ab-¡1 ¡1sorption peak is found at 1072 cm for thermal and at 1078 cm for plasma grown

oxides. The absorption band of the plasma grown oxide is found to be sharper with¡1 ¡1a FWHM of about 70 cm compared to 100 cm for the thermally grown oxides.

This indicates that the quality of plasma grown oxide is better compared to thermally

grown one.

3.5 Electrical and Interfacial Characteristics

Metal-oxide-semiconductor capacitor is the simplest two-terminal device, suitable

for the electrical characterization of the Si/SiO system. Studies on MOS structures2

on SiGeC heterolayers have been carried out to evaluate the electrical and interfacial

properties.

3.5.1 The MOS Capacitor

Figure 3.5: Energy band diagram of a MOS capacitor for p-type Si.

Figure 3.5 shows the energy band diagram of an ideal MOS structure fabricated

on a p-Si substrate. The potential à is assumed to be zero in the bulk of the semicon-

55

ductor and is measured with respect to the intrinsic Fermi level E as shown. At thei

semiconductor surface, Ã=à , where à is the surface potential and represents thes s

total band bending. Depending on the biasing condition, four regions can be distin-

guished: (a) accumulation of holes (Ã <0) with band bending upward, (b) °atbands

condition (Ã =0), (c) depletion of holes (Ã >Ã >0) with band bending downward,s B s

and (d) inversion (Ã >Ã ) with electrons at the surface and band bending downward.s B

oFigure 3.6 shows the capacitance-voltage characteristics of a thermal oxide (900 C;

140 min) grown on Si, representing di®erent regions for both high and low frequency

measurements. In contrast to ideal MOS capacitor, the experimental MOS structure

Figure 3.6: MOS capacitance-voltage (C-V) curves for Si: low frequency and high

frequency C-V for thermal oxide (sample: STO1) and low frequency ideal C-V curve

for comparison.

is not free of charges. Charge trapping, and generation and recombination in inter-

face traps occur at the interface. Due to the presence of trapped charges, the C-V

characteristics di®er in the real case from the ideal one as shown in ¯gure 3.6.

56

3.5.2 Determination of Trap Charges

In an oxide, there are four important types of oxide and interface trap charges

[150]. The location of di®erent types of charges trapped in a MOS structure is shown

in ¯gure 3.7. The ¯rst type, ¯xed oxide charge (Q ), is the charge density remainingf

Figure 3.7: Location of trapped charges at di®erent regions in the MOS structures.

after the interface trap charge is annealed out. Q is generally a positive charge andf

located at the Si/SiO interface. The second type of oxide charge, oxide trapped2

charge (Q ), is usually located either at the metal/SiO interface or at the Si/SiOot 2 2

interface. Q is commonly produced by the injection of hot electrons or holes from anot

avalanche plasma in a high ¯eld region in the Si, injection of carriers by photoemission

or by exposure to ionizing radiation. The third type, mobile ionic charge (Q ), ism

caused by the presence of ionized alkaline metal atoms such as sodium or potassium.

This type of charge is located either at the metal/SiO interface, where it originally2

enters the oxide layer, or at the Si/SiO interface, where it has drifted under an2

applied ¯eld. The fourth type of charge, the interface trapped charge (Q ), is locatedit

at the Si/SiO interface with energy states in the forbidden bandgap. Q can possibly2 it

be produced by excess Si (trivalent Si), excess oxygen, and impurities [150].

57

Oxide Charge Density:

The oxide charge density is calculated from the di®erence between the experi-

mentally determined and the ideal °atband voltages. The °atband voltage (V ) isF B

related to the oxide charge and the work function di®erence between the metal and

semiconductor (Á ). Oxide charges consist of the ¯xed oxide charge (Q ), the oxidems f

trapped charge (Q ) and the mobile ionic charge (Q ). The contribution of Q isot m m

relatively small, as indicated by the absence of hysteresis e®ect in the experimental

C-V characteristics and the low level of sodium contamination in the oxide during

processing. The oxide trapped charge (Q ) is generally assumed to be negligiblyot

small at the low applied ¯eld used in C-V measurements. For simplicity, the presence

of Q is assumed to be the only contributing factor for the °atband voltage shifts.f

The Q is then calculated using the relation:f

Q =q = C =(A:q)(Á ¡ Á ¡ V ) (3.1)f ox ms F F B

where C is the oxide capacitance in accumulation, Á is the Fermi potential of theox F

heterolayers, V is the °atband potential and A is the gate area of the capacitor.F B

The °atband voltage is determined using the °atband capacitance method. Silicon

space charge capacitance (C ) at the °atband condition is given by the relation:F BS

C = ² =L (3.2)F BS Si D

where ² is the permittivity of Si and L is the Debye length, expressed asSi D

2 1=2L = (² kT=q p ) (3.3)D Si o

where p is the equilibrium hole density in the semiconductor. The correspondingo

total high frequency °atband capacitance is given by

C = C C =(C + C ) (3.4)F B F BS ox F BS ox

The V is then determined as the voltage at which the measured high-frequencyF B

capacitance is equal to the °atband capacitance.

Interface Trap Charge Density:

Interface trap density (D ) is determined from the combination of a single fre-it

quency capacitance-voltage and conductance-voltage (G-V) characteristics using Hill's

58

method [151]. The mathematical expression for calculating interface state density is

given by2 2D = (2=q:A)(G =w)=[(G =wC ) + (1¡ C =C ) ] (3.5)it max max ox m ox

where G is the maximum conductance in G-V plot with its corresponding capac-max

itance (C ), C is the oxide capacitance, ! is the angular frequency.m ox

3.5.3 Oxide Charge and Interface State Density

Figure 3.8 shows the high frequency (1 MHz) C-V characteristics of both thermal

Figure 3.8: C-V characteristics of thermal and plasma grown oxides on Si Ge C0:69 0:3 0:01

¯lms. Plasma oxide on ternary (SGC2PO1 and SGC3PO2) alloys with and without

(inset) Si-cap. Thermal oxide on Si Ge C (SGC2TO2 and SGC3TO3) ¯lms0:69 0:3 0:01

with and without (inset) Si-cap.

and plasma grown oxides on Si Ge C heterolayers with and without (inset)0:69 0:3 0:01

Si-cap. All the MOS capacitors exhibit well behaved C-V characteristics with dis-

tinct accumulation and depletion regions. The plateau in high frequency C-V curves

59

for SGC2TO2 and SGC2PO1 samples are caused by the accumulation of holes in

the Si/SiGeC interface due to the type-I valence band o®set. The hole con¯nement is

observed only for the capped-SiGeC ¯lms due to the formation of an well in SiGeC lay-

ers. The plateau in C-V characteristics is absent in uncapped SiGeC ¯lms (SGC3TO3

and SGC3PO2) as the holes are accumulated at the SiO /SiGeC interface. The °at-2

band voltages (V ) for SGC2PO1, SGC2TO2, SGC3PO2 and SGC3TO3 samplesF B

are found to be 0.1 V, 0.3 V, 0.74 V and 0.54 V, respectively, due to the presence of

negative oxide charges in ¯lms.

Figure 3.9 shows the C-V and G-V characteristics of thermally grown oxides on

Si Ge C layers without Si-cap. The peak of the G-V characteristics has0:69 0:3 0:01

Figure 3.9: Typical C-V and G-V characteristics for thermally grown uncapped

Si Ge C sample (SGC3TO3).0:69 0:3 0:01

been taken to calculate the interface trap density at the mid-gap energy using Hill's

method [151]. Fixed oxide charge density (Q /q) and interface trap density for allf

the oxide samples are shown in Table 3.3. It is found that D values are lower forit

othermally (700 C) grown oxides compared to plasma grown oxides. Bera et al. [37]12 ¡2 12 ¡2reported values of Q /q (-2.2£10 cm ) and D (1.6£10 cm /eV) for rapidf it

60

Table 3.3: Interfacial properties of thermal and microwave plasma grown oxides on

Si Ge C heterolayers.1¡x¡y x y

¡2 ¡2 ¡1Sample Q /q (cm ) D (cm eV )f it

11 11SGC2TO2 -1.3£10 4.4£1011 11SGC3TO3 -2.7£10 5.4£1011 11SGC2PO1 -1.0£10 5£1011 11SGC3PO2 -3.0£10 8.1£10

othermally oxidized (1000 C) Si Ge C ¯lms. The values are higher than0:8738 0:113 0:0132

Figure 3.10: ¢D versus °uence on constant current stressing oxides on partiallyit

strained SiGeC ¯lms. SGC2PO1: plasma grown oxide on capped-SiGeC, SGC2TO2:

thermal oxide on capped-SiGeC, SGC3PO2: plasma grown oxide on uncapped-SiGeC

and SGC3TO3: thermal oxide on uncapped-SiGeC.

those obtained in our study using microwave plasma . It is also noted that the Q /qf

and D values increase in uncapped ¯lms and with increasing C concentration init

ternary alloy layers. The higher Q /q and D values in plasma grown oxide comparedf it

61

to those of thermal oxide are attributed to unavoidable plasma induced damage in

the former.

Figure 3.10 shows the change in interface state density as a function of charge2injection (°uence). The stress current density was -50 mA/cm . The initial Dit

value is found to be lower for thermal oxides in comparison to plasma oxides. The

generation of D is related to the density of strained bonds as well as the quality of theit

semiconductor/oxide interface. A signi¯cant improvement in resistance to interface

state generation (¢D ) is observed in thermal oxide MOS capacitors. A lower valueit

of ¢D is also observed for capped-SiGeC ¯lms as compared to uncapped ones.it

3.5.4 I-V Characteristics

Figure 3.11: Current density (J) vs. electric ¯eld (E) characteristics of stressed and

unstressed thermal and plasma grown oxides on partially strain compensated capped-oSiGeC ¯lms. SGC2TO2: thermal oxide (700 C 140 min), SGC2PO1: plasma oxide

(1%C) and SGC4PO3: plasma oxide (1.5%C).

62

2The e®ect of constant current (J =-50 mA/cm ) stressing on tunneling charac-0

teristics of thermal and plasma grown oxide on SiGeC ¯lms is shown in ¯gure 3.11.

The sample (SGC4PO3) containing higher C mole fraction exhibits a higher low-¯eld

leakage current compared to SGC2TO2 and SGC2PO1 sample. A step-wise increase

of current is observed at various breakdown regions in the J-E characteristics of un-

stressed samples. The ¯rst step is assigned as the quasi-breakdown region similar

to that observed by Lee et al. [152]. The quasi-breakdown ¯eld is found to be 7.5

MV/cm and 4.5 MV/cm for samples SGC2PO1 and SGC4PO3 [149], respectively.

Both the quasi and hard-breakdown ¯elds are found to be higher in oxides on capped

SiGeC ¯lms with lower carbon concentration. A similar behavior is observed in stress

induced leakage current characteristics of the samples. The mechanism of leakage

current in stressed samples may be attributed to enhanced generation of localized

defects or weak spots, localized negative charges, and C-induced trap states near the

injecting interface. It was proposed by Fukuda et al. [153] that the trap-assisted di-

rect tunneling e®ectively reduces the tunneling barrier height for the stressed sample

as compared to the unstressed one.

3.5.5 Charge Trapping Behavior

Electron and hole trapping in oxides have been studied to investigate their role

in the degradation of device characteristics which has now become a major reliability

concern for ultrathin dielectrics. The charge trapping characteristics of thermal and

plasma oxides have been investigated for MOS capacitors fabricated on capped- and

uncapped-SiGeC ¯lms. Figure 3.12 shows the gate voltage shift for both the thermally

and plasma grown oxides vs. time under constant current stressing (-20 ¹A and -40

¹A) with a negative gate bias. A positive gate voltage shift indicates electron trapping

while a negative gate voltage shift implies hole trapping characteristics [52, 154]. It

is observed that thermal and plasma grown oxides show electron and hole trapping,

respectively. Thermal oxides exhibit lower charge trapping compared to plasma grown

oxides. The improved charge trapping behavior in thermal oxides may be related to

the reduction of number of weaks spots by ¯lling or misaligning of micropores. On

the other hand, energetic ions/electrons present in the plasma may be responsible for

the creation of higher number of trap centers in plasma grown oxide ¯lms. Reduced

charge trapping is observed in oxides on capped-SiGeC ¯lms compared to uncapped

63

ones due to the better quality of semiconductor/oxide interface in the former. It is

also observed that the higher C-containing oxide ¯lms (SGC4PO3) show a higher

trapping density, compared to low C-containing oxides [149]. This may be due to the

presence of localized states/charge centers in high C-containing ¯lm. Furthermore,

the presence of C-rich clusters within the Si matrix upon oxidation of the 1.5% C

sample cannot be eliminated resulting in a higher trap density in high C containing

¯lms.

Figure 3.12: Gate voltage shift vs. stress time of oxides on partially strain com-

pensated Si Ge C ¯lms under constant current stress of -20 ¹A and -40 ¹A.1¡x¡y x y

oSGC2TO2: thermal oxide (700 C 140 min, 1%C) with cap, SGC2PO1: plasma oxide

(1%C) with cap, SGC3PO2: plasma oxide (1%C) without cap, SGC3TO3: thermalooxide (700 C 140 min, 1%C) without cap, and SGC4PO3: plasma oxide (1.5%C) with

cap.

64

3.5.6 Breakdown Characteristics

Charge-to-breakdown (Q ) is an important parameter for the evaluation of oxideBD

reliability. Fowler-Nordheim (F-N) constant current stressing is a commonly used

technique to determine the oxide reliability. In this technique, an electron current is

injected by tunneling through the oxide and the applied gate voltage (to maintain a

constant current density) is measured. The oxide breakdown is determined from the

sudden drop in the applied voltage. For each sample, a constant gate current stress of

Figure 3.13: Charge-to-breakdown characteristics of thermal and plasma grown oxidesoon Si Ge C ¯lms. SGC2TO2: thermal oxide (700 C 140 min, 1%C) with cap,1¡x¡y x y

SGC2PO1: plasma oxide (1%C) with cap, SGC3PO2: plasma oxide (1%C) withoutocap, SGC3TO3: thermal oxide (700 C 140 min, 1%C) without cap, and SGC4PO3:

plasma oxide (1.5%C) with cap.

2-100 mA/cm was applied as shown in ¯gure 3.13 and time-to-breakdown (charge-to-

breakdown) was recorded by HP-4145B semiconductor parameter analyzer. A large

drop in the applied voltage at the breakdown point can easily be detected. This

65

corresponds to the formation of a highly conductive path in the MOS structure. The

small discontinuous drop of the applied voltage corresponds to the oxide breakdown

in which the oxide defect generation reaches a critical condition at the weakest spot of

the capacitor and soft breakdown occurs [155]. The Q values are found to be 52, 38,BD

244, 27 and 18 C/cm for SGC2TO2, SGC3TO3, SGC2PO1, SGC3PO2 and SGC4PO3

samples, respectively. The improvement in Q for thermal oxide ¯lms (SGC2TO2BD

and SGC3TO3) are more pronounced, compared to microwave plasma grown oxide

¯lms (SGC2PO1 and SGC3PO2) due to reduced micropore density in the former. It

is also evident that Q is improved for oxide grown using both thermal and plasmaBD

process on capped samples. Q degrades drastically for high C-containing ¯lmsBD

(SGC4PO3) even in the presence of a Si-cap layer. Q values of oxides on SiGeCBD

2are comparable to the values (30 C/cm ) reported by Tomita et al. [156] with an

oxide thickness of 5.8 nm grown by thermal oxidation on Si substrate. Bera et al.¡4 2[37] reported lower charge-to-breakdown (Q ¼ 3£10 C/cm ) for 11.3% Ge andBD

1.32% C content ¯lms compared to our Q values.BD

3.6 Summary

Growth of oxides on partially strain compensated SiGeC ¯lms has been demon-ostrated at low temperatures (<200 C) using microwave plasma oxidation. While

othermal oxidation even at a temperature of 750 C causes partial strain relaxation

in the ternary layer, plasma technique has been found to be useful to preserve the

pseudomorphic nature of the ¯lm. Electrical, interfacial and charge trapping prop-oerties of plasma and thermally (700 C) grown oxides have been studied through the

characterization of fabricated MOS capacitors.

Thermally grown oxides exhibit improved interfacial, charge trapping and break-

down properties as compared to the plasma oxide. This may be due to a combination

of lower density and plasma induced damage that are unavoidable in a plasma oxide.

In both the cases, the presence of a thin Si-cap layer is found to be bene¯cial to obtain

improved electrical properties with enhanced immunity to stress induced degradation

of oxides. This is attributed to the formation of high quality SiO /cap-Si interface2

as compared to mixed oxide/SiGeC interface. Electrical and interfacial properties of

the oxide are found to be degraded on increase of C content from 1% to 1.5% in the

ternary ¯lm.

66

Chapter 4

Oxynitride Films on SiGe/SiGeC

Layers

Over the last two decades, much work has been done to improve the dielectric

integrity of conventional thermal oxides in the form of chemical modi¯cations of

SiO bulk and Si/SiO interface by incorporating a small amount of nitrogen or2 2

°uorine within the frame work of MOS processing. To have a better understanding

of the mechanism, one needs to know the structure and chemistry of the Si/SiO2

system [126]. The interfacial and the transition region of Si/SiO comprise of a non-2

stoichiometric monolayer (Si O , SiO, Si O) due to incomplete oxidation followed by2 3 2

a layer of strained SiO [126]. Therefore the strained interface is prone to damage by2

high ¯eld stress and radiation and thereby, cause the device reliability problems

Chemical modi¯cation of the Si/SiO interface can reduce this strain. Considering2

9 ¡2high intrinsic tensile stress of Si N (9-10£10 dynes cm ) on Si [157], incorporation3 4

9 ¡2of nitrogen in SiO may o®set the compressive stress (2-4£10 dynes cm ) which2

is present at the interface prior to nitridation [158]. This strain compensation is

believed to be due to the formation of Si N O along with SiO and Si N in the Si-2 2 2 3 4

N-O system [159]. An alternative model proposed by Ruggles et al. [160] states that

nitrogen which is co-ordinated to three atoms rather than two as in the case of O ,2

helps to densify the interfacial region and relax the strain.

In conventional Si processing technology, a novel process referred to as the `oxidized-

nitrided silicon (ONS)', was developed by Hao et al. [161] to produce reliable ultra-

ºthin tunnel dielectrics (∙50 A). These dielectrics exhibited reduced charge trappingand improved interface state generation characteristics on constant current (voltage)

67

stressing. The stress induced leakage current (SILC) was also found to be suppressed

by employing the ONS dielectrics. In addition, precise thickness control was easily

achieved by the ONS process even down to the ultrathin regime resulting in reliable

tunnel dielectrics suitable for memory applications.

It was reported in early 1980's that furnace annealing of SiO in NH resulted in2 3

an improvement in barrier properties against impurity penetration during subsequent

processing steps [162]. Improved radiation hardness [163] and suppressed interface

state generation under hot carrier stressing were also demonstrated [164]. However,

these dielectrics showed some drawbacks such as increase in ¯xed oxide charge and

interface state density [165], and increase in oxide electron trap concentration [164]. A

subsequent reoxidation step was suggested to reduce these undesirable e®ects of NH3

nitridation [166]. To avoid an increase in oxide thickness during reoxidation step,

an inert gas anneal of NH nitrided SiO was also suggested in order to achieve a3 2

high quality dielectric [167]. On the other hand, growth of oxynitrides using NH has3

been shown to incorporate su±cient N at the Si/SiO interface along with hydrogen2

[168, 169]. However, hydrogen-related species incorporated in the resulting dielectric

¯lms degrade the reliability of the oxynitrides. Reoxidation of these ¯lms is required

to reduce the hydrogen concentration at the interface to improve the reliability.

To avoid the problems in NH processing, a single-step process by direct oxidation3

in N O ambient has been proposed due to the absence of hydrogen in the processing2

ambient [170]. However, the levels of nitrogen incorporated at the Si/SiO interface2

as a result of N O oxidation are found to be very low and often not adequate to2

form an e®ective di®usion barrier [171]. In order to achieve higher N concentration

in the dielectrics by N O oxidation, a higher thermal budget is inevitable. On the2

other hand, reactions of NO with Si are more favorable [172]. However, the kinetics

of N O dissociation show that the dissociation pathway to NO is thermodynamically2

less favorable, since the bond dissociation energy of the N-NO bond (4.9 eV) is much

higher than that of the N -O bond (1.67 eV) [173]. Hence, it appears that the direct2

reaction of NO with silicon should result in higher N concentrations in the dielectric

¯lm compared to those from the reaction of N O with silicon at the same temperature2

[174].

As discussed in Chapter 1, a double wall `N' barrier is bene¯cial for ultrathin

dielectric with reduced B-penetration and improved hot carrier immunity. Gusev et

al. [175] studied the nitrogen incorporation in NO, NO/O and NO/O /NO treated2 2

o¯lms using thermal oxidation (»900 C) on Si. The depth pro¯le of nitrogen was

68

obtained using high-resolution (¢E/E»0.1%) medium energy ion scattering (MEIS).From the results presented in ¯gure 4.1, it is observed that the NO/O /NO treated2

sample has nitrogen located at both the top (SiO /polysilicon) and bottom (Si/SiO )2 2

interfaces of the oxynitride ¯lm.

oFigure 4.1: Nitrogen depth pro¯les for Si (100) samples processed in: (a) NO (800 C,o o o5 min), (b) NO (800 C, 5 min) followed by O (900 C, 60 min), and (c) NO (800 C,2

o o5 min) followed by O (900 C, 52 min) with ¯nal annealing in NO (900 C, 5 min).2

Arrows show the position of the interface for each oxynitride ¯lm. Figure is after

Gusev et al., J. Appl. Phys., vol. 84, 1998, p. 2980.

For the incorporation of N in oxides, conventional thermal or rapid thermal ni-otridation in the temperature range of 800-1000 C are used. However, strained SiGe

oand SiGeC ¯lms are grown in the temperature range 500-700 C and cannot be pro-

cessed beyond this temperature due to the problem of strain relaxation. Therefore,

there is a need of low temperature process for the growth of nitrided-oxide/oxynitride

¯lms on pseudomorphic group-IV alloy layers. In this chapter, we present the results

on the growth and electrical properties of stacked nitrided oxide/oxynitride ¯lms

69

(hereafter, referred to as `oxynitride' only) on SiGe and SiGeC heterolayers at a lowotemperature (< 200 C) using a combination of H -, O -, NO-, and NH -plasma. The2 2 3

electrical properties of the ¯lms have been studied using the fabricated metal-oxide-

semiconductor (MOS) structure.

4.1 Oxynitride Films on Strained SiGe Layers

Oxynitride ¯lms were grown in a microwave (700 W, 2.45 GHz) plasma system

that has been described in Chapter 3. Processing conditions for three di®erent types

of oxide and oxynitride ¯lms are given in Table 4.1. During growth process, the system¡3was ¯rst evacuated to 10 Torr followed by the introduction of O (12 sccm) and NO2

(15 sccm) gases into the discharge chamber at a pressure of 1.0 Torr. The substrateo otemperature due to the plasma discharge was about 150 -200 C. Thicknesses of the

ºoxide and oxynitride ¯lms were in the range of 75-90 A as determined using a single

ºwavelength (6328 A) ellipsometer (Gaertner L-117).

Table 4.1: Processing conditions for growth of oxide and oxynitride ¯lms on

Si Ge layer0:74 0:26

Samples NO-plasma O -plasma NO-plasma2

SG2O - 2 min -

SG2N 2 min - -

SG2NON 1 min 1 min 1 min

Since a single-step process using NO provides a `singe-wall' nitrogen distribution

either at the poly-Si/SiO or SiO /Si interface, a three-step (NO/O /NO) process2 2 2

was chosen so that N incorporation can take place at both sides of the dielectric ¯lm.

XPS study has been used to probe the oxide interface. Oxide and oxynitride ¯lms

have been characterized by measurements of interface state density, °atband voltage,

border trap density and soft breakdown properties under constant current (voltage)

stressing.

70

4.1.1 X-ray Photoelectron Spectroscopy

Surfaces exposed to oxygen and nitric oxide plasma were analyzed by X-ray photo-

electron spectroscopy to investigate the chemical bonding of the ¯lms. This technique

is particularly attractive for deducing local atomic structure due to the sensitivity of

the spectra to the chemical environment. In XPS, the shift in the binding energy

of the core level electron due to change in the bonding was monitored. XPS (VG

Scienti¯c ESCALABMK-II spectrometer equipped with a concentric hemispherical

analyzer) with AlK radiation was used to con¯rm the incorporation of nitrogen in®

the dielectric ¯lms.

Figure 4.2: Broad energy XPS spectra of plasma grown dielectric on strained+Si Ge layers: (a) O -plasma oxide (SG2O), (b) 1 min Ar ion etched O -plasma0:74 0:26 2 2

+oxide (SG2O) and (c) 1 min Ar ion etched NO-plasma oxynitride (SG2N)

Figure 4.2 shows the broad energy XPS spectra of the O and NO-plasma treated2

oxide grown on strained Si Ge layers. High resolution recording of spectrum,0:74 0:26

with a pcss energy of 25 meV, shows the XPS peak positions of Si 2p, Ge 3d, Si+2s, C 1s and O 1s for O -plasma grown oxide on SiGe. After 1 min Ar etching,2

71

disappearance of C 1s peak [see ¯gure 4.2(b)] is observed. High resolution XPS

spectrum of Si 2p shows a single peak at the surface, which is attributed to the

formation of stoichiometric SiO . The observed binding energy of Si 2p electrons2

is in between silicon nitride and silicon dioxide, indicating the formation of silicon+oxynitride ¯lms [176]. Figure 4.2(c) shows the XPS peak (1 min Ar ion etched) of

N 1s (398.4 eV) after 2 min exposure to microwave NO plasma. The incorporation of

nitrogen in the oxide layer is achieved using low temperature NO plasma oxidation

[177].

4.1.2 Interface Properties

High frequency C-V characteristics of SG2O, SG2N and SG2NONMOS capacitors

before and after stressing are shown in ¯gure 4.3. It is observed that after stressing

Figure 4.3: High frequency (1 MHz) C-V characteristics of MOS capacitors on strained

Si Ge (SG2O: O -plasma; SG2N: NO-plasma; SG2NON: NO/O /NO plasma).0:74 0:26 2 2

2(°uence of 150.0 mC/cm ), C-V curve for samples SG2O and SG2N shifts towards

positive voltage while that for SG2NON shifts towards negative voltage due to the

charge trapping characteristics of grown ¯lms. It indicates that O - and NO-plasma2

72

grown ¯lms show the electron trapping where as NO/O /NO-plasma grown stacked2

dielectric ¯lm exhibits the hole trapping behavior. C-V and G-V characteristics of 3-

step stacked dielectric (SG2NON) at di®erent frequencies are presented in ¯gure 4.4.

In accumulation region, the C-V characteristics show a little frequency dispersion

Figure 4.4: C-V and G-V characteristics of NO/O /NO plasma treated ¯lm (sample:2

SG2NON).

with a higher capacitance value at 100 kHz. The G-V characteristics show a frequency

dispersion in the accumulation region where a higher conductance is also observed

at 400 kHz. The dielectric loss, as seen from G-V curves, for sample SG2NON is

comparable to oxynitride ¯lms grown on Si [178]. Fixed oxide charge density (Q /q)f

11 ¡2 11 ¡2for SG2O, SG2N and SG2NON ¯lms are found to be 1.5£10 cm , 3.7£10 cm11 ¡2and 2.6£10 cm , respectively. The conductance peaks of the samples have been

used to calculate the interface state density (D ) near the midgap energy using Hill'sit

11method [151]. D values for SG2O, SG2N and SG2NON are found to be 4.7£10it

¡2 ¡1 12 ¡2 ¡1 11 ¡2 ¡1cm eV , 1.0£10 cm eV and 6.9£10 cm eV , respectively. The increase

in D value in SG2N and SG2NON (compared to SG2O, O -plasma grown oxide) isit 2

due to N incorporation in the oxide [52]. However, the use of a three-step NO/O /NO2

73

process is bene¯cial in reducing both the Q /q and D values compared to thosef it

obtained with a single-step NO-plasma.

4.1.3 Charge Trapping Characteristics

Charge trapping behavior of oxide and oxynitride ¯lms on Si Ge under a0:74 0:26

2constant current of -0.5 mA/cm (gate injection) stressing has been studied. Figure

4.5 shows the °atband voltage shift (¢V ) as a function of °uence. ¢V is sensitiveF B F B

to the combined e®ect of charge trapping at the interface and in the bulk, and mainly

Figure 4.5: j ¢V j as a function of °uence for plasma grown oxide and oxynitrideF B

¯lms (SG2O: O -plasma; SG2N: NO-plasma and SG2NON: NO/O /NO-plasma).2 2

re°ects the presence of charge near the SiGe/oxide interface. It is observed that O2

and NO-plasma treated samples exhibit electron trapping while NO/O /NO grown2

oxynitrides show the presence of hole trapping [52]. However, sample SG2O shows

a high value of ¢V (compared to SG2N and SG2NON) indicating a high stressF B

induced electron trap generation. NO/O /NO and NO grown dielectrics show a low2

charge trapping. This may be attributed to the presence of fewer broken Si-O bonds

resulting from a high degree of strain relief owing to N incorporation in SiO [179].2

74

4.1.4 Border Trap Density

According to the Deal committee's classi¯cation of oxide charges [180], the inter-

face trapped charge (Q ) which resides at the Si-SiO interface is in rapid electricalit 2

communication with the Si substrate, where as, the oxide trapped charge (Q ) residesot

in the oxide and does not communicate with the Si substrate. However, the fact that

the oxide traps close to the interface can communicate with the Si substrate calls for

the introduction of border traps (Q ) [181]. Figure 4.6 shows a hysteresis in the highbt

frequency (1 MHz) C-V (HFCV) characteristics of O -plasma grown (SG2O) oxides2

before and after high-¯eld stressing. The gate voltage is swept from inversion to

Figure 4.6: Typical border trap generation in plasma grown oxide on strained

Si Ge layers (SG2O) after constant current stressing . As shown by the arrows,0:74 0:26

the sense of hysteresis is counterclockwise.

accumulation to get forward HFCV and back to inversion to get reverse HFCV. The

hysteresis occurs because the gate bias at which electrons ¯ll the traps is di®erent

from the point at which the electrons leave the traps and/or due to the di®erence

between the capture and emission rates of the border traps. The border traps are

negatively charged during the forward sweep [181] and are neutral during the reverse

75

sweep. The reverse HFCV curve thus shifts to the left of the gate voltage axis rela-

tive to the forward HFCV curve. Therefore, the amount of hysteresis is a measure of

border trap density. The fact that electrons captured by border traps can electrically

compensate the trapped holes, makes it di±cult to obtain densities of hole traps,

border traps, and interface traps using any single electrical measurement [182].

The generation of border traps depends on the quality of the oxynitride/Si Ge0:74 0:26

interface. The border trap density is extracted from the hysteresis width at the

midgap (¢V ) capacitance, assuming that the interface states do not contribute tomg

the charge when the Fermi level is at the midgap. Figure 4.7 shows the border trap

Figure 4.7: Border trap density in plasma grown oxide/oxynitride ¯lms on strained

Si Ge (SG2O: O -plasma; SG2N: NO-plasma; SG2NON: NO/O /NO plasma).0:74 0:26 2 2

density for SG2O, SG2N and SG2NON ¯lms as a function of injected electron °uence.

Generated border trap density is found to be highest in plasma oxide (SG2O) ¯lm

compared to oxynitride ¯lms and lowest in stacked (SG2NON) oxynitride. Border

traps are attributed to the physical stress present at the substrate/dielectric interface.

SG2O ¯lm grown using O -plasma has high interface stress due to the interfacial2

oxidation. On the other hand, SG2N and SG2NON oxynitride ¯lms possess lower

stress due to reduced interfacial oxidation in the presence of nitrogen. It is presumed

76

that the energetic electrons release their energy at the collecting interface leading to

the breaking of bonds [183]. It is easier to break the strained Si-O bonds resulting

in higher trap generation in O -plasma ¯lm due to high-¯eld stressing. SG2N and2

SG2NON dielectric ¯lms, on the other hand, present robust interfaces due to the

incorporation of nitrogen at the interface [181].

4.1.5 Breakdown Characteristics

The reliability of oxide/oxynitride ¯lms was studied with time-dependent dielectric

soft breakdown (TDDSB) measurements. As a large direct tunnel current can be

injected into the dielectric, the stress-induced leakage current (SILC) at low electric

Figure 4.8: Evolution of the gate current during constant voltage stress of -8.0V.

Time-dependent dielectric soft breakdown properties for all ¯lms (SG2O: O -plasma;2

SG2N: NO-plasma; SG2NON: NO/O /NO-plasma).2

¯elds is observed for all the ¯lms. The evolution of the current through the oxide

and oxynitride ¯lms for a constant -8.0 V stressing is shown in ¯gure 4.8 for SG2O,

77

SG2N and SG2NON samples. The current behavior is seen to be consistent with a

trap-assisted tunneling mechanism [184]. The ¯rst stage consists of a small increase

in current and after that, the current suddenly becomes noisy and increases in steps.

The sudden increase of current in the second stage is attributed to quasi-breakdown

phenomena or soft breakdown [185]. The time to soft breakdown is observed to be

250 s, 570 s and 700 s for the samples SG2O, SG2N and SG2NON, respectively.

The TDDSB and hard breakdown (HBD) of SG2NON and SG2N samples are high

compared to SG2O indicating the role of `N' in enhancing the breakdown strength of

the oxide ¯lms.

Figure 4.9: Evolution of the gate voltage during constant current stress of -502mA/cm . Charge-to-soft breakdown properties have been studied for all ¯lms.

A constant tunnel current stressing is a standard method to determine the oxide

reliability. In this method, an electron current is injected by tunneling through the

oxide and the applied voltage over the MOS capacitor, to maintain a constant current

density, is measured. The oxide breakdown is determined by the large drop in the

applied voltage that suddenly occurs. The soft breakdown (SBD) properties of ultra-

78

thin gate oxide and oxynitride ¯lms are investigated using a constant current ( J0

2= -50 mA/cm ) stressing and the results are presented in ¯gure 4.9. The SBD

(also called quasi-breakdown) corresponds to a large increase of the stress-induced

leakage current and to the occurrence of °uctuations in the gate voltage (current) for

a constant current (voltage) stressing [186, 187]. The e®ective area of the conductive

SBD-path is given by [188] " #q tox

A = (4.1)² ¢Vox

where t is the oxide thickness. The value of conductive SBD-path has been reportedox

¡12 ¡13 2to be in the range of 10 -10 cm by several authors [188]. The above parameter

calculated from ¯gure 4.9 in dielectric ¯lms is found to be in the range of 3.0 -¡13 24.0£10 cm , indicating the occurrence of SBD in plasma grown ¯lms. Nearly

constant gate voltage up to 255 s, 740 s and 1005 s for SG2O, SG2N and SG2NON

¯lms, respectively, indicates an improved hot carrier immunity for N-incorporated

oxides with three-step stacked dielectric exhibiting their superior performance. The

relatively small voltage drop in each sample, due to SBD indicates good reliability

characteristics for MOS devices with ultrathin gate dielectrics on strained Si Ge .0:74 0:26

2The SBD occurred with charge-to-soft breakdown values Q = 12.5 C/cm , 37.0SBD

2 2C/cm and 50.0 C/cm for SG2O, SG2N and SG2NON, respectively. The above SBD

values are comparable with those reported in the literature by several authors viz.,2 273.4 C/cm [189] with 4.2 nm gate oxide, 12.5 C/cm [188] with 4.5 nm oxide, and215.0 C/cm [156] with oxide thickness 5.8 nm on Si substrate.

4.2 Oxynitride Films on Partially Strained SiGeC

Layers

Oxynitride ¯lms grown with di®erent process sequences on Si Ge C layers1¡x¡y x y

using microwave plasma at a low temperature are given in Table 4.2. The thick-

ness of the oxynitride ¯lms was determined both by ellipsometry and from the C-

ºV measurements and were found to be 85§10 A in all samples. FTIR has been

used to detect the nitrogen incorporation in the dielectric. Several properties of

di®erent oxynitride ¯lms have been investigated using electrical measurements such

as capacitance-voltage, current-voltage, trapped charge density and centroids under

79

Table 4.2: Processing conditions and sequences for oxynitride ¯lms on SiGeC layers

Samples Composition H NO O NH NO O2 2 3 2

SGC1HN Si Ge C 1 min 1 min - - - -0:795 0:2 0:005

SGC1NHN " - - - 1 min 1 min -

SGC1ONHN " - - 30 s 30 s 1 min -

SGC3ONO Si Ge C - - 30 s - 30 s 1 min0:69 0:3 0:01

SGC3NON " - 30 s 30 s - 1 min -

SGC3ONHN " - - 30 s 30 s 1 min -

SGC5N Si Ge C - 2 min - - - -0:685 0:3 0:015

static and dynamic stressing, and breakdown characteristics.

4.2.1 Fourier Transform Infrared Spectroscopy

Figure 4.10: FTIR spectra of NO-plasma treated oxynitride ¯lm grown on partially

strained Si Ge C sample.0:685 0:3 0:015

80

Fourier transform infrared spectra of NO-plasma grown oxynitride ¯lms on par-

tially strained Si Ge C heterolayers is shown in ¯gure 4.10. From the spectra,0:685 0:3 0:015

¡1a strong absorption peak at 1083.3 cm for Si-O bonds is observed. The absence¡1of any dominant signal at 800 cm shows that the absence of Si-C precipitation did

not occur in plasma processed dielectric. FTIR spectra has been deconvoluted by

Gaussian ¯tting to two peaks corresponding to overlapping bonds, which are shown¡1in the inset of ¯gure 4.10. The peak of absorption band at 1039.3 cm is attributed

to the formation of O-Si-N bonds, indicating the oxynitride formation but with low

nitrogen incorporation [190].

4.2.2 Fixed Charge Density

Electrical and charge trapping properties of oxynitride ¯lms are strongly a®ected

by the fraction of `O' and `N' atoms, `N' pro¯le in the dielectric and composition of

the plasma precursors. To study the above, high frequency (1 MHz) C-V character-

Figure 4.11: 1 MHz C-V characteristics of MOS capacitors on partially strained

Si Ge C , before and after stressing. SGC3ONO: O /NO/O plasma;0:69 0:3 0:01 2 2

SGC3NON: NO/O /NO plasma; SGC3ONHN: O /NH /NO plasma.2 2 3

81

istics of MOS capacitors using O /NO/O -, NO/O /NO- and O /NH /NO-plasma2 2 2 2 3

grown oxynitride ¯lms on SiGeC have been measured before and after stressing. The

results are presented in ¯gure 4.11. Flatband voltages (V ) of the oxynitride ¯lmsF B

(before stressing) are found to be 0.65 V, 0.45 V, and -1.12 V for samples SGC3ONO,

SGC3NON and SGC3ONHN, respectively. After ¯rst step oxidation, V for O - andF B 2

NO-plasma grown ¯lms are found to be 0.74 V and 0.62 V, respectively. Therefore,

°atband voltage shift (¢V ) are about -0.09 V, -0.17 V and -1.86 V for O /NO/O -,F B 2 2

NO/O /NO- and O /NH /NO grown ¯lms, respectively. The magnitude of ¢V2 2 3 F B

towards the negative voltage axis for stacked insulators depends on the amount of

nitrogen incorporation at the Si/SiO interface [191]2

2It is noted that after stressing (°uence of 7.5 C/cm ), C-V curve for sample

SGC3ONHN shifts towards the negative voltage axis while that for SGC3ONO and

SGC3NON shifts towards the positive voltage. The positive (samples: SGC3ONO and

SGC3NON) and negative (Sample: SGC3ONHN) voltage shifts indicate electron and

hole trapping [192] in the oxynitride ¯lms, respectively. Trapped charges after stress-

ing is found to be higher in SGC3ONO ¯lm compared to SGC3NON and SGC3ONHN

oxynitrides. It is also noted that reoxidation of NO treated oxide (SGC3ONO) sam-

ple reduces the nitrogen incorporation in the gate oxide resulting in a decrease in the

robustness of the dielectric [193]. A double `N'-wall oxynitride SGC3NON sample,

where strained bonds of Si-O are replaced e±ciently by Si-N bonds, results in the

reduction of negative charge density [52].

4.2.3 I-V Characteristics

Gate current vs. electric ¯eld (I-E) characteristics of SGC3ONO, SGC3NON and

SGC3ONHN samples have been measured and the results are shown in ¯gure 4.12.

A step-wise increase of current is generally observed at various breakdown region

in the I-E characteristics of unstressed samples. The breakdown ¯elds are found to

be 6.3 MV/cm, 10.9 MV/cm and 12.0 MV/cm for samples SGC3ONO, SGC3NON

and SGC3ONHN, respectively. Though the sample SGC3ONHN has the highest

breakdown ¯eld, it exhibits a high low-¯eld leakage current compared to SGC3ONO

and SGC3NON samples. The I-E behavior of the oxynitride samples can be explained

as follows. It is reported [194] that there are ¯ve well de¯ned trap levels located at

2.5, 2.76, 3.03, 3.36, and 3.76 eV below the nitride conduction band edge. Since

the band gap of nitride is about 5.1 eV, the lowest trap level is about 1.4 eV above

82

the nitride valence band edge. As it is known that oxynitride ¯lms follow Poole-

Frenkel type conduction mechanism, holes can °ow through the nitrogen containing

¯lms more easily than the electron which faces large barriers. As a result of the low

barrier for holes, total current is larger for the nitrogen treated ¯lms when the gate

is negatively biased. Current at a low electric ¯eld may also °ow via nitrogen-related

tunneling sites. In case of reoxidized nitrogen treated ¯lm (SGC3ONO), the gate

Figure 4.12: Gate current versus voltage for stacked oxynitride ¯lms grown on

Si Ge C layers. SGC3ONO: O /NO/O plasma; SGC3NON: NO/O /NO0:69 0:3 0:01 2 2 2

plasma; SGC3ONHN: O /NH /NO plasma.2 3

current decreases drastically due to the out di®usion of nitrogen from the oxynitride

[195]. In case of SGC3NON and SGC3ONHN samples, reoxidation by NO replace

many strained Si-H and Si-O bonds by Si-N, resulting in a higher current density

compared to SGC3ONO ¯lms [167]. This is in agreement to the reported results that

¯lms with higher nitrogen content show higher breakdown strength [193].

On constant voltage stressing at -10 V and -14 V for 300 s, the I-E characteristics

was measured again for SGC3ONO, SGC3NON and SGC3ONHN capacitors. The

ratio of increase in current after stressing to the initial (prestress) current (¢I /I ) isg g

plotted as a function of electric ¯eld in ¯gure 4.13. For SGC3NON and SGC3ONHN

83

¯lms, a small increase of current is observed at a low electric ¯eld where as a drastic in-

crease of current is observed in SGC3ONO one. The breakdown properties of ultrathin2oxynitride ¯lms have also been investigated using a constant current (-50 mA/cm )

2 2stressing. The breakdown occurs after a charge injection of 22.1 C/cm , 36.0 C/cm

Figure 4.13: ¢I /I vs. gate voltage on constant voltage stressing of -10 V and -g g

14 V for 300 s. SGC3ONO: O /NO/O plasma; SGC3NON: NO/O /NO plasma;2 2 2

SGC3ONHN: O /NH /NO plasma of 2 mins.2 3

2and 40.5 C/cm for SGC3ONO, SGC3NON and SGC3ONHN oxynitride ¯lms, re-

spectively. Charge-to-breakdown property of O /NH /NO-plasma grown oxynitride2 3

is found to be superior to that of O /NO/O and NO/O /NO treated oxynitride2 2 2

¯lms. This is associated with enhanced nitrogen incorporation in O /NH /NO di-2 3

electric rather than O /NO/O and NO/O /NO-plasma grown ones. Final treatment2 2 2

in O -plasma degrades the breakdown characteristics of oxynitride ¯lms.2

4.2.4 Trapping Behavior Under Static Stress

A constant current stressing technique has been used to investigate the high-

¯eld charge trapping behavior of gate dielectrics with reoxidized NO treated oxide

84

(SGC3ONO), double wall N incorporated oxide (SGC3NON) and reoxidized nitrided

oxide ¯lm (SGC3ONHN). Figure 4.14 shows the change of gate voltage (¢V ) re-G

Figure 4.14: Gate voltage shift vs. stress time for di®erent dielectrics on par-2tially strained Si Ge C under a constant current stressing of -0.5 mA/cm .0:69 0:3 0:01

SGC3ONO: O /NO/O -plasma, SGC3NON: NO/O /NO-plasma and SGC3ONHN:2 2 2

O /NH /NO-plasma.2 3

quired to maintain a constant current through oxynitride ¯lms during electron in-

jection from the gate electrode. It is observed that during the stress ¢V is shiftedG

to the negative voltage axis for SGC3ONHN ¯lm and towards the positive direc-

tion for SGC3ONO and SGC3NON ¯lms. It is evident that H-containing dielectric

SGC3ONHN ¯lm is characterized by the presence of electron traps even after reoxi-

dation. The double wall N-incorporated oxides exhibit the highest immunity to the

formation of stress induced trapping centers. Relatively lower trapped charges in

samples SGC3ONHN and SGC3NON are due to the presence of oxygen at Si/SiO2

interface in SGC3ONO ¯lm, and the replacement of Si-O strained bonds by Si-N

bonds [196] in the former.

The trapped charge density (Q ) has been measured using the bidirectional I-Vt

technique [197], where a voltage shift is observed under constant voltage injection.

85

The interpretation of the I-V characteristics after charge injection by constant current

(voltage) stressing is complicated. The gate current depends on the barrier height

and on the position of the potential maximum in the insulator near the injection

contact. The characteristics are sensitive to the internal ¯eld and the space charge

Figure 4.15: Trapped charge density of plasma grown oxynitride ¯lms on partially

strained Si Ge C ¯lms under constant voltage (-10 V, -12 V and -14 V) stress-0:69 0:3 0:01

ing. SGC3ONO: O /NO/O plasma; SGC3NON: NO/O /NO plasma; SGC3ONHN:2 2 2

O /NH /NO plasma of 2 mins.2 3

in the oxide which, in turn, a®ect the barrier height and the position of the potential

maximum near the interface [198]. A trapping event is followed by releasing an energy

leading to breaking of bonds [199]. The trapping centroid (X ) and trapped chargest

(Q ) are given by [199]t " #¡1¡¢VF NX = t ¢ 1¡ (4.2)t ox +¢VF N

and " #²ox ¡ +Q = ¢ ¢V ¡¢V (4.3)t F N F Ntox

86

¡where X is the distance measured from the metal gate/oxide interface, ¢V ist F N

+the negative gate voltage shift, ¢V is the positive gate voltage shift and t isoxF N

the oxide thickness. Trapped charge densities under di®erent voltage stress (-10V,

-12V and -14V) are shown in ¯gure 4.15. Trapped charges in the O /NH /NO-grown2 3

¯lms are found to be suppressed as compared to O /NO/O and NO/O /NO-grown2 2 2

oxynitrides. The result is consistent with trapping behavior shown in ¯gures 4.11 and

4.14.

4.2.5 Trapped Charge and Charge Centroid under Dynamic

Stress

Being closer to operating conditions, dynamic stress are better suited for the

evaluation of reliability of gate dielectric in MOS devices. Trapped charge and charge

centroid of oxynitride ¯lms were studied by applying pulsed unipolar and bipolar

stresses, the stress voltage (V ) being applied to the gate electrode. A square voltageS

waveform was used for both the bipolar and unipolar stresses. For bipolar stress, the

voltage was a symmetric bipolar square wave with +V during positive half-cycle andS

-V during the negative half-cycle. Unipolar one was divided into two subgroups: theS

positive unipolar stress (i.e., the voltage was maintained at +V during one half-cycleS

and at 0 V during the next half-cycle.) and the negative unipolar stress (i.e., theS

voltage was maintained at -V during one half-cycle and at 0 V during the nextS S

half-cycle). An ac pulse voltage stress has been used to characterize the trapping

behavior of di®erent oxynitride ¯lms by Tektronix TM-503 pulse generator.

Figure 4.16(a) shows the trapped charge distribution in dielectrics subjected to

unipolar square voltage stresses of both polarities at a frequency of 200 Hz. The

evolution during the total stress time (»2000 s) is shown for both the polarity. Thefast increase at the beginning of the stresses (due to the ¯lling of native traps and a

high rate of generation of new traps) followed by a slower evolution is mainly caused

by the reduction of the generation rate due to trapping. It is noted that the evolution

of the trapped charge density is dependent on the stress polarity as observed in ¯gure

4.16(a), though Rodriguez et al. [200] reported that the trapped charge density is

independent of the stress polarity.

For the same amplitude of applied voltage, electric ¯eld strength in the oxynitride

¯lm is di®erent for positive and negative voltages. The electric ¯eld in the oxynitride

87

¯lm E is evaluated as follows. For inversion, E is obtained by taking into accountox ox

of V and surface potential at inversion 2Á (qÁ is the energy di®erence betweenF B F F

Figure 4.16: Trapped charge distributions in oxynitride ¯lms grown on

Si/Si Ge C /Si subjected to 10 V unipolar stress of both polarities: (a)0:795 0:2 0:005

trapped charge density and (b) charge centroid .

88

the midgap position and the Fermi level in the bulk of the substrate) as [201]

E = (V ¡ V ¡ 2Á )=t (4.4)ox S F B F ox

where V is the voltage applied to the gate. For accumulation, E is de¯ned as [201]S ox

E = (V ¡ V ¡ 0:55 + Á )=t (4.5)ox S F B F ox

As the substrate is p-type, positive voltage corresponds to the inversion while the

negative voltage corresponds the accumulation. The values of V and Á are -0.9F B F

ºand 0.26 V, respectively, for the 80 A oxide ¯lm grown on a p-type substrate. During

injection from the gate (negative polarity), the electric ¯eld across the oxide has been

estimated to be ¼1.27 MV/cm lower than the applied ¯eld. It is observed that Qt

is higher in case of negative unipolar stress compared to positive one at higher oxide

¯eld and the reasons are as follows. For positive voltage, the interface trap generation

is attributed to the recombination of trapped holes with electrons and to the bond+breaking by the hydrogen (H and H ) released during stressing. For negative voltage,

in addition to these two mechanisms, the bond breaking by energetic electrons may

also contribute to interface trap generation [202]. Chaparala et al. [203] observed the

increase of interface trap generation under negative unipolar stress with the increase

of oxide ¯eld. This may be due to the fact that the current °owing through the oxide

increases as the oxide ¯eld increases. Trapped charges in O /NH /NO-grown ¯lms are2 3

found to be suppressed as compared to H /NO and NH /NO-grown oxynitrides due2 3

to higher nitrogen incorporation at the Si/SiO interface in the former. The evolution2

of charge centroid in ¯gure 4.16(b) is very similar to the trapped charge distribution.

Due to injected charges, the centroid of charge distribution shifts towards the injecting

interface.

Figure 4.17(a) shows the trapped charge distributions obtained in MOS capacitors

subjected to square bipolar stresses of 10 V at several frequencies having »2000s duration. The initial transient during which the charge density increases and a

second stage in which the process is slowed down are, respectively, due to the e®ect

of trapping and the decrease of the generation probability. A frequency dependence

is clearly observed: the higher the frequency, the slower is the generation process and

the lower is the trapping level [204, 205]. It has been reported that the trapping

and detrapping transients at the interfaces are observed when the stress polarity is

changed [206]. These transients gain relative importance when the stress frequency

increases, so that a considerable fraction of the semiperiod does not contribute to the

89

oxynitride ¯lm degradation. If the stress frequency is high enough, these processes

at the interfaces will not have enough time to reach the steady state occupation

Figure 4.17: Trapped charge distributions in dielectrics grown

on Si/Si Ge C /Si subjected to 10 V bipolar stress at di®erent frequencies:0:795 0:2 0:005

(a) trapped charge density and (b) charge centroid.

90

and, consequently, the trapped charge density will be smaller. A combination of these

two factors (reduced degradation rates and transient occupation at the interfaces) is

responsible for the lower trapped charge densities measured at a higher frequency.

Figure 4.17(b) shows the evolution of the centroid of the distribution (measured

from the metal/SiO interface) with the stress time. At low enough frequencies,2

the position of the centroid in the steady state regime can be predicted as a weighted

average of the centroids. At high frequency, however, the reduction of the degradation

rate and of the electron trapping in regions closer to the interfaces cause the centroid

to be mainly controlled by the distribution of native traps.

4.2.6 Charge-to-Breakdown Characteristics

Figure 4.18 shows the gate voltage versus stress time under a constant current

Figure 4.18: Typical examples for the evolution of the gate voltage during constant2current stress of -50 mA/cm . SGC1HN: H /NO- plasma; SGC1NHN: NH /NO-2 3

plasma; SGC1ONHN: O /NH /NO-plasma of 2 mins.2 3

2stress (-50 mA/cm ). The dielectric breakdown is determined by the large drop

in the applied voltage that suddenly occurs. The small discontinuous voltage drop

corresponding to soft breakdown (SBD) occurs in the oxide [188, 205] at lower charges.

91

After SBD, a small voltage °uctuation is observed and hard breakdown occurs

as seen by the large drop in applied voltage. Breakdown is found to be occurred on2 2 2the injection of charges of 47.0 C/cm , 60.0 C/cm and 86.0 C/cm for SGC1HN,

SGC1NHN and SGC1ONHN samples, respectively. Compared to SGC1HN and

SGC1NHN dielectrics, a high Q in SGC1ONHN ¯lm may be due to the replace-BD

ment of Si-H bonds by Si-O and Si-N bonds. The breakdown properties of various

oxynitride ¯lms grown on SiGe and SiGeC layers are presented in Table 4.3. It is

noted that both the soft and hard breakdown are higher in case of capped SiGeC

Table 4.3: Breakdown characteristics of SiGe and SiGeC layers

2 2Sample Group-IV alloy Q (C/cm ) Q (C/cm )SBD BD

SG2O Si Ge 12.5 -0:74 0:26

SG2N " 37.5 -

SG2NON " 50.9 -

SGC1HN Si Ge C 21.5 47.00:795 0:2 0:005

SGC1NHN " 44.6 60.0

SGC1ONHN " 73.7 86.0

SGC3ONO Si Ge C - 22.10:69 0:3 0:01

SGC3NON " - 36.0

SGC3ONHN " - 40.5

¯lms compared to uncapped SiGe and SiGeC ¯lms. Higher charge-to-breakdown is

also observed in NO/O /NO and O /NH /NO oxynitride ¯lms compared to other2 2 3

growth combinations.

4.3 Summary

The growth of ultrathin oxynitride ¯lms at a low temperature on strained SiGe

and SiGeC layers has been carried out using microwave plasma. The `N' pro¯le

and the location of `N' and `O' in the dielectric have been varied by changing the

sequence of plasma chemistry. When the oxynitride ¯lms are subjected to high ¯eld

stressing, signi¯cant border trap generation takes place. The dangling bond defects

created by bond breaking are the likely cause of border traps. Compared to O -2

92

plasma grown oxide, the NO- and NO/O /NO-plasma grown oxynitrides show better2

electrical properties under constant voltage and constant current stressing in terms

of generation of border traps and charge-to-soft breakdown. The double `N' wall in

the stacked oxynitride ¯lm (NO/O /NO-plasma) is found to be best in reducing the2

trap generation and improving the breakdown characteristics of the dielectric.

The e®ect of hydrogen on charge trapping behavior of oxynitride ¯lms grown

on Si/Si Ge C /Si heterolayers has been studied. Excellent electrical prop-0:795 0:2 0:005

erties in terms of charge trapping and breakdown mechanism under static and dy-

namic stress are observed in reoxidized NH nitrided oxides (sample: SGC1ONHN).3

Electrical properties of stacked oxynitride ¯lms grown on Si Ge C have also0:69 0:3 0:01

been studied. Compared to O /NO/O -plasma grown oxynitride, NO/O /NO and2 2 2

O /NH /NO oxynitride ¯lms show excellent electrical properties in terms of charge2 3

trapping and charge-to-breakdown characteristics under constant current stressing

due to enhanced nitrogen incorporation at Si/SiO interface.2

93

Chapter 5

Design and Simulation of SiGe

p-MOSFETs

A major advantage of SiGe is its compatibility with conventional CMOS technol-

ogy and both ¯eld e®ect and bipolar devices may be fabricated on a single Si chip

[207]. For MOSFETs, various types of channel have been proposed; surface channel

in which carriers propagate along the surface and in some devices such as depletion

mode devices, carriers propagate slightly under the surface and is known as a buried

channel device. The buried channel device has an added advantage over the surface

channel device; improved immunity to hot carrier degradation. The buried channel

operation has been known to yield a higher carrier mobility due to reduction in the

¯eld and avoids surface scattering. The e®ective gate capacitance is reduced as the

channel is further away from the surface, and the improvement in mobility cannot be

fully utilized. However, buried channel and surface channel MOSFETs behave simi-

larly in long channel regime. A substantial di®erence (threshold voltage lowering and

poor turn o® characteristics) is observed in device operation in short channel region.

Buried channel transistors have been advocated as a better choice for short channel

operation [208] and also o®er the possibility of improvement in packing density and

speed in VLSI applications.

Figure 5.1 shows the schematic diagram of several possible con¯gurations of MOS-

FETs using strained Si Ge and strained-Si channel. The SiGe-channel device (¯g-1¡x x

ure 5.1(a)) has a single layer of strained SiGe grown on top of the Si spacer layer. It

is di±cult to grow a high quality gate oxide directly on Si Ge due to preferential1¡x x

oxidation of Si leading to a pile-up of Ge at the oxide/SiGe interface [128]. In ¯gure

94

5.1(b), oxidation of the Si-cap (leaving an optimized unconsumed Si-cap layer) as-

sures formation of a high quality gate oxide. The structure reduces the e±ciency to

which the high mobility carriers in the Si Ge layer can be modulated due to the1¡x x

increased physical separation from the gate potential and the presence of a surface

inversion layer that forms at high gate overdrive.

Figure 5.1: MOSFET device structures for strained SiGe without Si-cap, strained-

Si, strained SiGe with Si-cap, and strained SiGe with Si-cap on doping spike: (a)

SiGe-channel on the surface, (b) SiGe buried channel, (c) strained-Si channel on the+surface, and (d) SiGe buried channel with p doping spike.

The surface channel device (¯gure 5.1(c)) has a single layer of thin strained-Si

grown on top of the relaxed Si Ge bu®er layer. This layer is oxidized to form gate1¡x x

oxide. The structure shows the type-II band o®sets and has several advantages over

the more common type-I band alignment, as a large band o®set is obtained in both

the conduction and valence bands, relative to the ralaxed Si Ge layer [12]. This1¡x x

is favorable for both the electron and hole con¯nement, making it useful for both n-

95

and p-type devices for strained Si/SiGe-based CMOS technology [20, 209].

Several studies have shown that the formation of low mobility surface channel in

Si/Si Ge heterojunction p-MOSFETs greatly reduces their performance [59]. To1¡x x

reduce the carrier population in the surface channel, Si/Si Ge heterojunction p-1¡x x

MOSFET with a buried ±-doping layer, separated by a Si spacer layer, (¯gure 5.1(d))

have been proposed by several researchers [62, 105, 210, 211]. The doping spike per-

forms two functions:

a) it creates a retarding electric ¯eld for holes at zero gate bias to suppress source/drain

leakage current (threshold adjust), and

b) it provides holes for the Si Ge channel for improved device transconductance.1¡x x

Figure 5.2: MOSFET device structure for strained SiGe on SOI substrate

Scaled devices have inherent problems that are associated with parasitic circuit

elements arising from junction capacitance. A way to circumvent the problem is to

fabricate devices in small islands of Si on an insulating substrate [212, 213]. The ini-

tial approach to fabricate such a structure was to grow Si epitaxially on a substrate

of sapphire. Silicon-on-insulator (SOI) technology promises very high performance

integrated circuits for numerous applications at the deep sub-micron regime. SOI

96

CMOS and BiCMOS devices have recently emerged as an attractive integrated cir-

cuit technology for low voltage and low power applications [214, 215]. SOI MOSFETs

show a performance advantage over conventional Si MOSFETs because of improved

device isolation, reduced parasitic capacitance, lower power consumption, better sub-

threshold swing, higher current drive, and suppression of °oating body e®ect. These

properties have been exploited in the fabrication of high speed SOI VLSI circuits [74].

In order to get higher hole con¯nement in the strained SiGe-channel, SiGe p-

MOSFETs have been demonstrated on a silicon-on-insulator (SOI) structure using

SIMOX [216]. The SOI structure consisted of a Si-cap layer on a strained Si Ge on1¡x x

buried-oxide-layer as shown in ¯gure 5.2. A key factor in realization of the SOI struc-

ture is the fabrication of a SiGe on insulator substrate by SIMOX technology [216].

The growth of high quality Si/Si Ge /Si structure on SIMOX may be hindered by1¡x x

the presence of residual defects (dislocations, contaminants, disorder in top-Si/buried-

oxide interface) during SIMOX formation [217, 218, 219, 220]. Improved quantum

con¯nement at the SiGe-well on SIMOX substrate compared to SiGe on Si substrate

was reported using photoluminescence (PL) measurement by Nayak et al. [76].

Hole mobility of SiGe-channel p-MOSFETs using ±-doping spike or SOI substrate

has been reported by several authors. Optimization of MOS structures is essential to

increase the hole density as well as hole mobility in the Si Ge layer over the hole1¡x x

density in the Si-cap layer, thus increasing the gate voltage window within which only

the buried channel is turned on. In this chapter, we consider the design and simulation+of SiGe-channel p-MOSFETs on Si substrate including devices with p ±-doping spike.

Device design is considered in detail. The charge distribution is predicted using 1-D

Poisson simulation and analytical model with quantum mechanical solutions. The

design is optimized for the following device parameters: thickness of the cap layer,

thickness of the gate oxide, thickness and Ge content of the Si Ge channel, boron1¡x x

doping beneath the channel and the e®ect of buried oxide below the channel. A 1-D

Poisson solver, semi-analytical models and Silvaco simulation tool [221] are used to

investigate the design and simulation of di®erent heterostructures on Si and SIMOX

substrates.

97

5.1 Review on Previous Work

5.1.1 Simulation of SiGe-channel p-MOSFETs

Several papers on both the numerical and analytical modeling of SiGe p-MOSFETs

have appeared [61, 68, 105, 222, 223] and some of the parameters such as e®ective

channel length (L ), Ge concentration (x), transconductance (g ), and low ¯eldeff m

mobility (¹) are listed in Table 5.1.

Verdonckt-Vandebroek et al. [68] simulated 0.2¹m SiGe p-MOSFETs with a 7

nm thick gate oxide, a 5 nm thick Si-cap layer and a 8 nm wide SiGe-channel. The

SiGe-channel had a graded pro¯le with 45% Ge at the top and 25% Ge at the bottom

resulting in a stable SiGe layer satisfying the Matthews-Blakeslee criterion. The

device was simulated by HETMOD yielding the peak linear transconductance 20

mS/mm.

Voinigescu et al. [222] reported the simulation on subthreshold characteristics, hot

carrier injection, and high frequency performance of Si/SiGe FETs. The transcon-¡2ductance and mobility were found to be 37.9 mS/mm and 400 cm /V.s, respectively.

The results indicate that by fully grading the Ge content in the channel of a MOS-

FET, short channel e®ects are reduced and high frequency performance is improved

as compared to devices with uniform Ge channel. Energy balance simulation reveals

that hot carrier injection at the Si/SiO interface is also considerably suppressed.2

Cho et al. [61]. analyzed the e®ect of substrate engineering for ±-doped SiGe p-

MOSFETs using a 3D device simulator, DAVINCI. Results of the simulation showed

a higher current (220%) drive capability for the ±-doped devices compared to con-

ventional Si p-MOSFETs. Sadek et al. [211] reported a device design consisting of a

relaxed Si Ge bu®er and strained Si Ge (0.7>x>0.5) quantum well. Transport0:7 0:3 1¡x x

was modeled using 2-D drift-di®usion and hydrodynamic numerical simulations. An2intrinsic transconductance as high as 150 mS/mm and the mobility 800 cm /V.s with

a channel length 0.25 ¹m were reported.

Ouyang et al. [223] proposed a heterojunction p-MOSFET transistor structure

with a reduced short channel e®ect using MINIMOS-NT simulator. Simulation results

of devices with 100 nm physical gate lengths were presented. The drive current was

80% higher compared to an optimized Si device. Shi et al. [224] reported a strained

Si Ge buried channel p-MOSFET with a Ge concentration up to 50%, simulated1¡x x

98

using the MEDICI. Simulation results for a channel length 0.35 ¹m showed that the

maximum drain current increases (300%) monotonically with the Ge mole fraction.

Table 5.1: Reported simulation results for SiGe-channel p-MOSFETs

Parameter [68] [222] [61] [211] [224]

L (¹m) 0.2 0.25 0.13 0.2 0.35eff

ºt (A) 70 50 40 50 85ox

ºt (A) 25 50 - 10 10cap

ºt (A) 80 150 200 40 100well

Ge mole 0.25-0.45 0-0.5 0.2 0.75-0.55 0.5

fraction, x (graded) (graded) (graded)

ºt (A) - 50 200 - -sp

ºt (A) - 80 50 - -A

¡3 18 19N (cm ) - 2£10 1£10 - -A

¡3 16 17 17 17N (cm ) 5£10 6£10 - 3£10 1£10d

g at 300 K 20 37.9 - 150 -m

(mS/mm)

Improved drive - - 220 - 300

current (%)

Simulator HETMOD Silvaco- DAVINCI 2D Hydro- MEDICI

ATLAS dynamic

In order to derive the bene¯ts of high mobility in Si Ge alloys without seri-1¡x x

ously degrading other properties, simulation and sensitivity analysis are necessary to

optimize the device design, material growth and device processing. Several authors

[61, 211, 223, 224] reported the drive current dependence on device performance. How-

ever, there still exists a scope for an optimized device design to achieve symmetrical

device behavior with minimized contribution from the parasitic surface channel.

5.1.2 p-MOSFETs on SIMOX

Several researchers [74, 212, 213, 216, 225] reported experimental and simulation

results of SiGe-channel p-MOSFETs on SOI or SIMOX substrate. From the view-

point of device technology, however, the biggest concern is the °oating-body e®ect,

99

which is known to manifest itself as lowering of abnormal subthreshold slope [226],

current instability in switching operation, enhanced leakage current in DRAM cells

Table 5.2: Reported results of SiGe-channel p-MOSFETs on SOI, SOS and SIMOX

substrates

Parameter [216] [74] [213]

Channel length, L (¹m) 10 1.0 0.05eff

ºOxide thickness, t (A) 65 80 20ox

ºCap thickness, t (A) 100 70 40cap

ºWell thickness, t (A) 100 120 150well

Ge concentration, x 0.3 0.2 0.0-0.3

ºSpacer thickness, t (A) 1600 100 -sp

¡3 15 17Channel doping, N (cm ) 1£10 4£10 undopedd

ºBuried oxide thickness (A) 4100 1000 4500

g at 300 K (mS/mm) 0.72 »3.5 -m

Improved drive current (%) - - 70

Substrate type SIMOX SOS SOI

[227] etc. To suppress the °oating body e®ect in SOI MOSFET's, Yoshimi et al.

[225] reported the bandgap engineering method using a SOI SiGe structure. Mathew

et al. [74] demonstrated the enhanced low ¯eld mobility, transconductance, and

noise ¯gure performance for SiGe MOSFETs using silicon-on-sapphire technology.

Reported room-temperature and low-temperature hole mobility enhancement using

SiGe-channel was seen to vary from 30% to 70% (depending upon Ge concentration)

over that of Si. Yeo et al. [213] reported a SOI SiGe p-channel MOSFET with 50

nm channel length. Enhanced drive current (70%) was reported [213] due to the

introduction of Si Ge on SOI structure. Choi et al. [212] reported a 40 nm gate0:7 0:3

length MOSFET with the suppression of short-channel e®ect.

Among the various SOI and SOS technologies, SIMOX is probably the best can-

didate for the improvement of mobility in SiGe-channel p-MOSFETs. Nayak et al.

[216] reported SiGe-channel p-MOSFET on SIMOX substrates. The device consists

of a Si/Si Ge /Si channel, which is grown pseudomorphically on a SIMOX sub-0:7 0:3

2strate. The e®ective channel mobility (181 cm /V.s) of this device was found to be

90% higher than that of an identically processed conventional SIMOX device. Table

100

5.2 shows some reported device parameters for SiGe-channel p-MOSFETs on SOI,

SOS and SIMOX substrates.

5.2 Simulation of SiGe p-MOSFETs

In this section, the charge distribution in the surface (Si-cap) and buried SiGe-

channel of Si Ge p-MOSFETs under various gate biases using semi-analytical1¡x x

model is presented. The model is based on analytical, quantum mechanical descrip-

tions for hole charge in the SiGe quantum well and Si-cap, and requires no ad-hoc

¯tting parameters. The charge screening e®ect that limits the maximum number of

charge carriers in the SiGe layer is explicitly revealed using this formulation.

Figure 5.3: A cross-sectional schematic of a Si Ge quantum well MOS structure1¡x x

and band diagram for an arbitrary negative gate bias.

101

The idealized MOS structure under investigation is shown in ¯gure 5.3 and consists+of the following layer sequence: Si substrate; p -doping spike; Si spacer layer; SiGe

quantum well; Si-cap layer; oxide and gate metal. It is assumed that the semiconduc-3tor region is doped uniformly throughout with N donors/cm , with the exception ofd

+ 3the p -doping spike which is doped with N acceptors/cm , and thin enough so thatA

it is fully depleted at zero gate bias. The band diagram shown in ¯gure 5.3 is for an

arbitrary negative gate bias condition and de¯nes the notation used throughout this

section. The treatment presented below utilizes quantum mechanical description for

mobile charge distributions in the Si-cap and in the SiGe layers, denoted by Q andcap

Q , respectively. The gate potential is related to the internal charges and potentialwell

viz.:

V = Ã + V + V (5.1)G s ox F B

where à is the internal electrostatic potential at the Si/SiO interface, V is thes 2 ox

voltage drop across the oxide due to free carrier and depletion charges within the

device and V is the °atband voltage, and the total charge is given byF B

Q = Q +Q +Q (5.2)tot cap well dep

where Q =-qN t and Q =-qN t .cap d cap well d well

In structures that do not contain any doping spike and a spacer layer, the carrier

distribution computation begins approximately at the °atband voltage. For a device+that does contain p ±-doping and a spacer layer, the layer is fully depleted and

the doping spike can be treated as a sheet of negative charge, similar to the ¯xed

oxide charge in a conventional Si MOS structure. As such, the doping spike acts as

a threshold adjust, causing downward band bending at zero gate bias that results in

electron accumulation at the Si/SiO interface. The slope of the band bending on2

either side of the doping spike is obtained as

dà qN tA A= § (5.3)

dx ²Si

where the plus and minus sign are applied to the right and the left, respectively,

of the sheet of acceptor charges. Neglecting the e®ect of free carriers (reasonable at

low gate biases), the magnitude of the potential perturbation due to the doping spike

can be approximated as:2 2qN t qN tA A A dep

¢Ã = + (5.4)2² ²Si Si

102

where t =(t /2)(N /N ), represents the thickness of donor depletion charge ondep A A d

either side of the doping spike. Potentials of di®erent heterostructure interfaces are

found to be:qN t tA A sp

à = ¢Ã ¡ (5.5)rw²Si

qN t tA A wellà = à ¡ (5.6)w rw

²SiGe

qN t tA A capà = à ¡ (5.7)s w

²Si

where à is the potential at top Si/SiGe interface and à is the potential atw rw

bottom SiGe/Si interface. These potentials are related to free carrier charges and the

calculation for the quantum well MOS structure is done.

5.2.1 Hole Density in the SiGe-well

To ¯nd the free carrier density in the SiGe layer (Q ), the region is treated as awell

quantum well for holes due to the observation that most of the bandgap discontinuity

between strained SiGe and Si resides in the valence band. Using the in¯nite well

approximation, the eigen energy:

2 2 2¼ h nE = ; (n = 1; 2; 3; :::::) (5.8)n ¤ 22m twellk

(0)with the carrier wave function, Á , given by:n s " #2 n¼x(0)Á = sin (5.9)n t twell well

¤where the e®ective mass, m , refers to the longitudinal e®ective mass since quan-

tization is occurring along the z direction [228]. The areal hole density (p ) is thenwell

obtained by multiplying the two-dimentional density of states with the Fermi integral

of order zero [229]:

Z¤ El2m dEDp = (5.10)well 2 1 + exp[(E ¡ E )=kT ]¡1¼¹h f

¤where m refers to the density-of-states e®ective mass of the heavy hole band atD

the Brillouin zone center [230]. A hole degeneracy factor of two is used in the above

rather than the conventional value of four since the strain in the SiGe layer lifts

103

the degeneracy at the zone center between the heavy hole and light hole bands. The

foregoing derivation for p is only valid for the condition where there is no potentialwell

variation across the well (i.e. Ã =Ã ). With an applied gate bias, the eigen energiesw rw

change (Stark shift) and can be approximated to ¯rst order using non-degenerate

perturbation theory as [231]:(0)E = E +H (5.11)n nnn

(0)where E are unperturbed eigen energies and H =(jà - à j)/2, represents then nn w rw

thn level perturbation matrix element. The areal electron density in the SiGe layer

can be computed for a given hole density from the law of mass action:

SiGe 2 2(n ) ti welln = (5.12)well

pwell

SiGewhere n is the intrinsic carrier concentration in Si Ge . The net areal mobilei 1¡x x

charge density in the SiGe layer is the di®erence between the areal hole and electron

charge densities, Q =q(p -n ).well well well

5.2.2 Hole Density in Si-cap

For larger band bending at the Si/SiO interface, the Boltzmann approximation2

fails to account for the degenerate buildup of carriers. Under these conditions, the

Si-cap be treated as a quasi-triangular potential well for holes. In this case, the

Si/SiO interface is treated as an in¯nite potential barrier, and eigenenergies within2

the triangular well are approximately given by [232]:

" # " #1=3 2=32¹h 3¼® 3E = (n+ ) (5.13)n ¤2m 2 4

where ®=q(jà - à j)/t , is related to the slope of the triangular well. Similars w cap

to the two-dimensional formulation used, p is found to be:cap

" #i¤ X4kTm (E ¡ E )n fDp = lnf1 + exp g (5.14)cap 2 kT¼¹h n=0

¤where m refers to the density-of-states hole e®ective mass for Si and the factorD

of four accounts for the degeneracy between the heavy and light hole bands at the

zone center. The su±cient con¯nement is de¯ned at the calculation index where the

di®erence, j qà - qà j, exceeds the ground state energy (n=0).s w

104

Carrier distribution in the Si-cap and SiGe-well as a function of gate bias depends

on the charge distribution in the heterolayers using electrostatic potential calculation.

With the °ow diagram as shown in ¯gure 5.4, new values for the free carrier and

Figure 5.4: Flowchart for algorithm to compute the charge densities and potentials

in a MOS structure.

depletion charges are calculated from the extrapolated potential function, and are

applied to the next calculation. The total band bending, qà , is incremented by a sets

amount between calculations to determine the potentials qà , qà and to study thew rw

free hole distribution in the surface and buried channel. The results of the analytical

model will be presented in subsection 5.3.4.

105

5.3 Design of SiGe p-MOSFETs

Two-dimensional (2-D) device simulator, Silvaco-ATLAS [221], which can handle

complicated device structures, has been used for the simulation of p-MOSFETs. The

simulation domain is partitioned into segments where arbitrary material properties

and di®erent physical models can be de¯ned independently. The segments are linked

together by various interface models. Fermi-Dirac statistics for carrier population

and a dense mesh speci¯cation for thin epitaxial layers has been used for accurate

calculation of charge distributions.

For heterostructures, the abrupt interface changes in band-edge energies has been

incorporated in the drift-di®usion (DD) model. The material parameters used for

Si Ge channel are described in ref. [221]. The reduction in carrier e®ective mass1¡x x

and e®ective density of states is also appropriately accounted for. The permittivity

is linearly interpolated between that of Si and Ge.

The critical design parameters for SiGe-channel p-MOSFETs are the choice of

gate material, the method of threshold voltage adjustment, the SiGe pro¯le in the

channel, the Si-cap and well thickness, and gate oxide thickness. The key design

parameter of a MOSFET is the device transconductance. This can be enhanced by

maximizing the number of high mobility holes con¯ned to the SiGe channel while

minimizing the density of low mobility holes, which °ow at the Si/SiO interface.2

±-doping spike has been used to enhance the transconductance and better control of

threshold voltage adjustment of the device.

5.3.1 Choice of Gate Material

The choice of gate material has a signi¯cant e®ect on the turn-on characteristics

of p-MOSFETs. In ¯gure 5.5, the hole distribution in SiGe channel and Si-cap layer+ +as a function of gate voltage is given for n - and p -gate Si Ge quantum well1¡x x

p-MOSFETs using a 1-D Poisson solver. The basic structural parameters used in

simulation for the hole distribution are given in Table 5.3.+ +Hole con¯nements show identical nature for both p - and n -poly gate Si Ge1¡x x

p-MOSFETs. The threshold voltages are di®erent due to di®erent work functions.

The amount of shift is equal to Si bandgap. But, the threshold voltage for a SiGe p-

MOSFET is lower than that of a Si MOSFET. This is due to the introduction of energy

band discontinuity in the valence band of Si/Si Ge interface. This di®erence in1¡x x

106

Table 5.3: Parameters used in simulation for a baseline structure.

Parameter Value

Work function, Á (eV) 4g

ºOxide thickness, t (A) 80ox

ºCap layer thickness, t (A) 50cap

ºWell thickness, t (A) 100well

ºSpacer layer thickness, t (A) 50sp

Ge mole fraction, x 0.3

º±-doping spike, t (A) 50A

¡3 18Doping in ±-doping spike, N (cm ) 2£10A

¡3 16Channel doping, N (cm ) 1£10d

threshold voltage between Si and SiGe MOSFET is valid provided that the hole

density in the cap layer is negligible at turn-on voltage.

+ +Figure 5.5: Hole distribution as a function of gate voltage for n - and p -poly gate

devices.

107

The holes are mostly con¯ned in the quantum well at the buried channel thresh-+old voltage (V ). If a p poly-Si gate is used with a buried channel p-MOSFET,T H

+the device operates in the depletion mode. However, if a n poly-Si gate is used,

the device threshold voltage is shifted negatively by approximately 1.0 V (silicon's

bandgap). Consequently, the buried channel device operates in enhancement mode

with the buried channel carrier transport properties determining the MOSFET elec-

trical characteristics at low gate biases.

For an optimal epitaxial structure, the cross-over voltage should occur at a large

negative gate bias and with a high hole density in the SiGe-channel. To promote high

speed operation, the p-MOSFET should be operated under bias conditions where the

hole population in the SiGe-well exceeds that in the Si-cap. The cross-over voltage+ + +for n -gate is higher than that of a p -gate MOSFET. Hence, a n gate design is

favorable for the p-MOSFET devices because it promotes transport through SiGe-well

for low gate biases.

5.3.2 E®ect of Ge Concentration

Figure 5.6: Low frequency (LF) C-V characteristics of a SiGe-MOS capacitor as a

function of Ge composition.

108

Ge mole fraction in the SiGe layer plays a critical role in determining the cross-over

voltage. A large valence band o®set at the top Si/SiGe interface results in a better

hole con¯nement [59]. Strain relaxation issues set the upper limit on the amount of

band o®set that can be achieved by the incorporation of Ge. For a ¯xed amount of

strain, it is advantageous to minimize the thickness of SiGe layer and increase the Ge

mole fraction.

Simulated low frequency C-V characteristics of Si Ge (x=0.2, 0.3 and 0.4)1¡x x

MOS capacitors using 1-D Poisson solver is shown in ¯gure 5.6. The plateau in

accumulation shows the hole con¯nement at the Si/Si Ge interface. The hole1¡x x

con¯nement increases with Ge content as the valence band o®set increases [233]. As

the structure is biased more negatively, an accumulation layer in the Si-cap forms and

the capacitance of the structure approaches the oxide capacitance. The accumulation

layer carrier population in the surface channel (Si-cap) and buried channel (SiGe-well)

have been extracted by integrating the carrier pro¯les across the total depths of these

Figure 5.7: Hole concentration in Si-cap and SiGe-channel as a function of Ge mole

fraction in a SiGe p-MOSFET.

layers. The enhanced hole population in Si Ge with increased Ge concentration1¡x x

+(x) is illustrated in ¯gure 5.7 where the n -poly Si gate MOSFET cross-over voltage

109

is shown to increase (arrows) with x. The cross-over voltage is linearly proportional

to the Ge concentration. As expected, more carriers °ow in the Si-cap layer as the

gate voltage (V ) increases and the device becomes a surface channel one. In orderG

to ensure that the majority of holes °ow in the SiGe-channel for gate voltages equal

to or higher than -3.0 V, the Ge percentage must be above 30% [26].

Figure 5.8: Simulated output characteristics of Si Ge and Si channel devices1¡x x

(W/L=10¹m/1¹m).

Simulated dc output characteristics of Si Ge (x=0.3; W/L=10¹m/1¹m) de-1¡x x

vices are shown in ¯gure 5.8 for V = -2.0, -3.0 and -4.0 V. The drain current increasesG

(compared to control-Si) as the Ge content is increased because of the enhancement

of hole mobility [58]. The drain saturation current is found to be -1.56 mA and -3.23

mA for Si and SiGe (x=0.3), respectively, at V =-2.0 V and V =-4.0 V. The drainD G

saturation current is 107% higher than that of the Si devices in agreement with the

results of Sadovnikov et al. [234].

Figure 5.9 shows the Silvaco-ATLAS simulations of the e®ect of Ge fraction on

low-¯eld (V =-0.1 V) transconductance. The transconductance of Si Ge devicesD 1¡x x

is found to increase with Ge fraction and decreases more rapidly at a high transverse

¯eld compared to control-Si device [233]. In simulation, a structure such as described

110

ºin ¯gure 5.1(b) is used with a Si-cap thickness of 50 A and a Ge mole fraction of 20 %

and 30 %. A higher peak transconductance value in alloy layer as compared to that

of control-Si is attributed to reduced interband and intraband scattering of carriers

in the Si Ge channel.1¡x x

Figure 5.9: Comparison of simulated transconductance characteristics of a SiGe-

channel p-MOSFET and a Si p-MOSFET at V =-0.1 V.D

5.3.3 E®ect of SiGe-well and Si-cap Layer Thickness

1-D Poisson simulation results for the sheet concentration of holes in the Si-cap

and in the Si Ge well as a function of gate voltage for two di®erent well thicknesses1¡x x

º º(100 A and 300 A) are shown in ¯gure 5.10. The cross-over voltage increases nominally

with a decrease in well thickness. The peak transconductance is weakly dependent

on SiGe quantum well thickness as shown in ¯gure 5.11. The simulation results show

that the drive current is optimum when the SiGe layer thickness is in the range 100-

º300 A. When SiGe layer is thinner than the normal inversion layer thickness, the

Si layer beneath the SiGe layer cannot be inverted due to the Si/SiGe valence band

111

o®set. The SiGe-well looses some carriers, compared to the case of a thicker SiGe

Figure 5.10: Simulated hole distribution in the SiGe-channel as a function of gate

voltage with di®erent SiGe-well thicknesses.

Figure 5.11: Peak transconductance (g ) as a function of SiGe-well thicknessm

(W/L=10¹m/1¹m).

112

layer, and therefore, the drive current decreases. On the other hand, when the SiGe

layer is too thick, the average distance of inversion carriers from the gate becomes

larger, and again a smaller drive current results.

Figure 5.12: Simulated hole distribution in the buried channel (SiGe-well) and surface

channel (Si-cap) as a function of Si-cap layer thickness at a gate voltage (V =-2 V).G

Figure 5.12 presents the 1-D Poisson simulation results for hole density in the

Si Ge layer and in the Si-cap as a function of gate voltage for di®erent cap layer1¡x x

thicknesses. The hole density increases in the cap signi¯cantly with an increase in

cap layer thickness. The reduction of cap thickness greatly increases the carrier

concentration in the Si Ge channel. So, one way to increase the concentration1¡x x

of holes in the Si Ge layer over that in the Si-cap is to reduce the cap thickness1¡x x

as much as possible. This, however, cannot be done without limitations. The Si-

cap layer serves two purposes. First it con¯nes the carriers away from the Si/SiO2

interface helping reduced carrier scattering by the interface states. Secondly, good

quality SiO is grown by consuming a part of the Si-cap layer to prevent the Ge2

segregation on oxidation of SiGe alloy. So, the cap layer thickness has to be thick

enough to prevent Ge di®usion to Si/SiO growth interface during oxidation [235]. It2

is noted that a Si-cap layer grown epitaxially on the group-IV alloy layer gives low

113

interface state density as observed experimentally in Chapter 3.

ºIt is noted that a cap thickness of only 50 A is enough to support an inversion

layer, hence the charge screening problem will still be present in such a structure

[236]. Consequently, the device should be operated at low gate voltages where the

SiGe-channel dominates the device electrical characteristics. Figure 5.13 shows the

peak transconductance versus Si-cap layer thickness with di®erent oxide thicknesses.

The results were obtained using Silvaco-ATLAS device simulator. This ¯gure re-

veals that the transconductance decreases with increasing Si-cap layer thickness as a

consequence of the reduced hole population in the alloy layer.

Figure 5.13: Simulated peak transconductance (g ) as a function of Si-cap layerm

thickness (W/L=10¹m/1¹m).

To maximize the gate-to-channel capacitance and hence to increase the SiGe p-

MOSFET transconductance, it is important to minimize both the thickness of the Si-+ºcap and the gate oxide. For a Si-cap thickness below 30 A, the p -gate design becomes

+an attractive alternative to the n -gate SiGe p-MOSFETs. However, such a thin Si-

cap layer does not permit a thermal reoxidation of the source and drain areas after

ºthe poly-Si gates are etched. In addition, since the current °ows less than 30 A away

from the gate oxide, interface scattering will degrade the hole mobility. Conversely,

114

with a thin Si-cap, the holes in the SiGe-channel °ow closer to the gate and the

channel-to-gate capacitance increases. The Si-cap thickness needed to optimize the

transconductance is therefore determined by a mobility/capacitance trade-o®. The

potential improvements in device performance, in terms of carrier con¯nement and

gate-to-channel capacitance, make SiGe transistors with a thin Si-cap very attractive

for short-channel applications.

5.3.4 SiGe-channel p-MOSFETs with ±-doping Spike

In section 5.2, we have discussed the semi-analytical model to calculate the hole

distribution at the SiGe-channel and Si-cap with ±-doping spike. In this section,

we present the results of simulations using MOSFET structure with ±-doping spike.

The hole distribution in the Si-cap and SiGe-well for structures with and without

±-doping spike is shown in ¯gure 5.14. The potential at strong inversion is loosely

Figure 5.14: Comparison of hole densities in channel with and without ±-doping spike.

de¯ned by the condition, à =2à , where à is bulk Fermi potential in the Si-cap.s b b

The saturation of carriers in the well is due to potential shielding by the 2DHG at

the surface. For the case where à exceeds 2à , Q is approximately exponentiallys b cap

115

dependent on à . Hence an incremental increase in à by Á (thermal voltage) resultss s t

in a factor of e increase in surface inversion layer charges [232]. Consequently, any

Figure 5.15: Plot of electrostatic potentials and normalized C/C .ox

Figure 5.16: Areal electron density from analytical model.

116

small increase in à is o®set by a commensurate increase in Q , causing the wells cap

potential, Ã , to remain essentially constant. This explanation for carrier saturationw

in the well is borne out by ¯gure 5.15, which plots the electrostatic potentials, Ã ands

à , as a function of gate bias without ±-doping spike. The corresponding normalizedw

capacitance is shown in ¯gure 5.15. Although the hole distribution curves for both

with and without ±-doping spike appear similar from ¯gure 5.14, the di®erence lies

in the areal electron density in the Si-cap at low gate biases as shown in ¯gure+5.16. As expected, the structure with the p threshold adjust (±-doping spike) has a

signi¯cantly higher density of electrons near zero gate bias, leading to the conclusion

that a ±-doping spike would serve to improve the subthreshold characteristic and hole

mobility of SiGe-channel p-MOSFETs.

Figure 5.17: Simulated output characteristics of Si Ge devices with di®erent Ge1¡x x

concentration (W/L=10¹m/1¹m).

Figure 5.17 shows the simulated dc current-voltage (I-V) characteristics of Si Ge1¡x x

(with x= 0.3) devices for both with and without ±-doping spike at V = -2.0, -3.0G

and -4.0 V. The channel width `W' and length `L' of these transistors were 10 and

1 ¹m, respectively, and the potential of source and substrate was set at 0 V during

simulation. The drain current for structure with ±-doping spike increases compared

117

to a structure without ±-doping spike [237]. The saturation drain current of ±-doped

device is found to be -3.75 mA for 30% Ge at a drain voltage of -2.0 V and gate-

to-source voltage of -4.0 V. The drain current is about 141% higher compared to

control-Si devices (not shown). The Si Ge transistor with ±-doping spike exhibits0:7 0:3

a higher (33%) drive current at the same V (=-3.0 V) than control Si Ge devices.G 0:7 0:3

Subthreshold characteristics of Si Ge (x= 0.2 and 0.3) p-MOSFETs (with and1¡x x

without ±-doping spike) are shown in ¯gure 5.18. Subthreshold swings are found to

be 123, 112, and 112 mV/dec (102, 104 and 104 mV/dec) for 10%, 20% and 30%

Ge, respectively, with and without ±-doping spike. The corresponding value is 84

Figure 5.18: Subthreshold characteristics of Si Ge devices at V =-0.1 V1¡x x D

(W/L=10¹m/1¹m).

mV/decade for control-Si device. Subthreshold slope for SiGe p-MOSFETs is higher

compared to control-Si devices [233]. This is due to the fact that the buried channel

is less sensitive to gate control under weak inversion and possibly due to the higher

permittivity of Si Ge layers [224].1¡x x

Figure 5.19 shows the transconductance of Si Ge devices computed using silvaco-1¡x x

ATLAS simulator at a low ¯eld (V =-0.1 V). In simulation, a structure similar to oneD

ºdescribed in ¯gure 5.3 is used with a Si-cap thickness of 50 A and Ge mole fraction

118

of 10, 20 and 30%. It is found that an increase in Ge fraction increases the g ,m

Figure 5.19: Simulated transconductance characteristics of SiGe p-MOSFETs with

comparison between ±-doping spike and without ±-doping spike at V =-0.1 VD

(W/L=10¹m/1¹m).

Figure 5.20: Simulated threshold voltage and peak transconductance as a function of

Ge concentration.

119

when one compares two devices with and without a ±-doping spike. Figure 5.20 shows

the variation of threshold voltage and peak transconductance with Ge concentration.

The threshold voltage decreases and peak transconductance increases with increase

in Ge concentration for both the devices. The threshold voltage decreases rapidly

in ±-doping spike compared to that without ± doping. From the plot, it is seen that

the presence of a ±-doped layer is advantageous mainly in terms of threshold voltage

adjustment with slight improvement in peak transconductance.

5.4 SiGe-channel p-MOSFETs on SIMOX

Figure 5.21: Device structure of SiGe p-MOSFET on SIMOX

A SiGe-SIMOX device is similar to a SiGe p-MOSFET as shown in ¯gure 5.21

with the main distinctions being the presence of a buried oxide (thickness: 410 nm)

and a spacer layer (thickness: 160 nm) in the former. Figure 5.22 shows the computed

low frequency C-V characteristics of SiGe-SIMOX and SiGe-bulk structures for both+ +n - and p -poly Si gate using an 1-D Poisson solver. The kink in the curve, between

+ +gate biases of about 0 to -1.0 V for p -poly and -1.0 to -2.0 V for n -poly gate, is a

120

result of the hole con¯nement in the SiGe-well. The plateau in accumulation region

Figure 5.22: Low frequency capacitance-voltage (C-V) characteristic of SiGe-bulk and

SiGe-SIMOX devices with x=0.3 using 1-D Poisson solver.

Figure 5.23: Hole distribution in SiGe-bulk and SiGe-SIMOX.

121

for the SiGe-SIMOX structure extends to wider range of gate voltage when compared

to that for the SiGe-bulk structure. The improvement in hole con¯nement can also

be seen from the hole distributions in Si-cap layer and in buried well.

Figure 5.24: Drain current vs. drain voltage characteristics for SiGe-SIMOX and

SIMOX.

Figure 5.25: Subthreshold characteristics for SiGe-SiMOX and SIMOX devices with

channel length 1¹m.

122

In ¯gure 5.23, the simulated hole distribution as a function of band bending in

SiGe-SIMOX and SiGe-bulk devices is shown. For the SiGe-bulk, the same well and

gate oxide (as in SiGe-SIMOX) parameters are used, and the substrate doping is15 ¡3taken to be 5£10 cm . The hole concentration at the Si surface for the SiGe-

SIMOX is about 2 orders of magnitude lower than that for the SiGe-bulk device,

which means that the channel conduction through the parasitic surface channel (at

Si/SiO interface) is signi¯cantly diminished in SiGe-SIMOX due to reduced band2

bending at the surface. The reduced band bending also results in a more uniform

hole concentration in the SiGe-well for the SIMOX device.

Figure 5.24 compares the I-V characteristics of SIMOX devices made of Si and

SiGe at room temperature. All devices show the linear and saturation region. The

drain current of the SiGe-SIMOX device is 222% higher in saturation region compared

to that for the Si SIMOX device. This shows that the circuits built in SiGe-SIMOX

device will have potentially high speed due to the higher drive current. The turn-on

and turn-o® characteristics of a device is largely determined by the current drive as

well as the peak transconductance of the device. The improvement in drain current

of the SiGe-SIMOX device over that of the SIMOX device is signi¯cant.

The subthreshold characteristics of SiGe-SIMOX (x=0.2 and x=0.3) and SIMOX

devices have been simulated and the results are shown in ¯gure 5.25. The subthresh-

old slopes are found to be 125 (x=0.2) and 130 (x=0.3) mV/decade for SiGe-SIMOX

and 115 mV/dec for SIMOX devices, respectively. It has been found that the sub-

threshold slopes are 120 mV/dec (x=0.2) and 121 mV/dec (x=0.3) for SiGe-bulk. The

subthreshold slopes are higher in case of SiGe-SIMOX devices compared to SiGe-bulk

devices. The interface states at the front and back interfaces of the SOI layers can

contribute to this subthreshold degradation.

A large valence band discontinuity at the top Si/Si Ge heterointerface is es-1¡x x

sential to increase the hole population in the SiGe channel and ensure adequate

con¯nement up to a high gate voltage. The improved con¯nement with increased

Ge concentration (SiGe-SIMOX and SiGe-bulk devices) is illustrated in ¯gure 5.26,+where the n -gate MOSFET cross-over voltage has been plotted. The cross-over volt-

age is linearly proportional to the relative Ge concentration for both SiGe-SIMOX

and SiGe-bulk devices. A higher cross-over voltage is observed for SiGe-SIMOX de-

vices compared to SiGe-bulk devices. It is also observed that the cross-over voltage

123

increases with Ge concentration more rapidly in SiGe-SIMOX devices compared to

SiGe-bulk due to improved carrier con¯nement in the SiGe-SIMOX quantum wells.

+Figure 5.26: n -gate cross-over voltage versus Ge mole fraction for SiGe-bulk and

SiGe-SIMOX devices. No threshold voltage adjustment was done in these devices.

The ratio of holes in the Si-cap to the SiGe-channel for two di®erent gate voltages

(V =-1.5 V and -2.5 V) are plotted in ¯gure 5.26. As expected, more carriers °owG

in the Si-cap layer as the gate voltage rises. In order to ensure that the majority of

holes °ow in the SiGe-channel for gate voltages equal to or more negative than -2.5

V, the Ge concentration must rise above 30%. The ratio of holes in the Si-cap over

those in SiGe-channel are observed to be lower for SiGe-SIMOX devices compared to

SiGe-bulk devices.

A plot of linear transconductance (g ) vs. gate voltage (V ) for a 1 ¹m channelm G

length device at a low ¯eld (V =-0.1 V) is shown in ¯gure 5.27. The improvement inD

peak g for SiGe-SIMOX device over that of Si SIMOX is evident in this ¯gure. Them

g of SiGe-SIMOX is found to increase with increase of Ge fraction and decreasesm

rapidly at high transverse ¯elds. The shape of the transconductance curve for the

SiGe-SIMOX is slightly di®erent than that of the SIMOX device. The transconduc-

124

tance of the SIMOX device exhibits a well de¯ned peak near threshold, similar to a

bulk-Si device.

Figure 5.27: Comparison of linear transconductances of SiGe-SIMOX and Si SIMOX

devices (W/L=10¹m/1¹m).

In case of SiGe-SIMOX, three regions are observed in the transconductance char-

acteristics:

a) at low gate voltages (close to the threshold voltage, V ¼-1.0V), the e®ectiveG

capacitance is small (series combination of oxide capacitance and Si-cap layer capac-

itance) but the peak g is high because the holes are mainly con¯ned to the well.m

Therefore, the peak g as well as the channel mobility will be high.m

b) The peak g value remains nearly same for a range of gate voltages (V =-1.0m G

to -1.5V). As the gate voltage is above -1.0V, carriers start to build up at the surface

channel, and for these carriers the channel mobility is low due to increased Si/SiO2

surface scattering but the e®ective gate capacitance is high due to the ultrathin oxide

º(80 A). Hence, the net e®ective transconductance still remains high.

c) As V exceeds -1.5V, the peak transconductance falls rapidly with the carriersG

in the surface channel starts to dominate the total channel conduction. As the e®ective

125

¯eld becomes more negative, the surface channel turns-on and the transconductance

decreases rapidly. This type of transconductance behavior has been observed earlier

for SiGe p-MOSFETs on SOS [74].

Di®erent structures of the control layers apparently change the device character-

istics as well. Table 5.4 summarizes the dependence of the device parameters on the

Ge concentration, ±-doping spike and the SIMOX substrate. The major merit of the

proposed device is the large current driving capability. It is seen from the device sim-

ulation that the hole con¯nement in the well of a SiGe-SIMOX structure and SiGe

with ±-doping spike is better than that of a SiGe-bulk structure. The improvement

in drive current of a SiGe-SIMOX and ±-doped SiGe devices over that of control-Si

device is about 222% and 141%, respectively, for a Ge concentration of 30%.

Table 5.4: Device parameters for SiGe, SiGe with ±-doping spike and SiGe on SIMOX

substrate

+Parameters Si SIMOX SiGe p -doping spike SiGe-SIMOX18 3(x=0.3) 2£10 /cm (x=0.3)

Subthreshold slope 84 115 104 112 130

(mV/decade)

g (¹S/¹m) 4.63 6.78 27.1 28.06 30.57m

Drive current (mA) at -1.56 -1.6 -3.23 -3.75 -5.15

V =-2.0 V, V =-4.0 VD G

5.5 Summary

Design and simulation issues for advanced SiGe p-MOSFETs have been investi-

gated. Charge distribution in the Si-cap and SiGe-well of Si Ge buried channel1¡x x

MOS structures has been calculated using semi-analytical model and 1-D Poisson

solver. Semi-analytical model, 1-D Poisson solver and Silvaco-ATLAS tools have

been used to optimize the Si Ge channel p-MOSFETs device performance for the1¡x x

modulation-doped structure.

126

A summary of simulation and optimization results are presented below:

i) The use of a Si-cap, leads to a buried channel behavior in these heterostructure

devices, resulting in a performance penalty over control-Si devices. Cap layer should

be as thin as possible: just thick enough to keep the high mobility charges away from

the surface.

ii) Hole con¯nement is not very sensitive to the thicknesses of the SiGe-well.+iii) n -poly Si gate promotes buried channel operation for low voltage application.

iv) A high Ge concentration is necessary for a large hole population within the

SiGe-well to increase the transconductance.+v) p ±-doping spike below the SiGe-channel improves subthreshold properties

and may be used for threshold adjustment.

vi) SiGe-channel p-MOSFETs on SIMOX substrates have been analyzed using 2-D

simulator. It is observed that the SiGe-SIMOX device exhibits improved saturation

current drive and channel saturation transconductance over that of SiGe-bulk device.

These results illustrate the availability of new degrees of freedom in SiGe p-HFET

design by using modulation doping and SOI substrates.

127

Chapter 6

Conclusion

Heterostructures on Si using group-IV alloy layers have opened up new ¯elds of

applications in Si technology. The extensive use of these heterostructures would re-

quire the understanding of the electronic and physical properties such as band align-

ment, scattering mechanism, generation lifetime, carrier mobility as well as device

transconductance. For integration of these heterostructures in Si microelectronics,

an important requirement is to realize high quality ultrathin dielectrics using low

thermal budget processing.

In this work, a broad range of experiments have been performed to study the

characteristics of pseudomorphic SiGe and SiGeC epitaxial layers grown by MBE

and UHVCVD. The growth and characteristics of oxide and stacked oxynitride ¯lms

on strained SiGe and partially strain compensated SiGeC layers using microwave

plasma have been studied. The design and simulation of SiGe p-MOSFETs using

modulation-doped layer and SIMOX substrate have also been carried out.

6.1 Contributions

The major contributions of this work are:

² Device quality fully strained Si Ge and partially strained Si Ge C het-1¡x x 1¡x¡y x y

erolayers have been grown at low temperatures using MBE and UHVCVD. SIMS,

RBS, HRXRD and AFM have been used to study the ¯lm quality, strain state and

Ge and C pro¯le in the layer.

² High frequency capacitance-voltage characteristics of MOS capacitors have been

128

used to measure the apparent doping pro¯le and thickness of unconsumed Si-cap layer.

The hole con¯nement in SiGe/SiGeC well in a buried channel structure has been

demonstrated by C-V measurements and simulation of MOS capacitors. Measured

threshold voltages of SiGe and SiGeC heterolayers have been used to determine the

valence band o®set (¢E ) in type-I band alignment. The band o®set is found to bev

reduced on incorporation of C but with a rate much lower than predicted by linear

interpolation of band energies.

² Minority carrier generation lifetime measured using transient capacitance char-acteristics is found to be lower in partially strain compensated SiGeC ¯lms compared

to strained SiGe ¯lms showing the presence of C-induced localized trap centers in the

former.

º² The growth of ultrathin oxides (<100 A) on SiGeC layers at a low temperatureo(<200 C) using microwave O -plasma has been demonstrated for the ¯rst time. The2

use of a Si-cap layer on the alloy improves the electrical and interfacial properties of

the grown oxide.

² Growth of stacked oxynitride ¯lms on SiGe and SiGeC layers at a low temper-ature using combinations of O , NH and NO-plasma has been demonstrated. The2 3

role of nitrogen incorporation and its pro¯le on interfacial charge trapping and relia-

bility characteristics of plasma grown dielectrics has been studied. NO/O /NO and2

O /NH /NO-plasma grown stacked oxynitride ¯lms show superior quality in terms of2 3

electrical and interfacial properties as compared to oxide or oxynitrides grown using

a single step plasma process.

² The design methodology for SiGe-channel p-MOSFETs have been presented.The device behavior has been studied using 1-D Poisson solver, developed analytical

model and Silvaco-ATLAS simulator. The e®ect of gate material, Ge concentration

and pro¯le, Si-cap and gate oxide thicknesses on the MOSFET device characteris-

tics have been addressed. Enhancement of device performance has been predicted

when one uses modulation-doped layer and SIMOX substrate. The improvement in

drive current for SiGe-SIMOX and ±-doped devices are found to be 222% and 141%,

respectively, over that of control Si devices for a Ge concentration of 30%.

6.2 Suggestions for Future Work

Although the present dissertation reports a detailed study on the di®erent tech-

129

niques used for the growth of ultrathin dielectrics on strained Si Ge and partially1¡x x

strain compensated Si Ge C layers using microwave plasma at a low tempera-1¡x¡y x y

ture, several important aspects as mentioned below could not be taken up and are

worth further investigating:

² growth mechanism and kinetics in plasma oxidation of SiGe and SiGeC layers,

² e®ect of Ge and C concentration on the growth rate and its modeling,² depth pro¯le of N incorporated ¯lms on SiGe and SiGeC layers,² e®ect of source, drain and gate engineering on SiGe p-MOSFETs using modulation-

doped layer and SIMOX substrate, and

² cut-o® frequency of SiGe p-MOSFETs using modulation-doped layer and SIMOXsubstrate.

130

Bibliography

[1] \National Technology Roadmap for Semiconductors," Semiconductor Industry

Association, San Jose, USA, 1997.

[2] P. K. Ko, \Approaches to scaling in advanced MOS device physics," Academic

Press, 1989.

[3] E. Kasper and H. J. Herzog, \Elastic strain and mis¯t dislocation density in

Si Ge ¯lms on Si substrate," Thin Solid Film., vol. 44, p. 357, 1977.0:92 0:08

[4] R. Hull and J. C. Bean, \Mis¯t dislocations in lattice-mismatched epitaxial

¯lms," Crit. Rev. in Solid-State and Mat. Sci., vol. 17, pp. 507{546, 1992.

[5] F. C. Frank and J. H. Van der Merwe, \One dimensional dislocations, part II.

Mis¯tting monolayers and oriented over growth," Proc. Roy. Soc., vol. A198,

pp. 216{225, 1949.

[6] J. H. van der Merwe , \Crystal interfaces, part II. Finite overgrowths," J. Appl.

Phys. , vol. 34, pp. 123{127 (see also Erratum p. 3420, (1963)), 1963.

[7] J. W. Matthews and A. E. Blakeslee, \Defects in epitaxial multilayers, part-I.

Mis¯t dislocations," J. Crystal Growth, vol. 27, pp. 118{125, 1974.

[8] J. W. Matthews, \Defects associated with the accommodation of mis¯t between

crystals," J. Vac. Sci. Technol., vol. 12, pp. 126{133, 1975.

[9] J. C. Bean, L. C. Feldman, A. T. Fiory, S. Nakahara, and I. K. Robinson,

\Ge Si /Si strained layer superlattice growth by molecular beam epitaxy,"x 1¡x

J. Vac. Sci. Technol. A, vol. 2, pp. 436{440, 1984.

[10] R. People and J. C. Bean, \Calculations of critical layer thickness versus lattice

mismatch for Ge Si /Si strained-layer heterostructures," Appl. Phys. Lett.,x 1¡x

vol. 47, pp. 322{324, 1985.

131

[11] E. Kasper, \Growth and properties of Si/SiGe superlattices," Surface Sci.,

vol. 174, p. 630, 1986.

[12] R. People, \Physics and applications of Ge Si /Si strained layer heterostruc-x 1¡x

tures," IEEE J. Quantum Elec., vol. QE-22, pp. 1696{1710, 1986.

[13] K. Eberl, S. S. Iyer, S. Zollner, J. C. Tsang, and F. K. LeGoues, \Growth and

strain compensation e®ects in the ternary Si Ge C alloy system," Appl.1¡x¡y x y

Phys. Lett., vol. 60, pp. 3033{3035, 1992.

[14] A. St. Amour, L. D. Lanzerotti, C. L. Chang, and J. C. Sturm, \Optical and

electrical properties of Si Ge C thin ¯lms and devices," Thin Solid Film.,1¡x¡y x y

vol. 294, pp. 112{117, 1997.

[15] I. Balslev, \In°uence of uniaxial stress on the indirect absorption edge in silicon

and germanium," Phys. Rev., vol. 143, pp. 636{647, 1966.

[16] R. People and J. C. Bean, \Band alignments of coherently strained Ge Si /Six 1¡x

heterostructures on < 001 > Ge Si substrates," Appl. Phys. Lett., vol. 48,y 1¡y

pp. 538{540, 1986.

[17] D. V. Lang, R. People, J. C. Bean, and A. M. Sergent, \Measurement

of bandgap Ge Si /Si strained-layer heterostructures," Appl. Phys. Lett.,x 1¡x

vol. 47, pp. 1333{1335, 1985.

[18] J. M. Hinckley and J. Singh, \Hole transport theory in pseudomorphic in

strained Si Ge alloys grown on Si(001) substrates," Phys. Rev. B, vol. 41,1¡x X

pp. 2912{2926, 1990.

[19] T. Manku and A Nathan, \Energy band structure for strained p-type Si Ge ,"1¡x x

Phys. Rev. B, vol. 43, pp. 12634{12637, 1991.

[20] C. K. Maiti, L. K. Bera and S. Chattopadhyay, \Strained-Si heterostructure

¯eld e®ect transistors," Semicond. Sci. Technol., vol. 13, pp. 1225{1246, 1998.

[21] C. G. van de Walle and R. M. Martin, \Theoretical calculations of heterojunc-

tion discontinuities in the Si/Ge system," Phys. Rev. B, vol. 34, pp. 5621{5634,

1986.

132

[22] W. X. Ni and G. V. Hansson, \Band o®sets in pseudomorphically grown Si/SiGe

heterostructures studied with core-level x-ray photoelectron spectroscopy,"

Phys. Rev. B, vol. 42, pp. 3030{3037, 1990.

[23] S. P. Voinigescu, K. Iniewski, R. Lisak, C. A. T. Salama, J. P. Noel and D.

C. Houghton, \New technique for the characterization of Si/SiGe layers using

heterostructure MOS capacitors," Solid-State Electron., vol. 37, pp. 1491{1501,

1994.

[24] O. Chretien, R. Apetz, A. Sou¯ and L. Vescan, \Si Ge /Si valence band o®set1¡x x

determination using current-voltage characteristics," Thin Soild Film., vol. 294,

pp. 198{200, 1997.

[25] S. Takagi, J. L. Hoyt, K. Rim, J. J. Welser and J. F. Gibbons, \Evaluation of the

valence band discontinuity of Si/Si Ge /Si heterostructures by application1¡x x

of admittance spectroscopy to MOS capacitors," IEEE Trans. Electron Dev.,

vol. 45, pp. 494{501, 1998.

[26] S. Maikap, L. K. Bera, S. K. Ray, S. John, S. K. Banerjee and C. K. Maiti,

\Electrical characterization of Si/Si Ge /Si quantum well heterostructures1¡x x

using a MOS capacitor," Solid-State Electron., vol. 44, pp. 1029{1034, 2000.

[27] H. J. Osten, \Supersaturated carbon in silicon and silicon/germanium alloys,"

Mat. Sci. Engr., vol. B36, pp. 268{274, 1996.

[28] R. A. Soref, \Optical band gap of the ternary semiconductor Si Ge C ,"1¡x¡y x y

J. Appl. Phys., vol. 70, pp. 2470{2472, 1991.

[29] P. Boucaud, C. Francis, F. H. Julien, J.-M. Lourtioz, and D. Bouchier, S. Bod-

nar, B. Lambert, and J. L. Regolini , \Band-edge and deep level photolumi-

nescence of pseudomorphic Si Ge C alloys," Appl. Phys. Lett., vol. 64,1¡x¡y x y

pp. 875{877, 1994.

[30] A. S. Amour, C. W. Liu, J. C. Sturm, Y. Lacroix, and M. L. W. Thewalt,

\Defect-free band-edge photoluminescence and band gap measurement pseudo-

morphic Si C alloy layers on Si ," Appl. Phys. Lett., vol. 67, pp. 3915{3917,1¡y y

1995.

133

[31] C. L. Chang, A. St. Amour and J. C. Sturm, \E®ect of carbon on the va-

lence band o®set of Si Ge C /Si heterojunctions," IEEE IEDM Tech. Dig.,1¡x¡y x y

pp. 257{260, 1996.

[32] F. K. Legoues, R. Rosenberg and B. S. Meyerson, \Kinetics and mechanism

of oxidation of SiGe: dry versus wet oxidation," Appl. Phys. Lett., vol. 54,

pp. 644{646, 1989.

[33] S. J. Kilpatrick, R. J. Jaccodine and P. E. Thompson, \A di®usion model for the

oxidation behavior of Si Ge alloys," J. Appl. Phys., vol. 81, pp. 8018{8028,1¡x x

1997.

[34] A. E. Bair, Z. Atzmon, T. L. Alford, D. J. Smith, \Wet oxidation of amorphous

Si Ge C grown on (100) Si substrates ," J. Appl. Phys., vol. 83, pp. 2835{0:67 0:25 0:08

2841, 1998.

[35] S. Kar and P. Zaumseil, \Characteristics of ultrathin (4-7 nm) gate oxides for

SiGe quantum well MOS structures," Microelectron. Engg., vol. 48, pp. 83{86,

1999.

[36] Y. H. Wu and A. Chin, \Gate oxide integrity of thermal oxide grown on high

temperature formed Si Ge ," IEEE Electron. Dev. Lett., vol. 21, pp. 113{0:3 0:7

115, 2000.

[37] L. K. Bera, W. K. Choi, W. Feng, C. Y. Yang and J. Mi, \Electrical properties of

rapid thermal oxides on Si Ge C ," Appl. Phys. Lett., vol. 77, pp. 256{258,1¡x¡y x y

2000.

[38] D. K. Nayak, K. Kamjoo, J. S. Park, J. C. S. Woo, and K. L. Wang, \Rapid

isothermal processing of strained GeSi layers," IEEE Trans. Electron Dev.,

vol. 39, pp. 56{62, 1992.

[39] J. Nulman, J. P. Krusius, and A Gat , \Rapid thermal processing of thin gate

dielectrics: oxidation of silicon," IEEE Electron Dev. Lett., vol. 6, pp. 205{207,

1985.

[40] K. K. Ng and J. R. Ligenza, \The mechanism of plasma oxidation on °oating

silicon substrates," J. Electrochem. Soc., vol. 131, pp. 1968{1970, 1984.

134

[41] S. K. Ray, C. K. Maiti, and N. B. Chakrabarti, \Low temperature oxidation

of silicon in microwave oxygen plasma," J. Mat. Sci., vol. 25, pp. 2344{2348,

1990.

[42] C. Saha, S. K. Ray and S. K. Lahiri, \Ion-assisted low-temperature oxidation

of strained Si Ge and Si Ge C ¯lms," Semicond. Sci. Technol., vol. 14,1¡x x 1¡x¡y x y

pp. 984{987, 1999.

[43] J. M. Madsen, Z. Cui and C. G. Takoudis, \Low temperature oxidation of SiGe

in ozone: Ultrathin oxides," J. Appl. Phys., vol. 87, pp. 2046{2051, 2000.

[44] L. C. Feldman, E. P. Gusev, E. Garfunkel, in: E. Garfunkel, E. P. Gusev, A.

Vul'(Eds.), \Fundamental aspects of ultrathin dielectrics on Si-based devices,"

Kluwer Academic Publishers, Dordrecht, p. 1, 1998.

+[45] Y. Wu and G. Lucovsky, \Ultrathin nitride/oxide (N/O) gate dielectrics for p -

polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced

CVD/thermal oxidation process," IEEE Electron Dev. Lett., vol. 19, pp. 367{

369, 1998.

[46] T. Mizokura, K. Yoneda, Y. Todokoro and H. Kobayashi, \Mechanism of low

temperature nitridation of silicon oxide layers by nitrogen plasma generated by

low energy electron impact," J. Appl. Phys., vol. 85, pp. 2921{2928, 1999.

[47] J. Ushio, T. Maruizumi and M. Miyao, \Incorporation of N into Si/SiO in-2

terfaces: Molecular orbital calculations to evaluate interface strain and heat of

reaction," Appl. Phys. Lett., vol. 75, pp. 680{682, 1999.

[48] Q. W. Ren, L. K. Nanver, C. R. de Boer, and H. W. van Zeijl, \Silicon nitride as

dielectric in the low temperature SiGe HBT processing," Microelectron. Engg.,

vol. 36, pp. 179{182, 1997.

[49] V. K. Bhat, K. N. Bhat, and A. Subrahmanyam, \E®ect of post-oxidation

annealing of the oxynitride on the C-V and G-V characteristics of Al/thin

oxynitride/n-Si tunnel diodes," Semicond. Sci. Technol., vol. 15, pp. 883{887,

2000.

[50] I. J. R. Baumvol, \Atomic transport during growth of utrathin dielectrics on

silicon," Surf. Sci. Rep., vol. 36, pp. 1{166, 1999.

135

[51] G. D. Leonarduzzi and D. L. Kwong, \Improving performance with oxynitride

gate dielectrics," Semicond. Int'l, pp. 225{230, 1998.

[52] S. Maikap, L. K. Bera, S. K. Ray and C. K. Maiti, \NO/O /NO plasma grown2

oxynitride ¯lms on strained-Si Ge ," Electron. Lett., vol. 35, pp. 1202{1203,1¡x x

1999.

[53] T. K. Carns, S. K. Chun, M. O. Tanner, K. L. Wang, T. I. Kamins, J. E. Turner,

D. Y. C. Lie, M.-A. Nicolet, and R. G. Wilson, \Hole mobility measurements

in heavily doped Si Ge strained layers," IEEE Trans. Electron Dev., vol. 41,1¡x x

pp. 1273{1281, 1994.

[54] H. J. Osten and P. Gaworzewski, \Charge transport in strained Si C and1¡y y

Si Ge C alloys on Si(001)," J. Appl. Phys., vol. 82, pp. 4977{4981, 1997.1¡x¡y x y

[55] R. Duschl, H. Seeberger and K. Eberl, \Hole mobilities in pseudomorphic

Si Ge C alloy layers," Thin Solid Film., vol. 336, pp. 336{339, 1998.1¡x¡y x y

[56] G. S. Kar, A. Dhar, S. K. Ray, S. John and S. K. Banerjee, \Hall mobilities in

B-doped strained Si Ge and Si Ge C layers grown by ultrahigh vacuum1¡x x 1¡x¡y x y

chemical vapor deposition," J. Appl. Phys., vol. 88, pp. 2039{2042, 2000.

[57] K. B. Joelsson, Y. Fu, W.-X. Ni, and G. V. Hansson, \Hall factor and drift

mobility for hole transport in strained Si Ge alloys," J. Appl. Phys., vol. 81,1¡x x

pp. 1264{1269, 1997.

[58] S. K. Ray, S. John, S. Oswal and S. K. Banerjee, \Novel SiGeC channel hetero-

junction PMOSFET," IEEE IEDM Tech. Dig., pp. 261{264, 1996.

[59] D. K. Nayak, J. C. S. Woo, J. S. Park, K.-L. Wang, and K. P. MacWilliams,

\Enhancement-mode quantum-well Ge Si PMOS," IEEE Electron Dev.x 1¡x

Lett., vol. 12, pp. 154{156, 1991.

[60] P. M. Garone, V. Venkataraman and J. C. Sturm, \Hole mobility enhancement

in MOS-gated Ge Si /Si heterostructure inversion layers," IEEE Electronx 1¡x

Dev. Lett., vol. 13, pp. 56{58, 1992.

[61] N.-I. Cho, S.-Y. Oh and H. G.-Nam, \Substrate engineering analysis of ±-doped

Si Ge p-MOSFET transistors ," Electron. Lett., vol. 32, pp. 2355{2357, 1996.0:8 0:2

136

[62] B.K Ip and J.R Brews, \Design tradeo® guidelines for n- channel delta-doped

Si/SiGe heterojunction MOSFETs," Solid-State Electron., vol. 44, pp. 593{604,

2000.

[63] M. Miyake.., \Subhalf-micron p-channel MOSFET with 3.5 nm gate oxide fab-

ricated using X-ray lithography," IEEE Electron Dev. Lett., vol. 8, pp. 266{168,

1987.

[64] P. W. Li, E. S. Yang, Y. F. Yang, J. O. Chu, and B. S. Meyerson, \SiGe

pMOSFET's with gate oxide fabricated by microwave electron cyclotron res-

onance plasma processing," IEEE Electron Dev. Lett., vol. 15, pp. 402{405,

1994.

[65] J. A. Scott, E. T. Croke and J. D. Plummer, \High mobility Si Ge PMOS1¡x x

transistors to 5K," J. de Phys. IV, vol. 4, pp. 66{69, 1994.

[66] H. J. Huang, K. M. Chen, C. Y. Chang, L. P. Chen, G. W. Huang and T. Y.

Huang, \Reduction of source/drain series resistance and its impact on device

performance for PMOS transistors with raised Si Ge source/drain," IEEE1¡x x

Trans. Electron. Dev., vol. 21, pp. 448{450, 2000.

[67] S. Okhonin, M. A. Py, B. Georgescu, H. Fischer and L. Risch, \DC and low-

frequency noise characteristics of SiGe p-channel FET's designed for 0.13 ¹m

technology," IEEE Trans. Electron Dev., vol. 46, pp. 1514{1517, 1999.

[68] S. V. Vandebroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J.

M. C. Stork and J. B. Johnson, \SiGe-channel heterojunction p-MOSFET's,"

IEEE Trans. Electron Dev., vol. 41, pp. 90{100, 1994.

[69] W. Lu, S. J. Koester, X. W. Wang, J. O. Chu, T. P. Ma and I. Adesida,

\Comparative study of self-aligned and nonself-aligned SiGe p-metal -oxide-

semiconductor modulation doped ¯eld e®ect transistors with nano- meters gate

lengths ," J. Vac. Sci. Technol. B, vol. 18(6), pp. 3488{3492, 2000.

[70] S.L Wu and S.J Chang, \High performance ±-modulation-doped Si/SiGe het-

rostructure FET's grown by MBE," Solid-State Electron., vol. 43, pp. 1313{

1316, 1999.

137

[71] R. H. Yan, A. Qurmazd, and K. F. Lee, \Scaling the Si MOSFET: from bulk

to SOI to bulk," IEEE Trans. Electron Dev., vol. 39, pp. 1704{1710, 1992.

[72] A. Kranti, S. Haldar, and R. S. Gupta, \Temperature-dependent threshold

voltage analysis of surrounding cylindrical gate fully depleted thin ¯lm SOI

MOSFET in the range 77 to 520 K," Microelectron. Engg., vol. 49, pp. 273{

286, 1999.

[73] D. K. Nayak, J. S. Park, K. L. Wang and K. P. MacWilliams , \Hole con¯nement

in a Si/GeSi/Si quantum well on SIMOX," IEEE Trans. Electron Dev., vol. 43,

pp. 180{182, 1996.

[74] S. J. Mathew, G. Niu, W. B. Dubbelday and J. D. Cressler, \Characterization

and pro¯le optimization of SiGe pFET's on silicon-on-sapphire," IEEE Trans.

Electron Dev., vol. 46, pp. 2323{2332, 1999.

[75] M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato and

H. Tango, \Two dimensional simulation and measurement of high-performance

MOSFET's made on a very thin SOI ¯lm," IEEE Trans. Electron Dev., vol. 36,

pp. 493{503, 1989.

[76] D. K. Nayak, N. Usami, S. Fukatsu, and Y. Shiraki, \Photoluminescence study

of the optical properties of SiGe quantum wells on separation by implanted

oxygen substrates," J. Appl. Phys., vol. 81, pp. 3484{3489, 1997.

[77] E. T. Yu. E. T. Croke and T. C. Mcgill, \Measurement of the valence-band o®set

in strained Si/Ge(100) heterojunctions by x-ray photoelectron spectroscopy,"

Appl. Phys. Lett. , vol. 56, pp. 569{571, 1990.

[78] K. Nauka, T. I. Kamins, J. E. Turner, C. A. King, J. L. Hoyt and J. F. Gibbons,

\Admittance spectroscopy measurements of band o®sets in Si/Si Ge /Si het-1¡x x

erostructures," Appl. Phys. Lett., vol. 60, pp. 195{197, 1992.

[79] F. Lu, J. Jiang, H. Sun, D. Gong, and X. Wang, \Single-frequency admittance

spectroscopy measurement of band o®set in a Si/Si Ge /Si quantum well ,"1¡x x

J. Appl. Phys., vol. 75, pp. 2957{2962, 1994.

[80] J. C. Brighten, I. D. Hawkins, A. R. Peaker, E. H. C. Parker, and T. E. Whall,

\The determination of valence band discontinuities in Si/Si Ge /Si hetero-1¡x x

138

junctions by capacitance-voltage techniques," J. Appl. Phys., vol. 74, pp. 1894{

1899, 1993.

[81] K. Rim, S. Takagi, J. J. Welser, J. L. Hoyt and F. Gibbons, \Capacitance-

voltage characteristics of p-Si/SiGeC MOS capacitors," Mat. Res. Soc. Symp.

Proc., vol. 379, pp. 327{332, 1995.

[82] H. J. Osten, \Band-gap changes and band o®sets for ternary Si Ge C1¡x¡y x y

alloys on Si(001)," J. App. Phys., vol. 84, pp. 2716{2721, 1998.

[83] J. Kolodzey, F. Chen, B. A. Orner, D. Guerin and S. I. Shah , \Energy band

o®sets of SiGeC heterojunctions," Thin Solid Film., vol. 302, pp. 201{203, 1997.

[84] C. L. Chang, L. P. Rokhinson and J. C. Sturm, \Direct optical measurement+ ¡of the valence band o®set of p Si Ge C /P Si(100) by heterojunction in-1¡x¡y x y

ternal photoemission," Appl. Phys. Lett. , vol. 73, pp. 3568{3570, 1998.

[85] H. J. Osten, E. Bugiel and P. Zaumseil, \Growth of an inverse tetragonal dis-

torted SiGe layer on Si (001) by adding small amounts of carbon," Appl. Phys.

Lett., vol. 64, pp. 3440{3442, 1994.

[86] J. P. Liu and H. J. Osten, \Substitutional carbon incorporation during

Si Ge C growth on Si (100) by molecular beam epitaxy: Dependence on1¡x¡y x y

germanium and carbon," Appl. Phys. Lett., vol. 76, pp. 3546{3548, 2000.

[87] T. Akane, M. Sano, H. Okumura, Y. Tubo, T. Ishikawa, and S. Mat-

sumoto, \Characterization of gas-source molecular beam epitaxial growth of

strain-compensated Si Ge C /Si (100) heterostructure," J. Crystal Growth,1¡x¡y x y

vol. 203, pp. 80{86, 1999.

[88] B. S. Mayerson, K. E. Ismail, D. L. Harame, F. K. Legoues, and J. M. C.

Stork, \UHVCVD growth of Si/SiGe heterostructures and their applications,"

Semicond. Sci. Technol., vol. 9, p. 2005, 1994.

[89] M. L. Green, B. E. Weir, D. Brasen, W. F. Hsieh, G. Higashi, A. Feygenson,

L. C. Feldman, and R. L. Headrick, \Mechanically and thermally stable Si-Ge

¯lms and heterojunction ¯lms and heterojunction bipolar transistors grown byorapid thermal chemical vapour deposition at 900 C," J. Appl. Phys., vol. 69,

pp. 745{751, 1991.

139

[90] P. Garone, J. C. Sturm, P. V. Schartz, S. A. Schwartz, and B. J. Wilkens ,

\Silicon vapor phase epitaxial growth catalysis by the presence of germane,"

Appl. Phys. Lett., vol. 56, pp. 1275{1277, 1990.

[91] J. Hoyt, C. A. King, D. B. Noble, C. M. Gronet, and J. F. Gibbons, \Limited re-

action processing: Growth of Si Ge /Si for heterojunction bipolar transistor1¡x x

applications," Thin Solid Film., vol. 184, pp. 93{106, 1990.

[92] M. L. Green, D. Brasen, H. Temkin, R. D. Yadvish, T. Boone, L. C. Feldman,

M. Geva, and B. E. Spear, \High gain Si-Ge heterojunction bipolar transistors

grown by rapid thermal chemical vapour deposition," Thin Solid Film., vol. 184,

pp. 107{111, 1990.

[93] J. Mi, P. Warren, M. Gailhanou, J.-D. Ganiere, M. Dutoit, P.-H. Jouneau, and

R. Houriet, \Epitaxial growth of Si Ge C alloy layers on (100) Si by rapid1¡x¡y x y

thermal chemical vapor deposition using methylsilane," J. Vac. Sci. Technol.

B, vol. 14, pp. 1660{1669, 1996.

[94] C. W. Liu, Y. D. Tseng and Y. S. Huang, \Substitutional carbon reduction in

SiGeC alloys grown by rapid thermal chemical vapor deposition," Appl. Phys.

Lett., vol. 75, pp. 2271{2273, 1999.

[95] Z. Atzmon, A. E. Bair, E. J. Jaquez, J. W. Mayer, D. Chandrasekhar D. J.

Smith, R. L. Hervig, M. D. Robinson, \Chemical vapor deposition of heteroepi-

taxial Si Ge C ¯lms on (100)Si substrates," Appl. Phys. Lett., vol. 65,1¡x¡y x y

pp. 2559{2561, 1994.

[96] J. W. P. Hsu, E. A. Fitzgerald, Y. H. Xie, P. J. Silverman, and M. J. Cardillo,

\Surface morphology of relaxed Ge Si ¯lms," Appl. Phys. Lett., vol. 61,x 1¡x

pp. 1293{1295, 1992.

[97] J. W. Strane, H. J. Stein, S. R. Lee, B. L. Doyle, S. T. Picraux and J. W. Mayer,

\Metastable SiGeC formation by solid phase epitaxy," Appl. Phys. Lett., vol. 63,

pp. 2786{2788, 1993.

[98] E. Finkman, P. Boucad, J. Boulmer, G. Guedj, D. Bouchier, S. Prawer, and K.

Nugeni, \Raman spectroscopy of Si Ge C layers obtained by pulsed laser1¡x¡y x y

induced epitaxy," Appl. Surf. Sci., vol. 106, pp. 171{178, 1996.

140

[99] S. Fukatsu, H. Yoshida, A. Fujiwara, Y. Takahashi, and Y. Shiraki, \Spectral

blue shift of photoluminescence in strained layer Si Ge /Si quantum well1¡x x

structures grown by gas source Si MBE," Appl. Phys. Lett., vol. 61, pp. 804{

806, 1992.

[100] Y. Kato, S. Fukatsu, and Y. Shiraki, \Post growth of a Si contact layer on

air exposed Si Ge /Si single quantum well grown by gas source molecular1¡x x

beam epitaxy, for use in an electroluminescent device," J. Vac. Sci. Technol.,

vol. B13, pp. 111{117, 1995.

[101] M. Fatemi and R. E. Stahlbush, \X-ray rocking curve measurement of compo-

sition and strain in Si-Ge bu®er layers grown on Si substrates," Appl. Phys.

Lett., vol. 58, pp. 825{827, 1991.

[102] A. C. Diebold and B. Doris, \A survey of non-destructive surface character-

ization methods used to insure reliable gate oxide fabrication for silicon IC

devices," Surf. Interface Analysis, vol. 20, pp. 127{139, 1993.

[103] G. S. Kar, S. K. Ray, T. Kim, S. K. Banerjee, and N. B. Chakrabarti, \Es-

timation of hole mobility in strained Si Ge buried channel heterostructure1¡x x

p-MOSFET," Solid-State Electron., vol. 45, pp. 669{676, 2001.

[104] P. M. Garone, V. Venkataraman and J. C. Sturm, \Hole con¯nement in MOS-

gated Ge Si /Si heterostructures," IEEE Electron Dev. Lett., vol. 12, p. 230,x 1¡x

1991.

[105] K. Bhaumik and Y. S. Diamand, \Semi-analytical model for charge control in

SiGe quantum well MOS structures," Solid-State Electron., vol. 36, pp. 961{968,

1993.

[106] M. Y. A. Yousif, O. Chretien, O. Nur and M. Willander, \Short-channel ef-

fects in Si/Si Ge retrograde double quantum well p-MOSFETs," Solid State1¡x x

Electron., vol. 43, pp. 969{976, 1999.

[107] K. Iniewski, S. Voinigescu, J. Atcha and C. A. T. Salama, \Analytical model-

ing of threshold voltages in p-channel Si/SiGe/Si MOS structures," Solid-State

Electron., vol. 36, pp. 775{783, 1993.

141

[108] W.-X. Ni, J. Knall and G. V. Hansoon, \New method to study band o®sets

applied to strained Si/Si Ge (100) heterojunction interfaces," Phys. Rev. B,1¡x x

vol. 36, pp. 7744{7747, 1987.

[109] P. J. Wang, F. F. Fang, B. S. Meyerson, J. Nocera and B. Parker, \Two-

dimensional hole gas in Si/Si Ge /Si modulation-doped double heterostruc-0:85 0:15

tures," Appl. Phys. Lett., vol. 54, pp. 2701{2703, 1989.

[110] S. S. Iyer, G. L. Patton, J. M. C. Stork, B. S. Meyerson and D. L. Harame,

\Heterojunction bipolar transistors using Si-Ge alloys," IEEE Trans. Electron

Dev., vol. 36, pp. 2043{2064, 1989.

[111] C. A. King, J. L. Hoyt and J. F. Gibbons, \Bandgap and transport properties

of Si Ge by analysis of nearly ideal Si/Si Ge /Si heterojunction bipolar1¡x x 1¡x x

transistors," IEEE Trans. Electron Dev., vol. 36, pp. 2093{2104, 1989.

[112] C. H. Gan, J. A. del Alamo, B. R. Bennett, B. S. Meyerson, E. F. Crabbe, C. G.

Sodini, and L. R. Reif, \Si/Si Ge valence band discontinuity measurements1¡x x

using a semiconductor-insulator-semiconductor (SIS) heterostructure," IEEE

Trans. Electron Dev., vol. 41, pp. 2430{2439, 1994.

[113] B. L. Stein, E. T. Yu, E. T. Croke, A. T. Hunter, T. Laursen, A. E. Bair, J.

W. Mayer and C. C. Ahn, \Band o®sets in Si/Si Ge C heterojunctions1¡x¡y x y

measured by admittance spectroscopy," App. Phys. Lett., vol. 70, pp. 3413{

3415, 1997.

[114] S.-H. Hwang, Y.-P. Eo, J.-H. Seo, K.-W. Whang, E. Yoon and H.-S. Tae, \Non-

contact minority carrier lifetime measurement of Si and SiGe epilayers prepared

by ultrahigh vacuum cyclotron resonance chemical vapor deposition," J. Vac.

Sci. Technol. A, vol. 14, pp. 1033{1036, 1996.

[115] R. Sorge, \Non-quasistatic simultaneous HF/LF-CV measurements for rapid

characterization of MOS structures," Solid-State Electron., vol. 42, pp. 761{

770, 1998.

[116] T. Mohacsy, N. Q. Khanh, M. Adam and J. Gyulai, \Modi¯ed C-t technique+for determining the generation lifetime pro¯le in MeV He implanted silicon,"

Vacuum, vol. 50, pp. 399{401, 1998.

142

[117] A. Ahaitouf, E. Losson and J. P. Charles, \A new determination of minority

carrier generation characteristics in a MOS channel-CCD process by DLTS,"

Solid-State Electron., vol. 43, pp. 1225{1230, 1999.

[118] M. Zerbst and Z. Angew Physik, vol. 22, p. 30, 1966.

[119] P. V. Schwartz and J. C. Sturm, \Microsecond carrier lifetimes in strained

silicon-germanium alloys grown by rapid thermal chemical vapor deposition,"

Appl. Phys. Lett., vol. 19, pp. 2004{2006, 1990.

[120] R. Shivaram, G. Niu, J. D. Cressler and E. T. Croke, \The e®ect of carbon+content on the minority carrier lifetime in lattice-matched p -Si/p-SiGeC/n-

+Si/n -Si diodes," Solid-State Electron., vol. 44, pp. 559{563, 2000.

[121] I. Ban, M. C. Ozturk, K. Christensen and D. M. Maher, \E®ects of carbon im-

plantation on generation lifetime in silicon," Appl. Phys. Lett., vol. 68, pp. 499{

501, 1996.

[122] G. Lippert, H. J. Osten, K. Blum, R. Sorge, P. Schley, D. Kruger and G. Fischer,

\Optimized processing for di®erentially moleculer beam epitaxy-grown SiGe(C)

devices," Thin Solid Film., vol. 321, pp. 21{25, 1998.

[123] T. Changhua, X. Mingzhen and H. Yandong, \Application of the proportional

di®erence time analysis to study carrier generation rate in MOS structures,"

Solid-State Electron., vol. 42, pp. 369{377, 1998.

[124] L. S. Riley, S. Hall and J. M. Bonar, \The separation of generation lifetimes

of Si and SiGe using capacitance-transient measurements on MOS capacitors

formed by plasma anodization of Si:Si Ge :Si substrates," Solid-State Elec-0:9 0:1

tron., vol. 43, pp. 2247{2250, 1999.

[125] F. J. Grunthaner and J. Maserjian, \Chemical structure of the transitional

region of the Si/SiO interface: in the physics of SiO and its interface," Per-2 2

gramon Press, Elmsford, New York, 1978.

[126] F. J. Grunthaner, B. F. Lewis, N. Zamini and J. Maserjian, \XPS studies of

structure induced radiation e®ects at the Si/SiO interface," IEEE Trans Nucl.2

Sci., vol. NS-27, pp. 1640{1646, 1980.

143

[127] E. Kobeda and E. A. Irene, \SiO ¯lm stress distribution during thermal oxi-2

dation of Si," J. Vac. Sci. Technol., vol. B6, pp. 574{578, 1988.

[128] D. K. Nayak, K. Kamjoo, J. S. Park, J. C. S. Woo and K. L. Wang, \Wet

oxidation of GeSi strained layers by rapid thermal processing," Appl. Phys.

Lett., vol. 57, pp. 369{371, 1990.

[129] D. Fathy, O. W. Holland and C. W. White, \Formation of epitaxial layers of Ge

on Si substrates by Ge implantation and oxidation," Appl. Phys. Lett., vol. 51,

pp. 1337{1339, 1987.

[130] B. Hollander, S. Mantl, B. Stritzker, H. Jorke, and E. Kasper, \Strain measure-

ments and thermal stability of Si Ge /Si strained layers," J. Mater. Res.,1¡x x

vol. 4, p. 163, 1989.

[131] C. G. Ahn, H. S. Kang, Y. K. Kwon, S. M. Lee, B. R. Ryum and B. K. Kang

, \Oxidation-induced traps near SiO /SiGe interface," J. Appl. Phys., vol. 86,2

pp. 1542{1547, 1999.

[132] A. R. Srivatsa, S. Sharan, O. W. Holland, and J. Narayan, \Nature of interfaces+and oxidation processes in Ge -implanted Si," J. Appl. Phys., vol. 65, pp. 4028{

4032, 1989.

[133] K. K. Liou, P. Mei, U. Gennser and E. S. Yang, \E®ects of Ge concentration

on SiGe oxidation behavior," Appl. Phys. Lett., vol. 59, pp. 1200{1202, 1991.

[134] Y. H. Wu, A. Chin and W. J. Chen, \Thickness dependent gate oxide quality of

thin thermal oxide grown on high temperature formed SiGe," IEEE Electron.

Dev. Lett., vol. 21, pp. 289{291, 2000.

[135] Z. Atzmon, A. E. Bair, T. L. Alford, D. Chandrasekhar, D. J. Smith and J.

W. Mayer, \Wet oxidation of amorphous and crystalline Si Ge C alloys1¡x¡y x y

grown on (100) Si substrates," Appl. Phys. Lett., vol. 66, pp. 2244{2246, 1995.

[136] A. Cuadras, B. Garrido, C. Bonafos, J. R. Morante, L. Fonseca and K. Pressel,

\Oxidation of Si Ge C strainrd layers grown on Si: kinetics and interface1¡x¡y x y

properties," Microelectron. Rel., vol. 40, pp. 829{832, 2000.

144

[137] O. Vancauwenberghe, O. C. Hellman, N. Herbots and W. J. Tan, \New SiGe

dielectrics grown at room temperature by low-energy ion beam oxidation and

nitridation," Appl. Phys. Lett., vol. 59, pp. 2031{2033, 1991.

[138] I. S. Goh, S. Hall, W. Eccleston, J. F. Zhang and K.Werner, \Interface quality of

SiGe oxide prepared by rf plasma anodization," Electron Lett., vol. 30, p. 1988,

1994.

[139] P. W. Li and E. S. Yang, \SiGe gate oxide prepared at low temperature in an

electron cyclotron resonance plasma," Appl. Phys. Lett., vol. 63, pp. 2938{2940,

1993.

[140] D. Tchikatilov, Y. F. Yang and E. S. Yang, \Improvement of SiGe oxide grown

by electron cyclotron resonance using H O vapor annealing," Appl. Phys. Lett.,2

vol. 69, pp. 2578{2580, 1996.

[141] V. Craciun, I. W. Boyd, P. Andreazza, C. B. Leborgne, \Stress e®ects induced

in SiGe strained layers by low-temperature ultraviolet-assisted oxidation," J.

Appl. Phys., vol. 83, pp. 1770{1772, 1998.

[142] L. S. Riley and S. Hall, \X-ray photoelectron spectra of low temperature plasma

anodized Si Ge alloy on Si(100): Implications for SiGe oxidation kinetics0:84 0:16

and oxide electrical properties," J. Appl. Phys., vol. 85, pp. 6828{6837, 1999.

[143] J. Rappich, I. Sieber and R. Knippelmeyer, \Enhanced passivation of the ox-

ide/SiGe interface of SiGe epitaxial layers on Si by anodic oxidation," Electro-

chemical and Solid-State Lett., vol. 4(3), pp. B11{B13, 2001.

[144] A. Agarwal, J. K. Patterson, J. E. Greene, and A Rockett, \Ultraviolet ozone in-

duced oxidation of epitaxial Si Ge (111)," Appl. Phys. Lett., vol. 63, pp. 518{1¡x x

520, 1993.

[145] L.-P. Chen, Y.-C. Chan, S.-J. Chang, G.-W. Huang, and C.-Y. Chang, \Di-

rect oxidation of Si Ge layers using vacuum-ultra-violet light radiation in1¡x x

oxygen," Jpn. J. Appl. Phys., vol. Part-2 37, pp. L122{L124, 1998.

[146] V. Craciun, A. H. Reader, W. Kersten, J. Timmers, D. J. Gravesteijn, and I.

W. Boyd, \UV-assisted oxidation of SiGe strained layers," Thin Solid Film.,

vol. 222, pp. 145{149, 1992.

145

[147] E. A. Ogryzlo, L. Zheng, B. Heinrich, K. Myrtle and H. Lafontaine, \Formation

of thin gate oxides on SiGe with atomic oxygen," Thin Solid Film., vol. 321,

pp. 196{200, 1998.

[148] M. Mukhopadhyay, S. K. Ray, T. B. Ghosh, M. Sreemani and C. K. Maiti,

\Interface properties of thin oxides grown on strained SiGe layers at low tem-

peratures," Semicond. Sci. Technol., vol. 11, pp. 360{365, 1996.

[149] S. Maikap, S. K. Ray, S. John, S. K. Banerjee and C. K. Maiti, \Electrical

characterization of ultra-thin gate oxides on Si/Si Ge C /Si quantum well1¡x¡y x y

heterostructures," Semicond. Sci. Technol., vol. 15, pp. 761{765, 2000.

[150] B. E. Deal, \The current understanding of charges in the thermally oxidized

silicon structure," J. Electrochem. Soc., vol. 121, pp. 198C{205C, 1974.

[151] W. A. Hill and C. C. Coleman, \A single frequency approximation for interface-

state density determination," Solid-State Electron., vol. 23, pp. 987{993, 1980.

[152] S. H. Lee, B. J. Cho, J. C. Kim and S. H. Choi, \Quasi-breakdown of ultrathin

gate oxide under high ¯eld stress," IEEE IEDM Tech. Dig., pp. 605{608, 1994.

[153] H. Fukuda, M. Yasuda, T. Iwabuchi and S. Ohno, \Novel N O oxynitridation2

technology for forming highly reliable EEPROM tunnel oxide ¯lm," IEEE Elec-

tron Dev. Lett., vol. 12, pp. 587{589, 1991.

[154] C. H. Seager and W. K. Senubert, \Hole trapping in oxides grown by rapid

thermal processing," J. Appl. Phys., vol. 63, pp. 2896{2871, 1988.

[155] M. Depas, T. Nigam and M. M. Heyns, \Soft Breakdown of ultra-thin gate

oxide layers," IEEE Trans. Electron Dev., vol. 43, pp. 1499{1504, 1996.

[156] T. Tomita, H. Utsunomiya, T. Sakura, Y. Kamakura and K. Taniguchi, \A

new soft breakdown model for thin thermal SiO ¯lms under constant current2

stress," IEEE Trans. Electron Dev., vol. 46, pp. 159{164, 1999.

[157] W. E. Beadle, J. C. C. Tsai amd R. D. Plummer, \Quick reference manual for

silicon integrated circuit technology P-1 ," John Wiley and Sons, New York,

1985.

146

[158] R. P. Vasquez and A. Madhukar, \Strain dependent defect formation kinet-

ics and correlation between °at-band and nitrogen distribution in thermally

nitrided SiO N /Si structures ," Appl. Phys. Lett., vol. 47, pp. 998{1000, 1985.x y

[159] W. Y. Ching and S. Y. Ren, \Electronic structures of Si N O and Ge N O2 2 2 2

crystals," Phys. Rev. B, vol. 24, pp. 5788{5795, 1981.

[160] G. A. Ruggles, R. Koba and R. E. Tressler, \Properties of SiO on Si after2

exposure of 3:1 H , N and NH ," J. Electrochem. Soc., vol. 133, pp. 2549{2 2 3

2554, 1986.

[161] M. Y. Hao, B. Maiti, and J. C. Lee, \Novel process for reliable ultrathin tunnel

dielectrics," Appl. Phys. Lett., vol. 64, pp. 2102{2104, 1994.

[162] T. Ito, T. Nakamura and H. Ishikawa, \Advantages of thermal nitride and ni-

troxidegate ¯lms in VLSI process," IEEE Trans. Electron Dev., vol. 29, pp. 498{

502, 1982.

[163] F. L. Terry Jr., R. J. Aucoin, M. L. Naiman, and S. D. Senturia, \Radiation

e®ects in nitrided oxides," IEEE Electron Dev. Lett., vol. EDL-4, p. 191, 1983.

[164] S. K. Lai, J. Lee, and V. K. Dham, \Electrical properties of nitrided oxide

systems for use in gate dielectric and EEPROM," IEEE IEDM Tech. Dig.,

pp. 190{193, 1983.

[165] T. Hori, H. Iwasaki, Y. Naito and H. Esahi, \Electrical and physical charac-

teristics of thin nitrided oxides prepared by rapid thermal nitridation," IEEE

Trans. Electron Dev., vol. 34, pp. 2238{2245, 1987.

[166] R. Jayaram, W. Yang and C. G. Sodini, \MOS electrical characteristics of low

pressure reoxidized nitrided oxide," IEEE IEDM Tech. Dig. , pp. 668{671, 1986.

[167] M. K. Mazumder, A. Teramoto, M. Sekine, S. Kawazu and H. Koyama, \Im-

proved reliability of NO treated NH -nitrided oxide with regard to O anneal-3 2

ing," Solid-State Electron., vol. 42, pp. 921{924, 1998.

[168] E. Ibok, K. Ahmed, M. -Y. Hao, B. Ogle, J. J. Worthman and J. R. Hauser

, \Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided

oxide dielectrics," IEEE Trans. Electron Dev., vol. 20, pp. 442{444, 1999.

147

[169] T. M. Pan, T. F. Lei, and T. S. Chao, \Robust ultrathin oxynitride dielectrics

by NH nitridation and N O RTA treatment," IEEE Electron Dev. Lett., vol. 21,3 2

pp. 378{380, 2000.

[170] T. Hori, H. Iwasaki and K. Tsuji, \Electrical and physical chracteristics of

ultrathin reoxidized nitrided oxides prepared by rapid thermal processing ,"

IEEE Elect. Dev., vol. 36, p. 340, 1989.

[171] W. Ting, G. Q. Lo, J. Ahn, T. Chu and D. L. Kwong, \Comparison of dielectric

wear-out between oxides grown in O and N O ," Proc. IEEE Reliability Phys.2 2

Symp., p. 323, 1991.

[172] M. Nishijima, H. Kobayashi, K. Edamoto and M. Onchi, \Reactions of NO with

Si (111) (7x7) surface: EELS, LEED and AES studies," Surface Sci., vol. 137,

p. 473, 1984.

[173] E. G. Keim and V. Silfhout, \An investigation of the interaction of N O with2

the Si (111)- 7x7 surface suing AES and optical re°ectory: A comparison with

O ," Surface Sci., vol. 216, p. L337, 1989.2

[174] M. Bhat, J. Kim, J. Yan, G. W. Yoon, L. K. Han, and D. L. Kwong, \MOS

characteristics of ultrathin NO-grown oxynitrides," IEEE Electron Dev. Lett.,

vol. 15, pp. 421{423, 1994.

[175] E. P. Gusev, H. C. Lu, E. Garfunkel and T. Gustafsson, \Nitrogen engineering

of ultrathin oxynitrides by a thermal NO/O /NO process," J. Appl. Phys.,2

vol. 84, pp. 2980{2982, 1998.

[176] M. Mukhopadhyay, S. K. Ray and C. K. Maiti, \Microwave plasma grown

oxynitride using nitrous oxide," Electron. Lett., vol. 31, pp. 1953{1954, 1995.

[177] Y. Okada, P. J. Tobin, K. G. Reid, R. I. Hegde, B. Maiti, and S. A. Ajuria,

\Furnace grown gate oxynitride using nitride (NO)," IEEE Trans. Electron

Dev., vol. 41, pp. 1608{1611, 1994.

[178] S. K. Ray, S. Das, C. K. Maiti, S. K. Lahiri, and N. B. Chakrabarti, \E®ects

of reactive ion bombardment on the properties of silicon nitride and silicon

oxynitride ¯lms deposited by ion beam sputtering," J. Appl. Phys., vol. 75,

pp. 8145{8152, 1994.

148

[179] C. T. Sah, \Models and experiment of degradation of oxidized silicon," Solid-

State Electron., vol. 33, pp. 147{167, 1990.

[180] B. E. Deal, \Standardized terminology for oxide charges associated with ther-

mally oxydized silicon," IEEE Trans. Electron Dev., vol. ED-27, pp. 606{608,

1980.

[181] N. Bhat and K. C. Saraswat, \Characterization of border trap generation in

rapid thermally annealed oxides deposited using silane chemistry," J. Appl.

Phys., vol. 84, pp. 2722{2726, 1998.

[182] D. M. Fleetwood and N. S. Saks, \Oxide, interface, and border traps in thermal,

N O, and N O-nitrided oxides," J. Appl. Phys., vol. 79, pp. 1583{1594, 1996.2 2

[183] P. P. Apte and K. C. Saraswat, \Constant current stress breakdown in ultrathin

SiO ¯lms," IEEE Trans. Electron Dev., vol. 41, p. 1595, 1994.2

[184] R. Moazzami and C. Hu, \Stress-induced current in thin silicon dioxide ¯lms,"

IEEE Trans. Electron Dev., vol. 92, pp. 139{142, 1992.

[185] O. Briere, A. Halimaoui and G. Ghibaudo, \Breakdown characteristics of ultra

thin gate oxides following ¯eld and temperature stresses," Solid-State Electron.,

vol. 41, pp. 981{985, 1997.

[186] E. Miranda, J. Sune, R. Rodriguez, M. Nafria and X. Aymerich, \Soft break-

down °uctuation events in ultrathin SiO layers," J. Appl. Phys., vol. 73,2

pp. 490{492, 1998.

[187] Y. D. He, H. Guan, M. F. Li, B. J. Cho and Z. Dong, \Conduction mecha-

nism under quasibreakdown of ultrathin gate oxide," Appl. Phys. Lett., vol. 75,

pp. 2432{2434, 1999.

[188] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam and H. E. Maes, \On the

properties of the gate and substrate current after soft breakdown in ultrathin

oxide layers," IEEE Trans. Electron Dev., vol. 45, pp. 2329{2334, 1998.

[189] M. Houssa, T. Nigam, P. W. Mertens and M. M. Heyns, \Soft breakdown

in ultrathin gate oxides: Correlation with the percolation theory of nonlinear

conductors," Appl. Phys. Lett., vol. 73, pp. 514{516, 1998.

149

[190] J. A. Diniz, A. P. Sotero, G. S. Lujan, P. J. Tatsch, J. W. Swart, \High quality of

ultra-thin silicon oxynitride ¯lms formed by low-energy nitrogen implantation

into silicon with additional plasma or thermal oxidation ," Nucl. Insts. and

Meth. in Phys. Res. (B), vol. 166-167, pp. 64{69, 2000.

[191] C. Gerardi, M. Melanotte, S. Lombardo, M. Alessandri, B. Crivelli and R.

Zonca, \E®ects of nitridation by nitric oxide on the leakage current of thin

SiO gate oxides," J. Appl. Phys., vol. 87, pp. 498{501, 2000.2

[192] M. J. Jeng and J. G. Hwu, \Enhanced nitrogen incorporation and improved

breakdown endurance in nitrided gate oxides prepared by anodic oxidation fol-

lowed by rapid thermal nitridation in N O," Appl. Phys. Lett., vol. 69, pp. 3875{2

3877, 1996.

[193] S. Maikap, S. K. Ray, S. K. Banerjee, and C. K. Maiti, \Electrical proper-

ties of O /NO-plasma grown oxynitride ¯lms on partially strain compensated2

Si/Si Ge C /Si heterolayers," Semicond. Sci. Technol., vol. 16, pp. 160{1¡x¡y x y

163, 2001.

[194] M. K. Mazumder, K. Kobayashi, J. -I. Mitsuhashi and H. Koyama, \Stress-

induced current in nitride and oxidized nitride thin ¯lms," IEEE Trans. Electron

Dev., vol. 41, pp. 2417{2422, 1994.

[195] T. Arakawa and R. Matsumoto, \Impact of nitrogen concentration pro¯le in

silicon oxynitride ¯lms on stress-induced leakage current," Appl. Surface Sci.,

vol. 113, pp. 605{609, 1997.

[196] M. K. Mazumder, A. Teramoto, J. Komori, M. Sekine, S. Kawazu, and Y.

Mashiko, \E®ects of N distribution on charge trapping and TDDB characteris-

tics of N O annealed wet oxide," IEEE Trans. Electron Dev., vol. 46, pp. 1121{2

1126, 1999.

[197] Z. H. Liu, P. T. Lai and Y. C. Cheng, \Characterization of charge trapping

and high-¯eld endurance for 15-nm thermally nitrided oxides," IEEE Trans.

Electron Dev., vol. 38, pp. 344{354, 1991.

[198] D. J. Dimaria, \Determination of insulator bulk trapped charge densities and

centroids from photocurrent-voltage characteristics of MOS structures," J.

Appl. Phys., vol. 47, pp. 4073{4077, 1976.

150

[199] D. J. DiMaria, E. Cartier and D. Arnold, \Impact ionization, trap creation,

degradation, and breakdown in silicon dioxide ¯lms on silicon," J. Appl. Phys.,

vol. 73, pp. 3367{3384, 1993.

[200] R. Rodriguez, M. Nafria, J. Sune and X. Aymerich, \Trapped charge distri-

butions in thin (10 nm ) SiO ¯lms subjected to static and dynamic stresses,"2

IEEE Trans. Electron Dev., vol. 45, pp. 881{888, 1998.

[201] Y. Hokari, \Stress voltage polarity dependence of thermally grown thin gate

oxide wearout.," IEEE Trans. Electron Dev., vol. 35, p. 1299, 1988.

[202] T. P. Chen, S. Li, S. Fung and K. F. Lo, \Interface Trap Generation by FN In-

jection under Dynamic Oxide Field Stress," IEEE Trans. Electron Dev., vol. 45,

pp. 1920{1926, 1998.

[203] P. Chaparala, J. S. Suehle, C. Messick and M. Roush, \Electric ¯eld depen-

dent dielectric breakdown of intrinsic SiO ¯lms under dynamic stress," IEEE{,2

pp. 61{66, 1996.

[204] L. Trapzon, O. O. Awadelkarim, J. Werking, G. Bersuker, and Y. D. Chan,

\Sinusoidal AC stressing of thin-gate oxides and oxide/silicon interface in 0.5-

¹m n-MOSFET's," IEEE Electron Dev. Lett., vol. 17, pp. 569{571, 1996.

[205] S. K. Ray, S. Maikap, S. K. Banerjee and C. K. Maiti, \Charge trapping char-

acteristics of ultrathin oxynitrides on Si/Si Ge C /Si heterolayers," Solid-1¡x¡y x y

State Electron., in press.

[206] M. Nafria, J. Sune, D. Yelamos and X. Aymerich, \Degradation and breakdown

of thin silicon dioxide ¯lms under dynamic electrical stress," IEEE Trans. Elec-

tron Dev., vol. 43, pp. 2215{2226, 1996.

[207] D. L. Harame, J. H. Comfort, J. D. Cressler, E. F. Crabbe, J. Y. C. Sun, B.

S. Meyerson and T. Tice, \Si/SiGe epitaxial-base transistors-part I: materials,

physics and circuits," IEEE Trans. Electron Dev., vol. 42, pp. 455{467, 1995.

[208] J. Y. Chen, \CMOS Devices and Technology for VLSI," Prentice-Hall, New

Jersey, 1990.

151

[209] D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang and K. P. Macwilliams,

\High-mobility p-channel metal-oxide-semiconductor ¯eld-e®ect transistor on

strained Si," Appl. Phys. Lett., vol. 62, pp. 2853{2855, 1993.

[210] Y. Fu and M. Willander, \Subband structure and ionized impurity scattering

of the two -dimensional electron gas in delta-doped ¯eld e®ect transistor," J.

Appl. Phys., vol. 78, p. 3504, 1995.

[211] A. Sadek, K. Ismail, M. A. Armstrong and D. A. Antoniadis, \Design of Si/SiGe

heterojunction complementary metal-oxide-semiconductor transistors," IEEE

Trans. Electron Dev., vol. 43, p. 1224, 1996.

[212] Y. K. Choi, K. Asano, N. Lindert, V. Subramanian, T. J. King, J. Bokor and

C. Hu, \Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE

Electron Dev. Lett., vol. 21, p. 254, 2000.

[213] Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. J. King J. Bokor and

C. Hu, \Nanoscale Ultra-Thin-Body Silicon-On-Insulator P-MOSFET With a

SiGe/Si Heterostructure Channel," IEEE Elect. Dev. Lett., vol. 21, p. 161, 2000.

[214] G. G. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chappell, J. H. Comfort,

B. Davari, R. H. Dennard, R. L. Franch, P. A. Mcfarland, J. S. Neely, T. H.

Ning, M. R. Polcari, and J. D. Warnock, \A room temperature 0.1-¹m CMOS

on SOI," IEEE Trans. Electron Dev., vol. 41, p. 2405, 1994.

[215] M. Ieong and T.-W. Tang, \In°unce of hydrodynamic models on the prediction

of submicrometer device characteristics," IEEE Trans. Electron Dev., vol. 44,

pp. 2242{2251, 1997.

[216] D. K. Nayak, J. C. S. Woo, G. K. Yabiku, K. P. Macwilliams, J. S. Park and K.

L. Wang, \High-mobility GeSi PMOS on SIMOX," IEEE Trans. Electron Dev.

Lett., vol. 14, pp. 520{522, 1993.

[217] C. G. Tuppen, M. R. Taylor, P. L. F. Hemment, and R. P. Arrowsmith, \Efeects

of implantation temperature on the properties of buried oxide layers in silicon

formed by oxygen implantation," Appl. Phys. Lett., vol. 45, p. 57, 1984.

[218] B.-Y. Mao, P.-H. Chang, H. W. Lam, B. W. Shen, and J. A. Keenan, \Mi-

crostructure of high-temperature annealed buried oxide silicon-on-insulator,"

Appl. Phys. Lett., vol. 48, p. 794, 1986.

152

[219] S. Cristoloveanu, J. H. Lee, J. Pumfrey, J. R. Davis, R. P. Arrowsmith, and

P. L. F. Hemment, \Pro¯ling of inhomogenious carrier transport properties

with the in°uence of temperature in silicon-on-insulator ¯lms formed by oxygen

implantation," J. Appl. Phys., vol. 60, p. 3199, 1986.

[220] C.-T. Lee and J. A. Burns, \Study of gate oxide leakage and charge trapping in

ZMR and SIMOX SOI MOSFET's," IEEE Electron Dev. Lett., vol. 9, p. 235,

1988.

[221] Silvaco International User's Manual Silvaco-ATLAS, 2000.

[222] S. P. Voinigescu, P. B. Rabkin, C. A. T. Salama and P. A. Blakey, \2D numer-

ical investigation of the impact of compositional grading on the performance

of submicrometer Si-SiGe MOSFET's," IEEE Trans. Electron Dev., vol. 42,

p. 1039, 1995.

[223] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, A. F. Tasch, L.

F. Register, and S. K. Banerjee, \A novel Si/SiGe heterojunction p-MOSFET

with reduced short-channel e®ects and enhanced drive current," IEEE Trans.

Electron Dev., vol. 47, pp. 1943{1949, 2000.

[224] Z. Shi, X. Chen, D. Onsongo, E. J. Quinones, and S. K. Banerjee, \Simulation

and optimization of strained Si Ge buried channel p-MOSFETs," Solid-State1¡x x

Electron., vol. 44, pp. 1223{1228, 2000.

[225] M. Yoshimi, M. Terauchi, A. Nishiyama, O Arusumi, A. Murakoshi, K. Mat-

suzawa, N. Shigyo, S. Takeno, M. Tomita, K. Suzuki, Y. Ushiku and H. Tango,

\Suppression of the °oating-body e®ect in SOI MOSFET's by the bandgap

engineering method using a Si Ge source structure," IEEE Trans. Electron1¡x x

Dev., vol. 44, p. 423, 1997.

[226] J. G. Fossum, R. Sudaresan, and M. Matloubian, \Anomalous subthreshold

current-voltage characteristics of n-channel SOI MOSFET's," IEEE Electron

Dev. Lett., vol. 8, p. 544, 1987.

[227] M. Yoshimi, M. Tarauchi, A. Murakoshi, M. Takahashi, K. Matsuzawa, N. Shi-

gyo and Y. Ushiku, \Technology trends of silicon-on-insulator - its advantages

and problems to be solved," IEEE IEDM Tech. Dig., p. 429, 1994.

153

[228] S. Chun and K. Wang, \E®ective mass and mobility of holes in strained

Si Ge layers," IEEE Trans. Electron Dev., vol. 39, p. 2153, 1992.1¡x x

[229] S. M. Sze, ed., \High Speed Semiconductor Devices," John Wiley & Sons, New

York, 1990.

[230] T. Manku and A Nathan, \E®ective mass for strained p-type Si Ge ," J.1¡x x

Appl. Phys., vol. 69, p. 8414, 1991.

[231] R. L. Libo®, \Introductory Quantum Mechanics," Addison-Wesley, reading

MA, vol. 2nd ed., 1992.

[232] F. Stern, \Self-consistent results for n-type Si inversion layers," Phys. Rev. B,

vol. 5, p. 4891, 1972.

[233] S. Maikap, B. Senapati and C. K. Maiti, \Technology CAD of SiGe-

heterojunction ¯eld e®ect transistors," Def. Sci. J., vol. 51, pp. 195{199, 2001.

[234] A. D. Sadovnikov, A Nathan, and T. Manku, \Numerical simulation of

transconductance in Si/SiGe p-MOSFETs," Solid-State Electron., vol. 39,

pp. 1199{1203, 1996.

[235] M. J. Palmer, G. Braithwaite, T. J. Grasby, P. J. Phillips, M. J. Prest, E. H.

C. Parker, T. E. Whall, C. P. Parry, A. M. Waite, A. G. R. Evans, S. Roy,

J. R. Watling, S. Kaya and A. Asenov, \E®ective mobilities in pseudomorphic

Si/SiGe/Si p-channel metal- oxide-semiconductor ¯eld-e®ect-transistors with

thin silicon capping layers," Appl. Phys. Lett., vol. 78, p. 1424, 2001.

[236] P. M. Garone, V. Venkataraman and J. C. Sturm, \Mobility enhancement

and quantum mechanical modeling in Ge Si channel MOSFETs from 90x 1¡x

to 300K," IEEE IEDM Tech. Dig., p. 29, 1991.

[237] L. S. Geux and K. Yamaguchi, \Modeling and characterization of a strained

Si/Si Ge transistor with ±-doped layers," J. Appl. Phys., vol. 86, pp. 1443{1¡x x

1448, 1999.

154