understanding irs3b, board-stack and mtc operation ...idlab/taskandschedule/... · 2 jul 2014jul...
TRANSCRIPT
![Page 1: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/1.jpg)
Understanding IRS3B, board-stack andmTC operation/calibrationmTC operation/calibration
C lib ti i~31ps RMS timing difference
Calibration in progress
timing difference (2 edges)
Si l dSingle edge timing:~22ps RMS
Net timing difference (Ch.7 – Ch. 4) [ns]
Gary S. Varner2 JUL 20142 JUL 2014
mTC Training Session #3
![Page 2: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/2.jpg)
Roadmap• mTC Readout
– Currently at about Phase 1.5y 5– You can get us to Phase 2.5
• Specifically• Specifically– Operators need to understand Hardware/Firmware/Software
D l l ti D t Q lit M it i– Develop real-time Data Quality Monitoring
• What I hope to convey:1. Details of the hardware: ASIC + boardstack2. Firmware and Configuration/Operating parameters3. Understand how to read and comprehend documentation
and ask meaningful questions (“it doesn’t work” notably not amongst them)
2
![Page 3: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/3.jpg)
IRS3B Structure
3http://www.phys.hawaii.edu/~mza/ASIC/IRS2-BLAB3A/index.html
![Page 4: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/4.jpg)
Hopefully, these will start to make sense in terms of
how these isettings map onto operational
parameters of theparameters of the IRS3B ASIC
4
![Page 5: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/5.jpg)
Simple softwarep
Once have writing template g pthat talks to the
picoblaze, tuning ioperational
parameters of the IRS3B ASICIRS3B ASIC really easy
5
![Page 6: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/6.jpg)
Servo-controls (3 parameters)
Sampling speed
Trigger 1-shot Width Adjust T_1_TRGPower (T_1_TRG)
ADC
100 [n
s]
Trigger outputWidthADC
Clock 10
Out
put W
idth
September 22, 20111
0 20 40 60 80 100 120
Discharge Current [uA] 6
![Page 7: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/7.jpg)
Specifically, for mTC
Software Servolock?
Trigger 1-shot Width Adjust T_1_TRGPower (T_1_TRG)
Keep
100 [n
s]
Don’t bother
Firmware Servo
10
Out
put W
idth
September 22, 20111
0 20 40 60 80 100 120
Discharge Current [uA] 7
![Page 8: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/8.jpg)
FirmwareFirmware Servo-lock
8
![Page 9: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/9.jpg)
mTC software pointer
9
![Page 10: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/10.jpg)
A word of caution
10
![Page 11: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/11.jpg)
What limits timing?Increased Amplification:
Want >100 ADC counts (> 60mV) for smallest pulses:11
Want >100 ADC counts (>~ 60mV) for smallest pulses:Carrier Rev C 90-100ps 60-70ps
![Page 12: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/12.jpg)
Oscilloscope on a chip? Calibration
~= ??
12
![Page 13: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/13.jpg)
Oscilloscope on a chip? Calibration
• Modified approximation:Modified approximation:
+ + ++ + +
~=
+ + + +=…
13
![Page 14: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/14.jpg)
Calibration and Sources of Ti i ETiming Error
voltage noise u
ti i t i t tsignal height U
timing uncertainty t
ut
Ut
1
t tr
rise time tr dBr f
t331
dBss
r
sr
rrr ffU
uft
Uu
ftt
Uut
nUut
Uut
331
14
dBsssr ffff 3
*Diagram, formulas from Stefan Ritt
![Page 15: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/15.jpg)
Calibration and Sources of Timing ErrorContributions to timing resolution:• Voltage uncertainties• Timing uncertainties
voltage noise u
timing uncertainty tsignal height U
rise time tr
*Diagram from Stefan Ritt
Of these contributions:• Random – irreducible (without
h d d i )
Let’s talk about where the deterministic pieces come from
15
hardware redesign)• Deterministic – in principle can be
calibrated away.
pand what has been done about them.
![Page 16: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/16.jpg)
First ASIC Calibration – Pedestals• Each storage cell has its own “offset” value.
M i h i l i– Measure with no signal input.– These offsets must be removed in order to see a clean(er) signal. – We call this “pedestal subtraction.”– 32k pedestals per channel (quarter million per ASIC!)
• Example:
Before pedestal subtraction After pedestal subtraction 16
![Page 17: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/17.jpg)
Comparator Transfer Functionsp• Wilkinson comparator.
R i li d t ll t ll• Ramp is supplied to all storage cells.• Comparator output fires when ramp
exceeds stored voltage.• Signals are stored with DC offset to fit
into the comparator’s dynamic range.– Offset varies somewhat for each storage
“pedestal”
cell. This is what we try to remove with pedestal correction.
• Comparator response is nonlinear.• Example shown for IRS3B comparator
17
![Page 18: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/18.jpg)
AC vs. DC Response, Pulse Persistence
• Previous slide transfer functions d ith DC i t Original pulsemeasured with DC inputs.
• AC response may not be the same!• Why not? One example… persistence.
g p“Ghost” pulse – result of writing pedestal voltage onto original pulse 1 cycle later.Why not? One example… persistence.
– Voltage has some dependence on previously stored voltage.Example from Eric Oberla PSEC3– Example from Eric Oberla, PSEC3 ASIC.
• This shows a pulse whose “ghost” persists for one or more cycles after thepersists for one or more cycles after the pulse.
• The inverse is almost certainly true: a pulse does not reach its full height due to p g
18
![Page 19: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/19.jpg)
Timing Uncertainties and Timing Calibration
• Time interval between delay line stages has intrinsic variation.• Not accounting for this properly causes significant timing errors• Differential (DNL) and Integral (INL) [run-out] Non-Linearity
19
![Page 20: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/20.jpg)
One calibration scheme
Have tried many, and they each
20have their merits and drawbacks
![Page 21: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/21.jpg)
A word of caution (anon)
21
![Page 22: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/22.jpg)
Timing Resolution as a Function of Sample NumberSample Number
75psp
Should be taking a lot of such data and analyzing
50pssuch data and analyzing it to understand timing error contributions
• Timing resolution as a function of sample number of the h h ld i ( l d )threshold crossing (pulser data).
• Indicative of noise contributions. 22
![Page 23: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/23.jpg)
IRS3D Improvements over IRS3B
1. Improved Trigger Sensitivity2 Timebase Servo locking2. Timebase Servo-locking3. dT hardware adjust4 Improved linearity/dynamic range4. Improved linearity/dynamic range5. Improved Wilkinson ADC6 No high current at power on6. No high current at power-on
= originally reported for TARGET7/X= demonstrated initially (TARGET7/X), detailed timing confirmed= LABRADOR4 independent confirmation= All ASICs since IRS3C= All ASICs since IRS3C
23
![Page 24: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/24.jpg)
Trigger Threshold Improvement• A significant improvement for smaller pulses where “first strike”
initiation of the MCP charge development is retarded
24• 16x doesn’t improve further, as already at the signal-to-noise limit
![Page 25: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/25.jpg)
Timebase servo-locking (DLL)
DLL Coarse Tuning1.15
dtTrim=1000
2.8
2.9
3
e [G
SPS]
DLL Coarse Tuning
1.11
1.13
jN (V
)
2.5
2.6
2.7
Sam
plin
g R
ate
IRSX1.07
1.09Vad
j
2.4105 110 115 120 125 130
Feedback Tap Number [of 128]
1.05105 110 115 120 125 130
SST_FB (tap stage)
Sampling tracks target delay Target sampling rate: 2.8 GSa/sFeedback tap = 121
(indirect “RCO” feedback mechanism injects asynchronous noise into timebased di i i f hi i i ifi i )
25
generator, degrading timing performance – so this is a significant improvement)
![Page 26: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/26.jpg)
Time base non-uniformity…
2.6 GSa/s If can correct reducesIf can correct, reduces processing time dramatically, as this is the
10-15% of dTtypical
y,most computationally-intensive aspect of “fast f i
26
feature extraction”
![Page 27: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/27.jpg)
Roughly Adjusted dT Sampling2 7GSa/s
Sampling not working2.7GSa/s
3.2GSa/s
Sample #
Still room for improved tuningSimple, linear dT slew correction
27Sample #
![Page 28: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/28.jpg)
Observed IRSX noise
~1.4mV
Non-gaussian distributions expected for small noise amplitude due to non-linearity in Gray-code least count
28
Take away message: noise is comparable, or better than IRS3B, and acquired while sampling continues to run
![Page 29: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/29.jpg)
IRS3B
IRS3D
29
![Page 30: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/30.jpg)
Improved Residuals, repeatabilityNote: IRS3D -- no comparator bias tuning yet done
Sh bl l~1% Integral deviation from 3rd-order over key sensitivity
Shape repeatable sample-sample (common lookup table, with only pedestal offset)
30
range with only pedestal offset)
![Page 31: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/31.jpg)
Useful Diagnostic tool
Quite sensitive to yuckiness in the data31
Quite sensitive to yuckiness in the data
![Page 32: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/32.jpg)
Improved Wilkinson “cross-feed”• Broadening at the extrema• Breakdown of simple ellipses expect otherwise
i k /i fl i h d f
IRS3B
• Kinks/inflections hard to manufacture without some type of digital interference
“kinks”
IRS3B“broadening” Broadening is “AC noise”
In vernacular of CTA colleagues
Much improved – some additional improvement expected with linearity
“kinks”
32
improvement expected with linearity correction“pinch-off”
![Page 33: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/33.jpg)
Result: visually nicer waveforms
IRS3BDifference most evident at the extremaof the waveforms
jumps
IRS3B
i
33
compression
![Page 34: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/34.jpg)
IRS3D timing (no detailed timebase calibration)(no detailed timebase calibration)
70
Single Photon Timing
~31ps RMS timing difference 50
60
70
g [p
s]
timing difference (2 edges)
Single edge30
40
gle
phot
on ti
min
g
40ps TTS
35ps TTSSingle edge timing:~22ps RMS
0
10
20
Sing
Net timing difference (Ch.7 – Ch. 4) [ns]
0 20 40 60
Electronics Contribution [ps]
For stretch goal of <= 50ps single p.e. timing, the electronics contribution should be <= 36ps for 35ps MCP-PMT TTS (best case) [<= 30ps for 40ps MCP-PMT TTS (worst case)]
IRS3D looks capable of achieving this goal. 34
![Page 35: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/35.jpg)
Summary – Day 3
H f ll f l
Final batch of detailed information presented• Hopefully useful•All of these concepts are straightforward, though
h h h t b i il t d ll tmuch, much, much to be assimilated all at once• Typically 3+ times through needed to ‘get it’
E ti l i t b dd d f lit TC• Essential issues to be addressed for quality mTCdata-taking: A i t fi ti /f db k b i Are register configurations/feedbacks being
set properly ? C t ll ? ( i f l DQM t l ?) Can we tell ? (meaningful DQM tools ?) Understanding what is being done ? C lib ti ! ( d di ti ) Calibration! (and diagnostics)
35
![Page 36: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/36.jpg)
Back-up slidesBack up slides
36
![Page 37: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/37.jpg)
Resources (where to find more)• Hardware:
– IRS3B webpage: 3 p ghttp://www.phys.hawaii.edu/~idlab/taskAndSchedule/ASIC/IRS3B/IRS3B_homepage.html
– Board stack schematics: http://www phys hawaii edu/~mza/PCB/iTOP/carriers/index html http://www.phys.hawaii.edu/ mza/PCB/iTOP/carriers/index.html http://www.phys.hawaii.edu/~mza/PCB/iTOP/index.html (Interconnect) http://www.phys.hawaii.edu/~mza/PCB/SCROD/index.html
Fi• Firmware:– References link:
http://www phys hawaii edu/~idlab/taskAndSchedule/ASIC/Firmware/Firmware homepage htmlhttp://www.phys.hawaii.edu/~idlab/taskAndSchedule/ASIC/Firmware/Firmware_homepage.html
– Repositories: http://idlab-scrod.googlecode.com/svn/SCROD-boardstack/iTOP/IRS3B_CRT/ https://code.google.com/p/idlab-general/source/browse/#svn%2Funiversal_eval%2FIRS3B_DC-stand-alone-firmware%2Fsrc
• Software:– Will talk about next time: https://www.phys.hawaii.edu/elog/
https://www.phys.hawaii.edu/elog/mtc/152
37
![Page 38: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/38.jpg)
Simplified IRS3B Block Diagramp g
Analog
Sampling
Input Analog Input
SA1 (64) SA2 (64)
Storage
Transfer A1 (64)
W0 W4 … W508
B1 (64)
W1 …
A2 (64)
W2 …
B2 (64)
W3 … W511
x8Readout 12‐bit‐counters (x64)
• Per channel:
Timing GeneratorRamp Generator
• Per channel:– Single input line– 128 sampling cells/capacitors
256 transfer cells/capacitors
• Common to all channels:• Timing generator
R t– 256 transfer cells/capacitors– 32,768 storage cells/capacitors– 64 counters used to digitize 64-samples in parallel 38
• Ramp generator
![Page 39: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/39.jpg)
mTC Readout 3 DSP_cPCI
12 DAQ fiber transceivers
IRS3B sampling ASIC
1,536 channels192 8‐ch. ASICs 12 SRM “board stacks”
CAJIPCI clock, trigger, programmingp g g
12 SCROD 39
![Page 40: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/40.jpg)
Example window buffer mgmt• Laser fired randomly with respect to FTSW clock…
– …but at a fixed time relative to the global trigger.g gg– Example 1:thit
…
PiLas TrigInPiLas TrigIn
PiLas Fires
System Trigger (CAMAC TDC start)21 MH FTSW T i I d tFTSW)21 MHz FTSW Trigger Issued (CAMAC TDC stop)
FTSW
Smaller thit larger tFTSW40
![Page 41: Understanding IRS3B, board-stack and mTC operation ...idlab/taskAndSchedule/... · 2 JUL 2014JUL 2014 mTC Training Session #3. Roadmap •mTCReadout – Currentlyy5 at about Phase](https://reader034.vdocument.in/reader034/viewer/2022052105/60402ca9a2fa716cc92349c0/html5/thumbnails/41.jpg)
Understanding Expectations: IRS3B “toy” Monte CarloVpeak 100 ADCVpeak 100 ADCRisetime 2.7 nsSampling rate 2.72 Gsa/snom dT 0 368 ns
40% CFD ratio: Applied between 2 points on leading edge that bracket this transitionnom dT 0.368 ns
nom dV 13.617 ADC/sample
sSNR = dV/noise
~44ps for 100mV peak, 2 V i
Leading Edge time [ns]
41
2mV noise