Understanding the Dynamic Behavior in GaN-on-Si Power Devices and IC’s

Kevin J. Chen

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Dynamic RON and beyond

Other important dynamic behavior

• Dynamic VTH

• Dynamic IOFF

Integrated gate driver for enhanced reliability

• Rail‐to‐rail output

• Suppressed gate ringing and false turn‐on

Summary

Outline

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Commercial GaN-on-Si power devicesCOMPARISON OF KEY FIGURES-OF-MERIT

Device Rating[V]

RDSON[mΩ]

RDSON∙QOSS[mΩ∙µC]

RDSON∙QRR[mΩ∙µC]

RDSON∙EOSS[mΩ∙μJ]

RDSON∙QG[mΩ∙nC]

VGS_max[V]

Si SJ 600 56 23.5 336.0 450 3800 20

GaN E‐mode GIT 600 55 2.2 2.2 350 300 N.A.

GaN E‐mode 650 50 2.8 2.8 350 290 7

GaN Cascode 650 52 5 7.0 730 1460 18

SiC DMOS 900 65 4.5 8.5 570 1950 18

SiC TMOS 650 60 3.8 3.3 540 3480 22

* GIT is a current driven device typically used with an RC network and a standard gate driver.

K. J. Chen, O. Häberlen, A. Lidow, C.-L. Tsai, T. Ueda, Y. Uemoto and Y. Wu, “GaN-on-Si Power Technology: Devices and Applications,” IEEE Trans. Electron Devices, vol. 64, p. 779, 2017.

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Substrate

GaN Buffer

AlGaN Barrier

2DEG

S Dp‐GaN Passivation

Gate

Different gate contact

• Different gate driving schemes• Different dynamic VTH behavior

Commercial E-mode p-GaN HEMTsType I: ohmic-type gate Type II: Schottky-type gate

-15 -12 -9 -6 -3 0 3 610-12

10-10

10-8

10-6

10-4

10-2

100

p-GaN Type II

I G (A

)

VGS (V)

p-GaN Type I

Panasonic Current‐drivingVoltage‐driving

G

Si Sub.

GaN

AlGaNPassivation DS

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• Electron trapping at the OFF state (at large VD) – Interface traps– buffer traps

• Reduced carrier density • Dynamic RON degradation• Increased VON

Increased RON

OFFON

Increased conduction loss and lower efficiency!

Dynamic RON has been the major focus.Dynamic behavior in GaN power devices

p‐GaN

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Suppression of dynamic RON degradation

• Passivation technology + field plate • Hole injection for trap compensation • Buffer optimization (carbon doping profile, “leaky buffer”, etc.)

TSMC, IEDM’14Panasonic, ISPSD’15

Other dynamic behavior?

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• Dynamic VTH and impact to: – gate driver design (e.g. how much overdrive is sufficient?) – transient behavior/performance evaluation

• Dynamic IOFF and impact to:– OFF‐state power consumption evaluation– choice of gate turn‐off voltage

Equally important (if not more) but less studied

Schottky‐type gate: Drain‐induced positive VTH as large as ~1.5 V

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VGS

VDS

VGSQ

VDSQ

t

t

tm

tm T 0 1 2 3 4 5 610-6

10-5

10-4

10-3

10-2

10-1

100

101

current collapse

0, 20, ..., 100,150, ..., 400 V

VDS: 1 V

VDSQ:

I D (A

)

VGS,ON (V)

VTH shift

Dynamic VTH in E‐mode p‐GaN HEMT

0 1 2 3 410 ‐610 ‐510 ‐410 ‐310 ‐210 ‐1100101

VDSQ

I D (A

)

VGS (V)

0V 50V 100V 200V 300V 400V

VDS = 1V

Ohmic‐type gate, e.g. GIT: Stable VTH with small VTH

Pulsed transfer curve measurement:

Dynamic VTH in Schottky p-GaN HEMT

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Root cause: the floating p‐GaN

G p-GaN AlGaN GaN

• Model: Schottky junction (DJ1) + p‐i‐n heterojunction (DJ2)

• Charge storage/emission in the floating p‐GaN VTH instability

Dynamic VTH

Floating p‐GaN

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Mechanism of the drain induced VTH

Stress: VGD < 0, J1 forward‐biased, h+ emission from p‐GaN to metalMeasure: reduced positive charges cannot be recovered immediately.

p

J1 & J2: back-to-backp-GaN: floating

VGD < 0 V

h+ reduced positive charges in p-GaN

Idischarge

EC

EF

EV

Hanxing Wang, et al., "Maximizing the Performance of 650-V p-GaN Gate HEMTs: Dynamic RONDegradation and Circuit Design Considerations," IEEE Trans. Power Electronics, July, 2017

“floating”

High drain bias OFF‐state

Gate induced VTH

10

0.0

0.4

0.8

321

VD (V

)Time (ms)

Frequency = 1 kHz

VG_stress = 5 V - 8 V

0

Sense

2

4

6

8

Sense

VG (V

)

VG_stress

sense delay

OscilloscopeCH1 CH2

VDD

RL

DUT

Function generator

VD(t)

VG(t)

Dynamic gate stress

VGS (V)

I D (A

)

VD @ VG_sense

VG (VTH shift)

ID @ VG_sense

( )DD DSD

L

V V tIR

• Dynamic VTH is extracted

from VD(t).

Gate induced positive VTH

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Positive VTH shift after gate turn-on

J. He, T. Gao and K. J. Chen, IEEE Electron Device Lett., p. 1576, Oct. 2018.

0 1 2 3 4 5 6 7 8-0.2

0.0

0.2

0.4

0.6

0.8Sense delay: 1sPeriod:

V TH

(V)

VG_stress (V)

10 s 100 s 1 ms

Mechanism: electron trapping in the depleted region of the p-GaN layer

Impact of VTH shift

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• Drain induced positive VTHmore positive VG (i.e. gate overdrive) to turn on the switch and narrower VG,ON range

• Gate induced positive VTH raised VTH at OFF state enhanced false turn‐on immunity

VGS,max

Vth

0 V False turn‐on

OFF-state leakage current

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• No p-n junctions between source and drain in the leakage path (e.g. buffer layer)

• Low leakage current is attributed to the buffer with raised energy band -- a result of C-doping.

0 200 400 60010‐1210‐1110‐1010‐910‐810‐7

VSUB = 0 V

ID IS IG ISUB

I D_O

FF (A

)

VDS (V)

VGS = 0 V

650‐V/7.5 A

Buffer: C induced traps

Quasi‐static IOFF

Dynamic IOFF

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0 200 400 60010‐9

10‐8

10‐7

10‐6

tdelay

= 2.5 ms

VGS = 0 V V

SUB = 0 V

ID I

S

IG I

SUB

I D_OFF (A

)VDS (V)

• Reduced voltage blocking capability in the buffer (both lateral and vertical)

• Reduced energy barrier due to unfilled electron traps in the buffer

Y. Wang, et al., IEEE EDL, p. 1366, Sep. 2018

Slow dynamic measurement

Static IOFF

Dynamic IOFF under fast switching

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0 20 40 6010‐910‐810‐710‐610‐510‐410‐3

tdelay = 5.0 s tdelay = 8.0 s

VDS ~ 400 V

7 V 0 V VGSQ

VGS = 0 V

tdelay = 2.5 s

I D (A

)Time (s)

• 1000 x increase without turning on the switch• 105 x increase after VG,ON = 7 V induced by hole

injection into the buffer

Dynamic IOFF vs. Static IOFF

OFF‐state power loss is ~10% of the ON‐state conduction loss.

fast dynamic measurement

Static IOFF

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Hole injection into the buffer lower barrier

Dynamic IOFF increase from hole injection

S

D

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• Lower threshold voltage Vth False turn‐on (miller effect)

• Narrower gate drive voltage VGS,ONLower noise immunity (gate ringing)

Critical gate drive margin

Driver

VDD

Lloop ~ 0

GaN driver + GaN switch

Driver

VDD

VGS

Si driver + GaN switch

Suppression of parasitic inductance by integration

Vo,max

Gen‐I integrated gate drive: issues

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Isource

During the charging process:• Charging current reduction

• Vo, max = VDD – Vth,up

• Larger VDD (> 7.5 V) → exceeding VG,max gate reliability issue

Gen‐II gate drive scheme

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Gate DriverGate Driver Power DevicePower Device

Novel gate driver design (Gen‐II)

• Charge pump unit → Help maintain the charging current

• Chip size: 4.6 mm × 1.1 mm (~5 mm2 including 130‐mΩ switch)

15% size including bonding pads

Chip‐level characterization

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The Gen‐II gate driver can provide with both enhanced drivingcapability (3X) and rail‐to‐rail output (Vo,max = VDD).

Driving capability

Power consumption

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• Caused by the DCFL (direct coupled FET logic) circuits (not CMOS)

• Standby power consumption (IDD ~ 6 mA @ VDD = 6 V)

Power consumption (from integrated gate driver)

650V130mΩ

DCFL circuit Logic stage

Switching performance using a double‐pulse tester

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• Small ringing & suppressed false turn‐on

• Without the need of negative VGS

• Minimum turn‐off time: 1.3 ns (dv/dt(max) = 336 V/ns)

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In addition to dynamic RON, the deployment of GaN‐on‐Sipower devices is also affected by other critical dynamiccharacteristics including• Dynamic VTH : impact on gate overdrive VG,ON

• Dynamic IOFF : impact on OFF‐state power consumption

Monolithically integrated gate driver leads to reducedparasitic inductance and offers several benefits including• Higher switching speed• Higher tolerance of tight gate driving voltage range

Summary

Thank you!

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AcknowledgementCollaboration and support: ‐ TSMC

Funding support: ‐ Hong Kong Innovation and Technology Fund