unit 10: testing and simulationcc.ee.ntu.edu.tw/~ywchang/courses/eda04/lec10.pdf · 2011. 1. 4. ·...
TRANSCRIPT
1
Unit 10 1Y.-W. Chang
Unit 10: Testing and Simulation˙Course contents
Combinational circuit testing Sequence circuit testing Simulation
˙Reading Chapter 10
Unit 10 Y.-W. Chang
Design Verification, Testing and Diagnosis
˙Design Verification: Ascertain that the design conform its specified
behavior˙Testing:
Exercise the system and analyze the response to ascertain whether it behaves correctly after manufacturing
˙Diagnosis: Locate the cause(s) of misbehavior after the
incorrect behavior is detected
2
Unit 10 3Y.-W. Chang
Testing˙Goal of testing is to ensure defect-free products.˙Need high quality tests that can detect realistic defects
Translate to extremely high fault coverage for low defect levels.
˙Varieties of testing Functional testing Performance testing
Unit 10 4Y.-W. Chang
Why Testing?˙Fault may occur anytime and anywhere.
Design Manufacturing Package Field
˙Larger circuits dramatically increase defect rates. n: # of transistors; p: probability that a transistor is faulty Yield: Y = (1-p)n
p = 10-6, n = 106 ⇒ Y = 36.8% p = 10-6, n = 4 r 106 ⇒ Y = 1.8%!
˙Faults are usually costly. Early finding of faults is desired.
3
Unit 10 5Y.-W. Chang
Physical Failures˙Manufacturing defects
Silicon defects Lithographic problems missing contact windows parasitic transistors oxide breakdown
˙Wear-out High current densities (electro-migration) Corrosion Ion migration “Hot” electron trapping, etc
˙These result in faulty devices, opens, shorts, improper thresholds of devices.
˙Failures are technology-dependent.
Unit 10 6Y.-W. Chang
Physical Failure Example˙Manufacturing defects
4
Unit 10 7Y.-W. Chang
Physical Failure Example˙Manufacturing defects
Unit 10 8Y.-W. Chang
Physical Failure Example˙Wear-out
5
Unit 10 9Y.-W. Chang
Fault Models˙Fault models: Stuck-at, stuck-open/closed, delay faults, etc
Possible locations of faults I/O behavior produced by the faults
˙Good news: If we have a fault model, we can test a network for every possible instantiation of that type of faults.
˙Bad news: It is difficult to enumerate all types of manufacturing faults.
Unit 10 10Y.-W. Chang
Scenario of Manufacturing Test
TEST VECTORS
ManufacturedCircuits
Comparator
CIRCUIT RESPONSE
PASS/FAILCORRECTRESPONSES
Courtesy Prof. S.-Y. Huang
6
Unit 10 11Y.-W. Chang
Stuck-at-0/1 Faults˙Stuck-at-0/1: Logic gate output is always stuck at 0 or 1,
independent of input values. Most popular fault model: single stuck-at fault.
˙Testing procedure Set gate inputs Observe gate output Compare fault-free and observed gate outputs
˙Key: Pick the gate inputs that should lead to 1 at the gate output to test stuck-at-0 fault. Similar trick works for stuck-at-1 faults.
Unit 10 12Y.-W. Chang
Stuck-at Faults in Gates˙Three ways to test NAND for stuck-at-0, only one way to test
it for stuck-at-1.˙Three ways to test NOR for stuck-at-1, only one way to test it
for stuck-at-0.
7
Unit 10 13Y.-W. Chang
Fault Coverage˙Fault coverage: % of faults that can be detected˙Test vector: set of gate inputs applied for testing defects
Test vectors for combinational circuits can be done automatically by CAD programs, called automatic test pattern generators (ATPGs).
˙6 stuck-at faults for a 2-input AND gate: SA0 (Stuck-At-0), SA1, SB0, SB1, SC0, SC1
Unit 10 14Y.-W. Chang
Defect Level˙Defect Level
Is the fraction of the shipped parts that are defective
DL = 1 – Y(1-T)
Y: yieldT: fault coverage
Courtesy Prof. S.-Y. Huang
8
Unit 10 15Y.-W. Chang
Defect Level v.s. Fault CoverageDefect Level
Fault Coverage ( % )0 20 40 60 80 100
0.2
0.4
0.6
0.8
1.0 Y = 0.01Y = 0.1
Y = 0.25
Y = 0.5
Y = 0.75Y = 0.9
(Williams IBM 1980)
High fault coverage Low defect level
Courtesy Prof. S.-Y. Huang
Unit 10 16Y.-W. Chang
Testing Combinational Networks˙100% fault coverage: test every gate for stuck-at-0 and
stuck-at-1.˙Assume that there is only one faulty gate per network.˙Example
Set (a, b, c) = (0, 0, 0) to test both NANDs for stuck-at-0 simultaneously.
Cannot test both NANDs for stuck-at-1 simultaneously due to inverter. Must use two vectors (1, 1, x) and (x, 0, 1).
Must also test inverter.
9
Unit 10 17Y.-W. Chang
Testing Procedure˙Two tasks to testing
Controlling the gate's inputs by applying values to primary inputs.
Observing the gate's outputs by inferring its values from the values at primary outputs.
˙Goal: Test gate D for stuck-at-0 fault.˙Step 1: Justify 0 values on gate inputs; work backward from
gate to primary inputs. w1 = 0 ⇒ i1 = i2 = 1; w2 = 0 ⇒ i3 = i4 = 1.
Unit 10 18Y.-W. Chang
Testing Procedure (cont'd)
˙ Step 2: Observe the fault at a primary output o1 gives different values if D is true (o1 = 0) or faulty (o1 =
1) ⇒ w3 = 0.˙Work forward and backward
w3 = 0 ⇒ i5 = w4 = 1 ⇒ i6 = i7 = 0. w3 = 0 ⇒ o2 = 1, i8 = don't care.
10
Unit 10 19Y.-W. Chang
Fault Masking and Redundancy
˙ Redundant logic may mask faults. Testing NOR for stuck-at-0 requires setting both inputs to 0. Network topology ensures that one NOR input will always be 1. Function reduces to 0: F = ab + b = 0.
˙Minimize redundant logic for design-for-testability.
Unit 10 20Y.-W. Chang
Stuck-at-Open/Closed Model
˙Model transistor always ON/OFF.
˙Stuck-open example If t1 is stuck open (switch
cannot be closed), there can be no path from VDDto output capacitance.
Testing requires two cycles
Must discharge the capacitorTry to operate t1 to see if the capacitor can be charged.
11
Unit 10 21Y.-W. Chang
Delay Fault
˙ Delay falls outside acceptable limits. Gate delay fault: assume that all delay errors are lumped
into one gate. Path delay fault: model delay errors along path through
network.˙Delay problems reduce yield
Performance problems Functional problems in some types of circuits.
Unit 10 22Y.-W. Chang
Sequential Testing
˙Much harder than combinational testing: cannot set memory element values directly. Key: Shift out memory element values. But how?
˙Must apply sequences to put machine in proper state for test, be able to observe the value of test.
12
Unit 10 23Y.-W. Chang
Sequential Testing Example˙To test NAND for stuck-at-1, must set both NAND inputs to 1.˙Primary input i1 can be controlled directly.˙To set lower NAND input, must set state to ps0 = ps1 = 0.˙Don't know the initial state of machine.˙Must find a sequence which drives machine to required state
independent of initial state.˙State sequence for test: * → s0 → s1 → s3.
Unit 10 24Y.-W. Chang
Level-Sensitive Scan Design (LSSD)˙Way to achieve full controllability, observability of registers by
linking all registers in a scan chain.˙Non-scan mode: latches are clocked by φ1, φ2 ⇒ like a two-phase
system.˙Scan mode: clocked by Ψ1, Ψ2 ⇒ latches work as a shift register
to shift present state out.˙Full scan is expensive: roll out/in states many times.˙Partial scan selects “proper” registers for scanability.
13
Unit 10 25Y.-W. Chang
Simulation˙Simulation is a design validation tool for checking a
circuit function, timing, etc.˙Simulation makes a computing model of the circuit,
executes the model for a set of input signals, and verifies the output signals.
˙Why simulation tools? Murphy's Law: “Anything that can go wrong, will!” Circuits are too large and complex! Long manufacturing turnaround time! Hard to fix a chip!
Unit 10 26Y.-W. Chang
Levels of Simulation˙Major types of simulation: from the lowest to the highest level
Device-level simulation: test the effect of fabrication parameters Circuit-level simulation: detailed analysis of voltage and current Timing-level simulation: uses slightly less accurate models of
transistors, allowing simulation of larger circuits. Switch-level simulation: treats transistors as switches. Gate-level simulation: uses gates as the basic elements. Register-transfer-level (RTL) simulation: register +
combinational logic System-level simulation:
Behavioral-level simulation: described in hardware description languagesMixed-level and mixed-mode simulationhardware-software co-simulation
14
Unit 10 27Y.-W. Chang
Device, Circuit, Timing Simulation ˙Device-level simulation:
Used to test the effect of fabrication parameters Used by technologists, not by circuit or system designers
˙Circuit-level simulation (e.g., SPICE): Analog Nodal/tableau equations: KCL, KVL laws Numerical integration
˙Timing-level simulation: Analog, but with simplifications (macro models, look-up
tables) Piecewise-linear methods
Unit 10 28Y.-W. Chang
Switch, Gate, RTL Simulation˙Switch-level simulation:
Transistors are modelled as bidirectional switches Mainly digital Circuits extracted from mask patterns can directly be simulated
˙Gate-level (or logic) simulation: ‘‘Gate’’ mainly refers to elements to be found in a component
library (e.g. for standard-cell design)NAND, NOR, multiplexer, D-flip-flop, latch, etc.
Unidirectional signal flow Closely related to ‘‘fault simulation’’
˙Register-transfer-level (RTL) simulation: Circuit is seen as composed of registers to store the state and
combinational logic to compute the next state (finite state machine model)
15
Unit 10 29Y.-W. Chang
System-Levels of Simulation˙Behavioral-level simulation:
Description in high-level language, e.g. VHDL (VHSIC Hardware Description Language), Verilog
˙Mixed-level and mixed-mode simulation: Descriptions at different levels of abstractions coexist within the
same simulation environment Critical parts of the design are described at a lower level than
noncritical parts, while it is inefficient or infeasible to model the whole circuit at the level of the most critical part
Might be easier to test a subsystem with stimuli from the system itself, rather than describing the stimuli explicitly
˙Hardware-software co-simulation: Useful in hardware-software co-design Becomes more and more important
Unit 10 30Y.-W. Chang
Circuit Simulation˙Circuit simulators like Spice numerically solve device
models and Kirchoff's Voltage and Current Laws (KVL, KCL) to determine time-domain circuit behavior. KVL: The algebraic sum of the voltage drops around a
closed path is zero. KCL: The algebraic sum of all the currents incident on a
node is zero. ˙Unlike resistors and capacitors, transistors are non-
linear devices ⇒ shall apply numerical approaches for circuit simulation.
˙Numerical solution allows more sophisticated models, non-functional (table-driven) models, etc.
16
Unit 10 31Y.-W. Chang
Spice Transistor Simulation Models˙MOS transistor models
Level 1: basic transistor equations; not very accurate. Level 2: more accurate determination of effective channel
length, transition between the linear and saturation regions. Level 3: empirical model Level 4 (BSIM): more efficient empirical model. Level 28 (BSIM2), Level 47 (BSIM3): recent model for deep
submicron transistors.˙Some Spice model parameters
L, W: transistor length, width (L, W) VT0: zero-bias threshold voltage (Vt 0) KP: transconductance (k') GAMMA: body bias factor (γ) TOX: oxide thickness (tox) NSUB: substrate doping (Na, Nd)
˙Commercially available circuit simulation tools: HSPICE, ST-SPICE, etc.
Unit 10 32Y.-W. Chang
Basic Transistor Equations
17
Unit 10 33Y.-W. Chang
Circuit Simulation of a CMOS Inverter (0.6 µm)
Unit 10 34Y.-W. Chang
Switch Simulation of a Domino Circuit˙Event-driven simulation: Evaluate a component only
when an event occurs on its inputs.˙Exp: simulation for the domino logic G= ab + c.
18
Unit 10 35Y.-W. Chang
Event-Driven Simulation˙Event-driven simulation is a widely-used mechanism
in gate- and switch-level simulators.˙An event is a change of a signal value that may trigger
new changes.˙There is a queue of events ordered by the time the
event is going to happen.˙Basic steps:
The output of a gate G changes at time ti. The fanout of the gate is inspected; it consists of the inputs of
the gates Gk that are connected to the output of gate G. If the outputs of the gates Gk change, they are scheduled to
change at time ti + ∆k, where ∆k is the delay associated with the transition.
Unit 10 36Y.-W. Chang
Signal Modeling for Gate-Level Simulation˙Signal values are discrete. ˙The minimum set consists of ‘0’, ‘1’ and ‘X’.
‘X’ means ‘‘unknown’’.˙Many models use more signal values.
IEEE std_logic data type with 9 values: mixture of leveland strength.
‘U’ (uninitialized)‘X’ (forcing unknown)‘0’ (forcing 0); ‘1’ (forcing 1)‘Z’ (high impedance)‘W’(weak unknown)‘L’ (weak 0), ‘H’, (weak 1)‘–’ (don’t care).
19
Unit 10 37Y.-W. Chang
Gate Modeling
˙Gate models should deal with multiple-valued logic.
˙Gate behavior can be represented by truth tables or compiled code.
Unit 10 38Y.-W. Chang
Delay Models for Gate-Level Simulation˙Inertial delay: a change to an input signal has to last at
least a certain time before it can trigger any reaction.˙Propagation (or transport) delay: some time passes
between the start of a signal change at the gate input and the start of a signal change at its output.
˙Rise/fall delay: due to capacitances that have to be loaded or unloaded, there is a time difference between the moment an output starts to change and the moment the output has reached its final value.
20
Unit 10 39Y.-W. Chang
Delay Model Example
Unit 10 40Y.-W. Chang
Compiler-Driven Simulation˙Compiler-driven simulation is often used in gate-level
simulators. ˙Based on making an executable-code model of circuit.˙Efficient simulation mechanism (few machine
instructions per gate).˙Applicable to few delay models in synchronous circuits
(e.g. zero-delay model).
21
Unit 10 41Y.-W. Chang
Unit-Delay Simulation
˙Assumes that all gate delays equal 1.
˙Provides some information on signal evolution in time, especially to detect glitches.
Unit 10 42Y.-W. Chang
Compiled Code for Unit-Delay Simulation