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Infuence on Instruction

Sets

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Overview

• Some instructions are much bettersuited to pipeline execution thanothers.

• Addressing modes

• Conditional code fags

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Addressing Modes

• Addressing modes include simpleones and complex ones.

• In choosing the addressing modes to

be implemented in a pipelinedprocessor, we must consider theeect o each addressing mode on

instruction fow in the pipeline! Side eects "he extent to which complex addressing modes

cause the pipeline to stall #hether a given mode is li$el% to be used b%

compilers

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&ecall

F1

F2

F3

I1

I2 (Load)

I3

E1

M2

D1

D2

D3

W1

W2

Instruction

F4I4

Clock cycle 1 2 3 4 5 6 7

Figure 8.5. Effect of a Load instruction on pipeline timing.

F5I5 D5

Time

E2

E3 W3

E4D4

'oad ()&*+, &

'oad )&*+, &

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Complex Addressing Mode

F

F D

D E

X +[R1] [X +[R1]] [[X +[R1]]]Load

Next instruction

(a) Complex addressing mode

W

1 2 3 4 5 6 7Clock cycle

Time

W

Forward

'oad )()&*++, &

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Simple Addressing Mode

X + [R1]F D

F

F

F D

D

D

E

[X +[R1]]

[[X +[R1]]]

Add

Load

Load

Next instruction

(b) Simple addressing mode

W

W

W

W

Add -(, &*, &'oad )&+, &'oad )&+, &

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Addressing Modes

• In a pipelined processor, complex addressingmodes do not necessaril% lead to asterexecution.

•

Advantage! reducing the number oinstructions program space

• /isadvantage! cause pipeline to stall morehardware to decode not convenient or

compiler to wor$ with• Conclusion! complex addressing modes are

not suitable or pipelined execution.

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Addressing Modes

• 0ood addressing modes should have! Access to an operand does not re1uire more than

one access to the memor%

Onl% load and store instruction access memor%operands

 "he addressing modes used do not have sideeects

• &egister, register indirect, index

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Conditional Codes

• I an optimi2ing compiler attempts to reorderinstruction to avoid stalling the pipelinewhen branches or data dependencies

between successive instructions occur, itmust ensure that reordering does not causea change in the outcome o a computation.

•  "he dependenc% introduced b% the condition3

code fags reduces the fexibilit% available orthe compiler to reorder instructions.

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Conditional Codes

Add

Compare

Branch=0

R1,R2

R3,R4

. . .

Compare

Add

Branch=0

R3,R4

R1,R2

. . .

(a) A program fragment

(b) Instructions reordered

Figure 8.17. Instruction reordering.

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Conditional Codes

•  "wo conclusion! "o provide fexibilit% in reordering instructions, the

condition3code fags should be aected b% as ew

instruction as possible. "he compiler should be able to speci% in which

instructions o a program the condition codes areaected and in which the% are not.