unit – 3 session - 11...its logic symbol is as shown: the 7486 ic the 7486 ttl ic is a quad...
TRANSCRIPT
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
B. S. Umashankar, BNMIT Page 1
Unit – 3
Session - 11
Data Processing Circuits
Objectives
• Write the truth table for exclusive-OR (EX-OR) Gates
• Explain the purpose of Parity Checking
• Design Parity Generators and Checkers
• Show how a Magnitude Comparator works
• Design of n-bit Magnitude Comparator
• Describe a diode ROM
Exclusive-OR Gates
The exclusive-OR gate has a high output only when an odd number of inputs are high. The 2-input
Exclusive-OR (EX-OR) gate truth table is as shown:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
The output expression is
Y = A’B + AB’.
The logic circuit of 2-input EX-OR gate is as shown:
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Its logic symbol is as shown:
The 7486 IC
The 7486 TTL IC is a quad 2-input Exclusive
performs the logic exclusive-OR function
Full Adder using EX-OR gates
The truth table of full adder is as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
input Exclusive-OR gate. It has four independent gates each of which
OR function. The pin out diagram is as shown below:
The truth table of full adder is as shown:
3 Data Processing Circuits
Page 2
It has four independent gates each of which
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Inputs
A
0
0
0
0
1
1
1
1
Full Adder Realizations:
a. Using 3-input EX-OR gate
b. Using 2-input EX-OR gates
Parity Generators and Checkers
In data communications, parity checking refers to the use of parity bits to check that data has been
transmitted accurately. The parity bit is added to every data unit that is transmitted
each data unit is set so that all bytes have either an odd number or even number of set bits
Even Parity
Even parity means an n-bit input has an even number of set bit (1’s)
Example:
Data unit 110011 has even parity. It has four set bits (1’s) i.e. even no. of 1’s
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Inputs Outputs
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Parity Generators and Checkers
In data communications, parity checking refers to the use of parity bits to check that data has been
parity bit is added to every data unit that is transmitted.
each data unit is set so that all bytes have either an odd number or even number of set bits
bit input has an even number of set bit (1’s).
It has four set bits (1’s) i.e. even no. of 1’s.
3 Data Processing Circuits
Page 3
In data communications, parity checking refers to the use of parity bits to check that data has been
. The parity bit for
each data unit is set so that all bytes have either an odd number or even number of set bits.
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Odd Parity
Odd parity means an n-bit input has an odd number of set bits (1’s)
Example:
Data unit 110001 has odd parity. It has three set bits (1’s) i.e. odd
Parity Checker
EX-OR gates are ideal for checking the parity of a binary number because they produce an output 1
when the input has an odd number of 1’s
Odd parity number
Even parity number
Parity Generation
An extra bit is added to the original binary number to produce a new binary number with even or odd
parity. The extra bit is called the parity bit
Odd-Parity Generation
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
bit input has an odd number of set bits (1’s).
It has three set bits (1’s) i.e. odd no. of 1’s.
OR gates are ideal for checking the parity of a binary number because they produce an output 1
when the input has an odd number of 1’s.
Input Output
Odd parity number 1
Even parity number 0
is added to the original binary number to produce a new binary number with even or odd
The extra bit is called the parity bit.
3 Data Processing Circuits
Page 4
OR gates are ideal for checking the parity of a binary number because they produce an output 1
is added to the original binary number to produce a new binary number with even or odd
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
74180 Truth Table
Σ of 1’s at
A - H
Even
Odd
Even
Odd
X
X
Using a 74180 to generate odd parity
Σ of 1’s
at A -
Even
Odd
Odd parity generator
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Inputs Outputs
of 1’s at
H EVEN ODD ΣEVEN ΣODD
Even 1 0 1 0
Odd 1 0 0 1
Even 0 1 0 1
Odd 0 1 1 0
1 1 0 0
0 0 1 1
odd parity
of 1’s
- H EVEN ODD ΣODD
Even 0 1
1
Odd 0
3 Data Processing Circuits
Page 5
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Magnitude Comparator
Magnitude comparator compares magnitude of two n
three outputs: X > Y, X = Y, and X < Y
1-bit Magnitude Comparator
The truth table of 1-bit magnitude comparator is as shown below:
The output expressions are:
(X>Y) = XY’
(X=Y) = X’Y’ + XY = (X’Y + XY’)’
(X<Y) = X’Y
The logic circuit of 1-bit comparator is as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Magnitude comparator compares magnitude of two n-bit numbers, say X & Y and activates one of the
X < Y. The logic diagram of n-bit comparator is as shown below:
bit magnitude comparator is as shown below:
Input Outputs
X Y X>Y X=Y X<Y
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
= (X’Y + XY’)’
bit comparator is as shown:
3 Data Processing Circuits
Page 6
say X & Y and activates one of the
bit comparator is as shown below:
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
B. S. Umashankar, BNMIT Page 7
2-bit Magnitude Comparator
The truth table of 2-bit magnitude comparator is as shown below:
Inputs Outputs Inputs Outputs
X Y X>Y X=Y X<Y X Y X>Y X=Y X<Y
0 0 0 0 0 1 0 1 0 0 0 1 0 0
0 0 0 1 0 0 1 1 0 0 1 1 0 0
0 0 1 0 0 0 1 1 0 1 0 0 1 0
0 0 1 1 0 0 1 1 0 1 1 0 0 1
0 1 0 0 1 0 0 1 1 0 0 1 0 0
0 1 0 1 0 1 0 1 1 0 1 1 0 0
0 1 1 0 0 0 1 1 1 1 0 1 0 0
0 1 1 1 0 0 1 1 1 1 1 0 1 0
Comparator Design
We can obtain simplified logic equation for 4-variable expression and implement it using logic gates.
This procedure will become very complex when we try to design a comparator for 3-bits or more. The
solution steps are:
• Use a simple generic procedure
• Define
1. Bit-wise greater than terms (G):
G1 = X1Y1’ G0 = X0Y0’
2. Bit-wise less than terms (L):
L1 = X1’Y1 L0 = X0’Y0
3. Bit-wise equality terms (E):
E1 = (G1 + L1)’ E0 = (G0 + L0)’
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
• From the definitions of G, L and E, we have
(X=Y) = E1E0 X= Y when both bits are equal
(X>Y) = G1 + E1G0 X>Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X is higher
(X<Y) = L1 + E1L0 X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
is lesser
n-bit Magnitude Comparator
The output expressions are listed bel
(X=Y) = En-1En-2…. E0
(X>Y) = Gn-1 + En-1Gn-
(X<Y) = Ln-1 + En-1Ln-2
where Ei, Gi, Li represent for
respectively
The 7485 IC
It is a 4-bit magnitude comparator TTL IC. The functional diagram is as shown below:
The additional inputs (X=Y)in, (X>Y)
numbers having more than 4-bits. When 7485 is not used in cascade (X=Y)
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
From the definitions of G, L and E, we have 2-bit comparator output as follows:
X= Y when both bits are equal
Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X is higher
X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
is lesser
The output expressions are listed below:
-2 + ……+ En-1En-2…E1G0
2 + ….. + En-1En-2…E1L0
represent for ith bit Xi = Yi, Xi > Yi, Xi < Yi terms
TTL IC. The functional diagram is as shown below:
, (X>Y)in, (X<Y)in are used to connect more than one 7485 to compare
When 7485 is not used in cascade (X=Y)in = 1, (X>Y)in
3 Data Processing Circuits
Page 8
bit comparator output as follows:
Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
are used to connect more than one 7485 to compare
in = 0, (X<Y)in = 0.
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
8-bit Comparator
The 8-bit comparator is realized using two 7485 ICs as shown below:
Read-Only Memory
A read-only memory (ROM) is used to store fixed data
be used to implement truth tables.
Diode ROM
We can build a diode circuit that stores binary numbers
Consider the binary numbers shown in the table:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
bit comparator is realized using two 7485 ICs as shown below:
only memory (ROM) is used to store fixed data. ROM can be used as ‘look-up’ table
We can build a diode circuit that stores binary numbers.
Consider the binary numbers shown in the table:
Address Nibble
0 0111
1 1000
2 1011
3 1100
4 0110
5 1001
6 0011
7 0111
3 Data Processing Circuits
Page 9
up’ table. It can also
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
The diode ROM matrix is as shown below:
When switch is
On-Chip Decoding
Switch that selects the addresses in diode ROM is replaced by on
3-to-8 decoder is used as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The diode ROM matrix is as shown below:
When switch is
at position
Output
Y3Y2Y1Y0
0 0111
1 1000
2 1011
3 1100
4 0110
5 1001
6 0011
7 0111
Switch that selects the addresses in diode ROM is replaced by on-chip decoding. For this purpose a
3 Data Processing Circuits
Page 10
. For this purpose a
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
B. S. Umashankar, BNMIT Page 11
TTL ROM ICs
Some popular TTL ROM ICs are listed below:
7488 256 bits organized as 32 x 8
74187 1024 bits organized as 256 x 4
74S370 2048 bits organized as 512 x 4
Generating Boolean Functions
Because the on-chip decoder of ROM produce all the fundamental products and the diodes OR some of
these products, diode ROM can be used to generate Boolean functions.
Questions
1. What is a parity generator?
2. Explain parity checking.
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
B. S. Umashankar, BNMIT Page 12
3. What is a magnitude comparator? Write the truth table and circuit diagram of a 1-bit magnitude
comparator.
4. Write the (X>Y) output expression for a 4-bit comparator.
5. Draw a ROM diode circuit that produces the following output:
Y3 = A’BC’, Y2 = AB’C + ABC, Y1 = AB’C + A’BC + ABC, Y0 = A’BC’ + A’BC + ABC’ + ABC
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS
www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | RESULTS | FORUMS