unit – 4 session - 14 · 2013. 4. 25. · 10cs 33 logic design unit – 4 clocks, flip-flops b....
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10CS 33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
B. S. Umashankar, BNMIT Page 1
Unit – 4
Session - 14
Flip-Flops
Objectives
• Describe the operation of the basic RS flip-flop
• Explain the purpose of the additional input on the gated or clocked RS flip-flop
• Obtain a D flip-flop from RS flip-flop
Introduction
A flip-flop is a bistable electronic circuit that has two stable states. The first electronic flip-flop was
invented by British physicists William Eccles and F. W. Jordan in 1918. It was initially called the Eccles-
Jordan trigger circuit.
Flip-flops can be either simple (transparent) or clocked. The transparent ones are commonly called
latches. It is called a latch since it will hold, or latch, in either stable state. The word latch is mainly used
for storage elements, while clocked devices are described as flip-flops.
Flip-Flop States
The flip-flop output is either low state (state 0) or high state (state 1) as shown below:
Basic Flip-Flop
The latch using two inverters is as shown:
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
One Stable State:
The Second Stable State:
NOR-Gate Latch
The basic latch can be improved by replacing the inverters with either NAND or NOR gates
additional inputs on these gates provide a convenient means for application of input signals to switch
the latch from one stable state to the
RS Latch using NOR Gates
Two 2-input NOR gates are connected as shown:
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
The basic latch can be improved by replacing the inverters with either NAND or NOR gates
additional inputs on these gates provide a convenient means for application of input signals to switch
the latch from one stable state to the other.
input NOR gates are connected as shown:
Flops
Page 2
The basic latch can be improved by replacing the inverters with either NAND or NOR gates. The
additional inputs on these gates provide a convenient means for application of input signals to switch
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
The rearranged circuit of RS latch using NOR g
The latch has two inputs reset (R) and set (S). It has two complementary outputs Q and Q’. When Q is
set, Q’ will be reset and vice-versa.
Consider the truth table of NOR gate as shown below:
From the truth table it is noted that if one of the input of NOR gate is logic 1, the output is logic 0
irrespective of the logic present on the other input. One input of NOR gate A is called reset (R) since it
resets the output (Q = 0) and similarly one input of NOR gate B is called set (S) since it resets the output
Q’, thereby setting the output Q to 1.
Working of RS latch
Consider the two inputs R = 0, and S = 0
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
using NOR gates is as shown below:
The latch has two inputs reset (R) and set (S). It has two complementary outputs Q and Q’. When Q is
Consider the truth table of NOR gate as shown below:
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
From the truth table it is noted that if one of the input of NOR gate is logic 1, the output is logic 0
logic present on the other input. One input of NOR gate A is called reset (R) since it
resets the output (Q = 0) and similarly one input of NOR gate B is called set (S) since it resets the output
Q’, thereby setting the output Q to 1.
S = 0. Assume the previous output Q n= 0.
Flops
Page 3
The latch has two inputs reset (R) and set (S). It has two complementary outputs Q and Q’. When Q is
From the truth table it is noted that if one of the input of NOR gate is logic 1, the output is logic 0
logic present on the other input. One input of NOR gate A is called reset (R) since it
resets the output (Q = 0) and similarly one input of NOR gate B is called set (S) since it resets the output
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
From the truth table of NOR gate, it can be easily verified that the next output Q
illustrated by the figure below:
Now assume that the previous output Q
Qn+1 will remain at 1 as illustrated by the figure below:
The results are summarized as shown:
We can conclude that when R = 0 and S = 0 there is no c
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
From the truth table of NOR gate, it can be easily verified that the next output Qn+1 will be 0
Now assume that the previous output Q n= 1. Once again it can be easily verified that the next output
will remain at 1 as illustrated by the figure below:
The results are summarized as shown:
Present
Inputs
Previous
Output
Next
Output
R S Qn Qn+1
0 0 0 0
0 0 1 1
that when R = 0 and S = 0 there is no change in output, i.e., Qn+1 = Q
Flops
Page 4
will be 0 as
= 1. Once again it can be easily verified that the next output
= Qn.
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Consider the two inputs R = 0, and S = 1. The circuit operation for two different assumptions of the
previous output is illustrated below:
The results are summarized as shown:
Present Inputs
R
0
0
We can conclude that when R = 0 and S = 1, we have set o
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
and S = 1. The circuit operation for two different assumptions of the
previous output is illustrated below:
The results are summarized as shown:
resent Inputs Previous
Output
Next
Output
S Qn Qn+1
1 0 1
1 1 1
We can conclude that when R = 0 and S = 1, we have set operation, i.e., Qn+1 = 1.
Flops
Page 5
and S = 1. The circuit operation for two different assumptions of the
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Consider the two inputs R = 1, and S = 0
previous output is illustrated below:
The results are summarized as shown:
Present Inputs
R
0
0
We can conclude that when R = 0 and S = 1, we have reset o
The input combination R = 1 and S = 1 is contradictory to our assumption that outputs Q and Q’ are
complementary. Hence this input combination is forbidden.
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
S = 0. The circuit operation for two different assumptions of
previous output is illustrated below:
The results are summarized as shown:
Present Inputs Previous
Output
Next
Output
R S Qn Qn+1
0 1 0 0
0 1 1 0
We can conclude that when R = 0 and S = 1, we have reset operation, i.e., Qn+1 = 0.
combination R = 1 and S = 1 is contradictory to our assumption that outputs Q and Q’ are
complementary. Hence this input combination is forbidden.
Flops
Page 6
. The circuit operation for two different assumptions of the
combination R = 1 and S = 1 is contradictory to our assumption that outputs Q and Q’ are
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
The RS flip-flop working is summarized as shown below:
RS flip-flop logic symbol is as shown:
NAND Gate Latch
The latch can be realized using NAND gates also as shown below:
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
flop working is summarized as shown below:
R S Qn+1 Action
0 0 Qn No
Change
0 1 1 SET
1 0 0 RESET
1 1 ? Forbidden
logic symbol is as shown:
latch can be realized using NAND gates also as shown below:
NAND Gate A
NAND Gate B
Flops
Page 7
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Consider the NAND gate truth table
From the truth table it is noted that if one of the input of NAND gate is logic 0, the output is logic 1
irrespective of the logic present on the other input. One input of NAND
sets the output (Q = 1) and similarly one input
Q’, thereby resetting the output Q to 0
action happens when the inputs are held at logic 0.
The truth table of the S’R’ flip-flop is shown below:
R’
1
1
0
0
The logic symbol of S’R’ is as shown:
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
able:
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
From the truth table it is noted that if one of the input of NAND gate is logic 0, the output is logic 1
irrespective of the logic present on the other input. One input of NAND gate A is called Set (S’
) and similarly one input of NAND gate B is called reset (R’) since it
resetting the output Q to 0. S’ and R’ are active low inputs, i. e., the intended set and reset
action happens when the inputs are held at logic 0.
is shown below:
S’ Qn+1 Action
1 Qn No Change
0 1 SET
1 0 RESET
0 ? Forbidden
The logic symbol of S’R’ is as shown:
IEEE Symbol
Flops
Page 8
From the truth table it is noted that if one of the input of NAND gate is logic 0, the output is logic 1
gate A is called Set (S’) since it
since it sets the output
S’ and R’ are active low inputs, i. e., the intended set and reset
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
SR Flip-Flop
We obtain SR flip-flop by adding inverters to the
SR flip-flop truth table is rewritten as shown below:
RS or SR flip-flop was constructed using two different methods:
– NOR gate realization
– NAND gate realization
We note that both have the exact same symbol and truth table
shown:
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
Logic Symbol
flop by adding inverters to the S’R’ flip-flop circuit as shown below:
flop truth table is rewritten as shown below:
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ?
flop was constructed using two different methods:
NOR gate realization
NAND gate realization
oth have the exact same symbol and truth table. The logic symbol of SR flip
Flops
Page 9
. The logic symbol of SR flip-flop is as
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Need for Clock
The latches are transparent. Any change in input information at S or R inputs is transmitted immediately
to the output at Q and Q’ according
latch when the inputs are changing and have not become stable
the inputs have become stable.
Clocked SR Flip-Flop
The SR flip-flop with an enable input and its truth table is as shown:
Truth Table
EN
1
1
1
1
0
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
Any change in input information at S or R inputs is transmitted immediately
to the output at Q and Q’ according to the truth table. We need a gating or clocking signal
latch when the inputs are changing and have not become stable. The latch has to be enabled only after
le input and its truth table is as shown:
EN S R Qn+1
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 ?
0 X X Qn
Flops
Page 10
Any change in input information at S or R inputs is transmitted immediately
gating or clocking signal to disable the
The latch has to be enabled only after
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
Clocked SR flip-flop is realized using NAND
Clocked D Flip-Flop
Generation of two input signals S and R to drive
forbidden condition of S = R = 1 may occur inadvertently
needs only a single data input as shown below:
The logic symbol of D flip-flop is as
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
using NAND gates as shown below:
Generation of two input signals S and R to drive a flip-flop is a disadvantage in many applications
forbidden condition of S = R = 1 may occur inadvertently. This has led to the D flip-flop, a circuit that
as shown below:
flop is as shown:
Flops
Page 11
flop is a disadvantage in many applications. The
flop, a circuit that
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10CS 33 LOGIC DESIGN UNIT
B. S. Umashankar, BNMIT
The D flip-flop truth table is shown below:
Data Storage
The idea of data storage is illustrated in fig
Four D latches are driven by the same clock
Questions
1. Differentiate transparent and gated flip
2. Explain the basic SR flip-flop that is
3. Write the truth table of clocked SR flip
33 LOGIC DESIGN UNIT – 4 Clocks, Flip-Flops
is shown below:
EN D Qn+1
1 0 0
1 1 1
0 X Qn
The idea of data storage is illustrated in figure below:
Four D latches are driven by the same clock and 4-bit word is stored.
Differentiate transparent and gated flip-flops.
that is realized using NOR gates.
Write the truth table of clocked SR flip-flop and D-flip-flop.
Flops
Page 12
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