UNITVI:CONTROLUNIT

Agenda•  ControlUnitmicroopera3ons•  ControlUnithardwiredimplementa3on•  MicroProgrammedcontrol•  MicroInstruc3onFormat•  Applica3onsofmicroprogramming

BasicConcept

Micro-Opera3ons•  Instruc3onexecu3on

Ø  execu3onofasequenceofsteps,i.e.,cycles•  Fetch,Indirect,Execute&Interruptcycles•  Cycle-asequenceofmicro-opera3ons•  Micro-opera3ons

Ø  datatransferbetweenregistersØ  transferbetweenaregister&anexternalbusØ  ALUopera3on

•  CUcauses theprocessor tostep throughaseriesofmicro-opera3ons inthepropersequence

•  CUgenerates the control signals that causeeachmicro-opera3on tobeexecuted

•  Micro-Opera3onsaretheatomicopera3onsoftheProcessor

Cons3tuentElementsofProgramExecu3on

Registers•  MemoryAddressRegister(MAR)

— Connectedtoaddresslinesofsystembus— Specifiesaddressforreadorwriteopera3on

•  MemoryBufferRegister(MBR)— Connectedtodatalinesofsystembus— Holdsdatatowriteorlastdataread

•  ProgramCounter(PC)— Holdsaddressofnextinstruc3ontobefetched

•  Instruc3onRegister(IR)— Holdslastinstruc3onfetched

FetchSequence•  Addressofnextinstruc3onisinPC•  Address(MAR)isplacedonaddressbus•  ControlunitissuesREADcommand•  Result(datafrommemory)appearsondatabus•  DatafromdatabuscopiedintoMBR•  PCincrementedby1(inparallelwithdatafetchfrommemory)[micro-code

RISC,length==1]•  Data(instruc3on)movedfromMBRtoIR•  MBRisnowfreeforfurtherdatafetches

FetchCycle:SequenceofeventsMAR (PC);

MBR <- (memory) PC <- (PC) +1 IR <- (MBR)

FetchCycle:SequenceofeventsMAR (PC);

MBR <- (memory) PC <- (PC) +1 IR <- (MBR)

FetchSequence(symbolic)•  t1: MAR<-(PC);CUissuesREADcommand

•  t2: MBR<-(memory) simultaneously

PC<-(PC)+I

•  t3: IR<-(MBR)wheretxreferstothe3meunit/clockcycle

------------------or------------------•  t1: MAR<-(PC)•  t2: MBR<-(memory)•  t3: PC<-(PC)+1

IR<-(MBR)

RulesforClockCycleGrouping•  Propersequencemustbefollowed

— MAR<-(PC)mustprecedeMBR<-(memory)•  Conflictsmustbeavoided

— Mustnotread&writesameregisteratsame3me— MBR<-(memory)&IR<-(MBR)mustnotbeinsamecycle

•  Also:PC<-(PC)+1involvesaddi3on— MustuseALU— Hence,mayneedaddi3onalmicro-opera3ons

IndirectCycle•  Onceaninstruc3onisfetched,thenextstepistofetchsourceoperands.•  Iftheinstruc3onspecifiesanindirectaddress,thenanindirectcyclemustprecede

theexecutecycle

•  MARcontainsanindirectaddress•  MBRcontainsadirectaddress•  Result:IRisplacedinsamestateasifdirectaddressinghadbeenusedoriginally

Address A Opcode Instruction

Memory

Operand

Pointer to operand

Indirect Addressing

t1:MAR←(IR(Address))t2:MBR←Memory

t3:IR(Address)←(MBR(Address))

IndirectCycle•  Theaddressfieldoftheinstruc3onistransferredtotheMAR.Thisisthen

usedtofetchtheaddressoftheoperand.•  Finally,theaddressfieldoftheIRisupdatedfromtheMBR,sothatitnow

containsadirectratherthananindirectaddress.•  The IR is now in the same state as if indirect addressing had not been

used,anditisreadyfortheexecutecycle.

InterruptCycle•  At the comple3on of the execute cycle, a test is made to determine

whetheranyenabled interruptshaveoccurred. If so, the interruptcycleoccurs. The nature of this cycle varies greatly from one machine toanother.

•  In the first step, the contents of the PC are transferred to theMBR, sothattheycanbesavedforreturnfromtheinterrupt.

•  ThentheMARisloadedwiththeaddressatwhichthecontentsofthePCaretobesaved,andthePCisloadedwiththeaddressofthestartoftheinterrupt-processing rou3ne. These two ac3ons may each be a singlemicro-opera3on.thefinalstepistostoretheMBR,whichcontainstheoldvalueof thePC, intomemory. Theprocessor is now ready tobegin thenextinstruc3oncycle.

t1:MBR←(PC) t2:MAR←Save_AddressforPCcontentPC←Rou3ne_Address t3:Memory←MBR(actualsavingofthePCcontents)

ExecuteCycle(ADD)•  Differentsequenceofmicro-operaEonsforeachinstrucEon

•  ADDR1,X-addthecontentsofloca3onXtoRegister1,placetheresultinR1

•  t1: MARß(IR(address(X)))•  t2: MBRß(Memory)•  t3: R1ß(R1)+MBR(loca3onX)•  Note:thereisnooverlapofmicro-operaEons

ExecuteCycle(ISZ)•  ISZX-incrementandskipifzero

— t1: MARß(IR(address(x))

— t2: MBRß(memory)

— t3: MBRß(MBR)+1

— t4: memoryß(MBR)

if(MBR)==0thenPCß(PC)+1

test&acEonoperaEonisonemicroop performedduringEmeunitt4

ExecuteCycle(BSA)–subrou3necallinstruc3on•  BSAX-Branchandsaveaddress

— AddressofinstrucEonfollowingBSAissavedinX;itwillbeusedtoreturnfromthesubrouEne

— ExecuEonconEnuesfromX+1

— t1: MARß(IR(address(X))—  MBRß(PC)-addressofnextinstrucEon

inthesequenceBSAXbranchestoX+1aXersavingreturnaddresstolocaEonX

— t2: PCß(IR(address(X))—  memoryß(MBR)-savePCcontentsinmemory

— t3: PCß(PC)+1 -startprocessingfromX+1

X : return address X+1: start of subroutine … … X+n: return from subroutine

Instruc3onCycle•  Eachphasedecomposedintosequenceofelementarymicro-opera3ons•  E.g.fetch,indirect,andinterruptcycles•  Executecycle

— Onesequenceofmicro-opera3onsforeachopcode•  Needto3esequencestogether•  Assumenew2-bitregister

—  Instruc3oncyclecode(ICC)designateswhichpartofcycleprocessorisin–  00:Fetch–  01:Indirect–  10:Execute–  11:Interrupt

FlowchartforInstruc3onCycle(Code)Operation of the Processor çè Performance of a Sequence of Micro-Operations

Indirect Cycle è Execute Cycle è next cycle depends upon the state of the system Interrupt Cycle è Fetch Cycle è next cycle depends upon the state of the system

00: Fetch 01: Indirect 10: Execute 11: Interrupt

HardwiredImplementa3on•  Controlunitinputs•  Flagsandcontrolbus

— Eachbitmeanssomething•  Instruc3onregister

— Op-codecausesdifferentcontrolsignalsforeachdifferentinstruc3on— Uniquelogicforeachop-code— Decodertakesencodedinputandproducessingleoutput— nbinaryinputsand2noutputs

•  Clock— Repe33vesequenceofpulses— Usefulformeasuringdura3onofmicro-ops— Mustbelongenoughtoallowsignalpropaga3on— Differentcontrolsignalsatdifferent3meswithininstruc3oncycle— Needacounterwithdifferentcontrolsignalsfort1,t2etc.

ControlUnitwithDecodedInputs

ProblemsWithHardWiredDesigns•  Complexsequencing&micro-opera3onlogic•  Difficulttodesignandtest•  Inflexibledesign•  Difficulttoaddnewinstruc3ons

Microinstruc3on•  An instruc3on that controls data flow and instruc3on-execu3on

sequencing in a processor at a more fundamental level than machineinstruc3ons.

•  A series of microinstruc3ons is necessary to perform an individualmachineinstruc3on.

MicroprogramExample

Microinstruction Format

EA is the effective address Symbol OP-code Description

ADD 0000 AC ← AC + M[EA] BRANCH 0001 if (AC < 0) then (PC ← EA) STORE 0010 M[EA] ← AC EXCHANGE 0011 AC ← M[EA], M[EA] ← AC

Computer instruction format

I Opcode 15 14 11 10

Address 0

Four computer instructions

F1 F2 F3 CD BR AD 3 3 3 2 2 7

F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

Micro-instruc3onTypes•  Each micro-instruc3on specifies single (or few) micro-opera3ons to be

performed—  (ver&calmicro-programming)

•  Each micro-instruc3on specifies many different micro-opera3ons to beperformedinparallel— (horizontalmicro-programming)

HorizontalMicro-programming•  Widememoryword•  Highdegreeofparallelopera3onspossible•  Likleencodingofcontrolinforma3on

Microinstruc3onFormat:Horizontal—  1.Toexecutethismicroinstruc3on,turnonallthecontrollinesindicatedbya

1 bit; leave off all control lines indicated by a 0 bit. The resul3ng controlsignalswillcauseoneormoremicro-opera3onstobeperformed.

—  2. If the condi3on indicated by the condi3onbits is false, execute the nextmicroinstruc3oninsequence.

—  3. If the condi3on indicated by the condi3on bits is true, the nextmicroinstruc3ontobeexecutedisindicatedintheaddressfield.

Microinstruc3onFormat:Ver3calVer3calMicroinstruc3on:•  Widthisnarrow•  Limitedabilitytoexpressparallelism•  Considerableencodingof control informa3on requiresexternalmemory

worddecodertoiden3fytheexactcontrollinebeingmanipulated•  In a ver3cal microinstruc3on, a code is used for each ac3on to be

performed[e.gMARPC]

MicroprogrammedControlUnit•  Thesetofmicroinstruc3onsisstoredinthecontrolmemory.•  The control address register contains the address of the next

microinstruc3ontoberead.•  When a microinstruc3on is read from the control memory, it is

transferredtoacontrolbufferregister.•  A sequencing unit that loads the control address register and issues a

readcommand.

MicroprogrammedControlUnit:Func3oning1. To execute an instruc3on, the sequencing logicunitissuesaREADcommandtothecontrolmemory.2.Thewordwhoseaddressisspecifiedinthecontroladdress register is read into the control bufferregister.3. The content of the control buffer registergenerates control signals and nextaddressinforma3onforthesequencinglogicunit.4.Thesequencinglogicunitloadsanewaddressintothe control address register based on the next-address informa3onfromthecontrolbuffer registerandtheALUflags.DependingonthevalueoftheALUflags and the control buffer register, one of threedecisionsismadebasedontheopcodeintheIR.

—  Get the next instrucEon: Add 1 to thecontroladdressregister.

—  Jump to a new rouEne based on a jumpmicroinstrucEon: Load the address field ofthe control buffer register into the controladdressregister.(Interrupt)

—  JumptoamachineinstrucEonrouEne:Loadthe control address register(Indirectaddressing)

Organiza3onofControlMemory

Wilkes:MicroprogrammedControlUnit•  ProposedbyWilkesin1951•  Matrixpar3allyfilledwithdiodes•  Duringcycle,onerowac3vated

— Generatessignalswherediodepresent— Firstpartofrowgeneratescontrol— Secondgeneratesaddressfornextcycle

Wilkes'sMicroprogrammedControlUnit

AdvantagesandDisadvantagesofMicroprogramming•  Simplifiesdesignofcontrolunit

— Cheaper— Lesserror-prone

•  Slower

TasksDoneByMicroprogrammedControlUnit•  MicroinstrucEon sequencing: Get the next microinstruc3on from the

controlmemory.•  MicroinstrucEon execuEon: Generate the control signals needed to

executethemicroinstruc3on.

Microinstruc3onsequencing:DesignConsidera3ons•  Sizeofmicroinstruc3ons•  Addressgenera3on3me

— Determinedbyinstruc3onregister–  Oncepercycle,aperinstruc3onisfetched

— Nextsequen3aladdress–  Commoninmostdesigned

— Branches–  Bothcondi3onalanduncondi3onal

SequencingTechniques•  Basedoncurrentmicroinstruc3on,condi3onflags,contentsofIR,control

memoryaddressmustbegenerated•  Basedonformatofaddressinforma3on

— Twoaddressfields— Singleaddressfield— Variableformat

BranchControlLogic:TwoAddressFields

BranchControlLogic:SingleAddressFieldWiththisapproach,theop3onsfornextaddressareasfollows:•  Addressfield•  Instruc3onregistercode•  Nextsequen3aladdress

BranchControlLogic:VariableFormatAnother approach is to provide for twoen3relydifferentmicroinstruc3onformats•  One bit designates which format is

beingused.•  In one format, the remaining bits are

usedtoac3vatecontrolsignals.•  The next address is either the next

sequen3al address or an addressderivedfromtheinstruc3onregister.

•  Intheotherformat,somebitsdrivethebranchlogicmodule,andtheremainingbitsprovidetheaddress.

•  With the second format, either acondi3onal or uncondi3onal branch isbeingspecified.

Onedisadvantageof this approach is thatone en3re cycle is consumed with eachbranch microinstruc3on. With the otherapproaches, address genera3on occurs aspartofthesamecycle.

AddressGenera3on

Explicit Implicit

Two-field Mapping

Unconditional Branch Addition

Conditional branch Residual control

Microinstruc3onExecu3on•  Thecycleisthebasicevent•  Eachcycleismadeupoftwoevents

— Fetch–  Determinedbygenera3onofmicroinstruc3onaddress

— Execute–  Effectistogeneratecontrolsignals–  Somecontrolpointsinternaltoprocessor–  Restgotoexternalcontrolbusorotherinterface

ControlUnitOrganiza3on

Microinstruc3onEncoding:DirectEncoding

Microinstruc3onEncoding:IndirectEncoding

Microinstruc3onFormat:Ver3cal

Microinstruc3onFormat:Horizontal

Example:LSI-I1Microinstruc3onFormat