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he zero flag z and the sign flag s are omitted for simplicit!. In particular LNS addition

requires the computation of the nonlinear function

Sad/ ( logb"6b-d/ 7

which substantiall! limits the data word lengths for which LNS can offer efficient VLSIimplementations. he organization of the realization of an LNS adder is shown in below fig4.

It2s noted that in order to implement LNS subtraction ie/ the addition of two quantities

of opposite sign a different memor! loo8-up table L9/ is required. he LNS subtraction L9

contains samples of the function

Ssd/ ( logb"-b-d/ :

3.1./ LNS a#, Poer ,i&&i0aio#(

LNS is applicable for low-power design because it reduces the strength of certain

arithmetic operators and the bit activit!.he operator strength reduction b! LNS reduces the

switching capacitance ie/ it reduces the CL factor of

; (

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load in comple+ number processing thus providing savings at the algorithmic level of the design

abstraction.

3./.1 RNS %a&i"&

he @ns maps an integer + to a N-triple of residues 'i

' -* A+"+4#+nB =

0here 'i(&+*mi # &.*mi denotes the mod mi operation and mi is a member of the set of the

co-prime integers 5(Am"m4#mB called moduli co-prime integers have the propert! that

gcd mimD/("i(D. he modulo operation &+*m returns the integer reminder of the integer

division + div mie/ an integer 8 such that +(m.l68 where l is an integer. @NS is of interest

because basic arithmetic operations can be performed in a digit-parallel carr! free manner

%i( &+i$ !i*mi E

0here i("4#..m and the s!mbol $ stands for addition subtraction or/ multiplication. he

C@ retrieves an integer from its @NS representation as follows,

'( &Fmi&mi-"+i*mi*m G

0here

Fig.3)a+ &r$"$re o2 %i#ar' ar"hie"$re Fig 3 )%+ Corre&0o#,i#g RNS 0ro"e&&or

3././ RNS a#, 0oer ,i&&i0aio#(

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@NS can reduce power dissipation since it reduces the hardware cost the switching

activit! and the suppl! voltage. 5! emplo!ing the binar!-li8e @NS filter structures @NS reduces

the bit activit! up to 7H in :J:/-bit multipliers. ? different approach to low power @NS is

proposed. his approach suggests to one-hot encode the residues in an @NS based structure thus

defining one-hot @NS. Instead of encoding a residue value 'i in a conventional position

notation an m-"/ bit word is emplo!ed. In this word the assertion of the ith bit denotes the

residue value 'i. It allows for further reducing bit activit! and power dela!

3.3 Re,$"i#g 0oer "o#&$!0io# i# !e!orie&(

;ower consumption due to memor! access in a computing s!stem often constitutes the

dominant portion of the total power consumption as a result power consumption of memor!

circuits has been the focus of man! research efforts during the recent !ears. this chapter e+ams

high-performance random access memor! circuits with emphasis on the sources of power

consumption and techniques for low power operation.

3./.1 Sai" ra#,o! a""e&& !e!orie&(

Static random access memories are readKwrite @K0/ memor! circuits which permit the

modification of data bit stored in memor! cells as well as their retrieval on demand. he terms

static start from the fact that as long as sufficient power suppl! voltage is provided the stored

data is retrieved indefinitel!. @andom access indicates that the access time is independent of the

ph!sical location of the data to be readKstored in the memor! arra!. S@? features high speed

and therefore is used for the main memor! in super computer or cache memor! of main frame

computer. he basic data storage cell which consist of a simple latch circuit with two stable

operating points as shown on the fig and requires si+ transistors per bit also called full S@?cell/. ?ccess to the data being held in the memor! cell is enabled b! the word line0L/ which

controls the pass transistors = and E. Connection to the "bit S@? is implemented b! two

complementar! bit lines.

Fig 2$ll SRAM "ell

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Vint ( internal suppl! voltage

Idcp ( total static current

3 ( operating frequenc!

3.3.1.3 Lo 0oer SRAM "ir"$i e"h#i$e&(

". Pivided word-line approach

4. Pivided bit-line approach

7. ;ulse operation of word-line circuitr!

:. Low power design techniques for sense amplifiers

3.3./ 4'#a!i" ra#,o! a""e&& !e!orie&(

he heart of all S@? cells consists of a two inverter latch circuit which holds the

memor! value and is accessed via two pass transistors for read and write operations. he onl!

function of the load devices in the inverters whether transistors or/ resistors was to replenish the

charge which is lost b! lea8age currents. ?s a result an S@? cell require four to si+

transistors per bit four to five lines connecting each cell including power and ground supplies

moreover most S@? cells e+cept for the full E transistor cell have non-negligible standb!

power dissipation.

In a P@? the principle is to eliminate the load devices in each cell b! simpl! storing

binar! data as a charge in a capacitor whose state is periodicall! refreshed. he refresh

operation which is necessar! since the data stored as a charge in a capacitor cannot be retained

indefinitel! because of lea8age currents removing the stored charged.

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Fig. 2o$r-ra#&i&or 4RAM "ell

3.3./.1 So$r"e& o2 0oer ,i&&i0aio# i# 4RAM&(

Similar to S@?s total power consumption in a P@? is the sum of standb! and active power

active power dissipation in d!namic random access memor! is due to the following components,

the row and column decoders

the memor! arra! which is the dominant source of power consumption in P@?s

the sense amplifiers

circuit bloc8s such as the refresh circuit the substrate bac8-bias generator the boosted

level generator the voltage reference circuit and the half-voltage generator

peripheral circuit bloc8s such as the man sense amplifier the IK buffers the write

circuitr! etc

the power sources can be summarized,

;active ( Vdd Idd(VddMmCdVd 6 CptVint/f 6 IdcpO

0here

Cd ( bit-line capacitance

Vd ( bit-line voltage swing

3.3././ Lo 0oer 4RAM "ir"$i e"h#i$e&(

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". ulti divided word-lines

4. ulti divided bit-lines

7. @efresh time increase

:. >alf-voltage bit-line precharging

=. n-chip voltage-down converter

3.5 Lo 0oer "lo"67 i#er"o##e" a#, la'o$ ,e&ig#&(

3.5.1 Lo 0oer "lo"6 ,e&ig#(

1. "lo"6 &6e

icroprocessors are cloc8ed b! a global cloc8 signal the largest difficult! is to have fr

global cloc8 and to design the cloc8 free for such a frequenc!. his is due to the cloc8 s8ewthat occurs in the cloc8 free proposed solutions are to balance the cloc8 free dela!s while

using various tric8s these solutions generall! increase the power consumption. furthermore

the! are not acceptable for ver! low voltage circuits as slightl! Vth variations can change

significantl! the dela! values of the cloc8 free buffers.

Fig. "lo"6 ,ri8er& i# he 4EC al0ha /1195

s8ew dela!s on the cloc8 inputs of flip-flops or/ latches are alwa!s shorter than

registeror/ logic dela!s. his can be achieved b! putting alwa!s some logic between latches

3.5./ La"h-%a&e, "lo"6i#g &"he!e(

he design methodolog! using latches and two non-overlapping cloc8s has man! advantages

over the use of P flip-flops methodolog! with a single-phase cloc8 as shown in fig below due to

the non overlapping of the cloc8s as long as half period of the master frequenc! and the

additional time barrier caused b! having two latches in a loop instead of one P flip-flop

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Fig. #o# o8erla00i#g "lo"6& i# ,o$%le-la"h &"he!e

his allows the s!nthesizer and router to use smaller cloc8 buffers and to simplif! the

cloc8 free generation which will reduce the power consumption of the cloc8 free with latch-

based designs the cloc8 s8ew becomes relevant onl! when its value is close to the non-

overlapping of the cloc8s.