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UNITED STATES

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2017

The Premier Conference for Design & Verification February 27 - March 2, 2017 • San Jose, California

Simulation Prototyping

VIP, Models & Databases

VERIFICATION CONTINUUM

Debug, Planning & Coverage

VirtualPrototyping

Static& Formal

Emulation

• Fastest Engines

• Native Integrations

• Unified Compile with VCS

• Unified Debug with Verdi

Visit Synopsys at Booth #101

SpyGlass

HAPS

Virtualizer ZeBuVerdi

VCS

VCFormal

VIP

PlatformArchitect

Verification Continuum Platform

table of contents

General Chair’s Welcome ..............................4

General Information ...........................................6

Voting Instructions ..............................................7

Steering Committee ............................................8

Technical Program Committee..........................9

Conference Sponsor .........................................10

Accellera Technical Excellence Award ............10

Monday Agenda ...........................................12

Tutorial Overview ..............................................13

Tutorial: 1 ..........................................................14

Sponsored Luncheon .......................................15

Tutorial: 2 ..........................................................15

Tutorial: 3 ..........................................................16

Tuesday Agenda ...........................................18

Opening Session: .............................................19

Sessions: 1 - 2 ....................................................19

Session: 3 ..........................................................20

Session 4: Poster Session .................................20

Special Session: ................................................21


Keynote Address ...............................................23

Session: 5 ...........................................................23

Session: 6 - 7 ......................................................24

Wednesday Agenda .....................................25

Panel ...................................................................26

Sessions: 8 - 9 ....................................................27

Session 10: ........................................................28


Panel ...................................................................29

Session: 11 .........................................................29

Sessions: 12 - 13 ...............................................30

Best Paper & Poster Award .............................30

Thursday Agenda .........................................32

Tutorial: 4 ...........................................................33

Tutorial: 5 ..........................................................34

Tutorial: 6 ..........................................................35


Tutorial: 7 ...........................................................36

Tutorial: 8 ...........................................................37

Tutorial: 9 ..........................................................38

DVCon Expo ...................................................40

Exhibitor Listing.................................................42

Exhibitor Floor Plan ..........................................43

Exhibiting Companies .......................................44

Simulation Prototyping

VIP, Models & Databases

VERIFICATION CONTINUUM

Debug, Planning & Coverage

VirtualPrototyping

Static& Formal

Emulation

• Fastest Engines

• Native Integrations

• Unified Compile with VCS

• Unified Debug with Verdi

Visit Synopsys at Booth #101

SpyGlass

HAPS

Virtualizer ZeBuVerdi

VCS

VCFormal

VIP

PlatformArchitect

Verification Continuum Platform

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welcome to dvcon

Dennis BrophyGeneral Chair -Mentor Graphics Corp

Welcome to DVCon U.S. 2017! It is hard to believe, but for almost 30 years, 29 to be precise, we have been gathering to explore advances in language-based design automation methodologies and electronic system verification techniques. We trust you will get a lot out of the 29th DVCon that you can apply to your daily design and verification activities.

The DVCon format is uniquely focused on the needs of electronic design and verification teams and to those in the electronic systems design automation industry who are focused on algorithmic advances, tool development and application of standards. This conference is more than just a conference, it is a community gathering that acts as an annual milestone in technology evolution and a means by which we can share best practices with each other and set the next technology goalposts as we are challenged by ever increasing design complexity.

Accellera Systems Initiative hosts the conference but the DVCon volunteers taking input from design and verification engineers around the world bring the conference to life. The volunteers are DVCon’s life blood. As General Chair, I have the honor and privilege to work with a dedicated team of volunteers. While you enjoy DVCon, feel free to connect with me and other conference volunteers if you would like to explore an active volunteer role as well. We are always looking for additional passionate individuals to join us.

DVCon is a fixture in our industry to explore the most advanced technologies to help design and verify the most complex chips. Those collaborating with me as your General Chair include several of the past DVCon chairs, particularly Yatin Trivedi and Stan Krolikoski who are full of insights and advice. I extend my gratitude for their past service and willingness to help DVCon evolve by offering their continued counsel. If you don’t recall, Yatin and Stan are the last two immediate DVCon U.S. General Chairs. They have been very involved to help make DVCon a global event where local design verticals and technologies focused in certain geographies give each DVCon their own flavor.

How do we bring DVCon to life? The Program Chair, Tom Fitzpatrick, plays a pivotal role to create a compelling technical program for you. He has a large team of reviewers

that have culled the paper submissions to create this great, comprehensive program. We offer a balance to the technical sessions with training, tutorials, poster sessions, panels and more. DVCon starts with Monday “Accellera Day” tutorials. Accellera working groups use the Monday tutorials to highlight current and emerging standards from Accellera and their application that you can use or plan to use shortly. DVCon concludes on Thursday with a day of in-depth industry sponsored tutorials. My thanks to Tutorial Chair, Aparna Dey, for bringing this all together in conjunction with the Accellera Promotions Committee. Srivastava Vasudevan is the Poster Chair. I have always found conference poster sessions to be a great way to hold a one-on-one conversation with a poster presenter and the DVCon poster sessions are ready to delight you this year. Srivastava has a good lineup for the poster session that will engage you. Vanessa Cooper is the Panel Chair where she has put in place panels that will feature some back-and-forth discussions and debates certain to make us all think. As always, we encourage you to get your questions ready because you are an active part of DVCon panels.

You will find additional program elements interesting as well.

Keynote

Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group (DSG) and System & Verification Group (SVG) at Cadence is the conference keynote. Dr. Devgan’s keynote title is “Tomorrow’s Verification Today.” He is going to review the latest trends which are redefining verification from IP to System-level with an increasingly application-specific set of demands for hardware and software development. I’m certain Dr. Devgan’s keynote will resonate with all your challenges.

Tutorials

Tutorials will be on Monday and Thursday. On Monday, Accellera Day will have a set of tutorials and on Thursday there will be a set of industry-sponsored tutorials. Accellera has three half day tutorials. Monday morning starts with one tutorial, “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” that will cover the emerging Portable Stimulus standard. This tutorial will help you prepare to take advantage of this standard when it is approved by

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Accellera. The tutorial will be delivered by Portable Stimulus Working Group members so you will get the most current information on the status of the emerging standard. I predict this emerging standard may well be one of the great productivity boosters to design and verification of advanced systems in recent times. At the lunch break, we will have a panel discussion that will give you the opportunity to interact with the Portable Stimulus presenters and those who are working on IEEE P1800.2 (UVM) and the SystemC Design and Verification standard where you will learn about the pending IEEE approval of UVM and advances in abstraction above RTL respectively. After lunch, tutorials on those two last topics will be held.

The industry tutorials on Thursday bring solutions to issues in a way that show the practical application of tools and technology. The Big-3 EDA companies are your tutorial sponsors with topics that include “Reinventing SoC Verification” from Cadence, to an “Only Formal” answer from Mentor Graphics and “Managing Low Power Verification Complexity” from Synopsys. Those topics only scratch the surface as the afternoon industry-sponsored sessions will cover more practical topics that I’m certain you can apply to your current challenges.

Technical Papers & Poster Sessions

On Tuesday and Wednesday the conference technical sessions will be held and topics will rangefrom design verification language specifics, methodology application of UVM, Formal, Analog/Mixed-Signal to system-level considerations with the impact of software on the design of systems, not just hardware. As with past years, the Technical Program Committee had a hard task to select from so many great submissions. A conference will never have room for all papers submitted. As the TPC selected the best from the best, not all good papers were able to make it into the conference. When we could, we tried to make room in the poster sessions. There are almost twenty poster presentations scheduled for Tuesday morning. There will be awards for both best papers and best posters at the end of the day on Wednesday. Please be sure to vote!

Panels

On Wednesday, there will be two panels. The morning panel will be “User’s Talk Back on Portable Stimulus.” While this is

an emerging standard, users are already using technology from several companies that have helped drive the standardization effort. It will be great to add your voice from the floor as the panels are going to be open for audience questions too.

The afternoon panel will explore the impact of SystemVerilog on one’s career. Has it been good for you or has it “jinxed” it as the panel title says may have happened. Certainly, SystemVerilog has had many things emerge because of it. Verification IP as a business standardized on the language has flourished and we have all come to leverage it with UVM, the Universal Verification Methodology. This leads me to ask, is “jinxed” a “good” spell that has been cast on your career or something else?

Special Session

From time-to-time DVCon will host some special sessions. This year, Harry Foster has been asked to present “Trends in Functional Verification: A 2016 Industry Study” based on the Wilson Research Group’s 2016 study. The findings from the 2016 study provide invaluable insight into the state of today’s electronics industry.

Exhibits and Show Floor

Coming together as a community is fostered by the DVCon Expo. The bigger and better exposition will run from Monday evening to Wednesday evening. See the program for specific opening and closing times. The Expo is a great place to catch up with commercial vendors and learn the latest in product developments. It is also great to connect with colleagues and exchange and share information and ideas. Join us for the DVCon U.S. 2017 “Booth Crawl” where after visiting select exhibitors you will be automatically entered for a lucky draw.

All in all, there will be four days of learning, sharing, and industry interactions that will allow you to plan how to apply all this to your own design and verification environment in the months and years ahead. On behalf of all the volunteers and conference management staff we welcome you to DVCon U.S. 2017!

General Chair, DVCon U.S. 2017

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conference details

Registration Hours Location: Bayshore FoyerMonday, February 27 .......................... 7:30am to 7:00pmTuesday, February 28 .......................... 7:30am to 6:00pmWednesday, March 1 ........................... 7:30am to 6:00pmThursday, March 2 ............................... 7:30am to 4:00pm

Expo Hours Location: Bayshore Ballroom

Monday, February 27 ......... 5:00pm to 7:00pm

Tuesday, February 1 ............................ 2:30pm to 6:00pmWednesday, March 2 ........................... 2:30pm to 6:00pm

Parking Instructions Day/overnight self parking is $13.00 per day/per car with no in/out privileges.

Local attendees are to scan their parking ticket at the designated DVCon validation area (Bayshore Foyer). The scanner will beep 3 times to notify the attendee has validated their tickets at the group discounted rate.

There are two pay stations inside the hotel. One is located near the convention entrance (Bayshore Foyer) side. This machine accepts both cash and credit card. The second pay station is located near the guest elevators near the South Parking Lot. This machine accepts only cash.

DVCon Tutorials & Proceedings Distribution DVCon Conference Papers and Tutorial presenter slides will be delivered electronically online via a username and password.

To access: http://proceedings.dvcon.org Username = Email address Password = Registration ID (on your badge)

Please refer to your registration receipt to access the files you are eligible to view.

Wireless InformationEnjoy free Wi-Fi at DVCon! Connect to the Conference Wi-Fi via: Wi-Fi SSID: DVCon2017 No Password Required

Social Media At DVConFollow @DVCon on Twitter and get hourly conference announcements. Also, tweet #DVCon about your experience and highlights at the conference! Don’t miss DVCon on Facebook at facebook.com/DVCon.

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Thank you to our Sponsor:

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Best Paper & Poster VotingAll Access, Conference Only and One-Day only registrants are entitled to vote for the “DVCon Best Paper and Poster” awards. The attendees are the judges! Enjoy the convenience of voting from your PC and mobile device: 1. Go to http://vote.dvcon.org2. Vote on the papers and posters you have attended

Awards PresentationWednesday, March 1 | Location: Bayshore Ballroom | 5:00pm Join us on the Exhibit Floor for the announcement of the 2017 award recipients!

Expo Floor Plan

EMPLOYEE AREA

REGISTRATION

UP TOSECONDFLOOR

FOYERENTRANCE

EXIT

EXIT

WOMEN MEN

SERVICE CORRIDOR

205305405

304404504604

302402502602

1013014015018019011001

1101

505805905

904

1002 902702

1004

605705

601701

PHONES

Thank you to our sponsors:

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steering committee

Past ChairYatin TrivediAricent, Inc.2580, N. First StreetSan Jose, CA [email protected]

Accellera Representative & Finance ChairLynn Bannister-GaribaldiAccellera Systems Initiative8698 Elk Grove Blvd. Ste 1, #114 Elk Grove, CA 95624 [email protected]

General Chair Dennis BrophyMentor Graphics Corp. 8005 SW Boeckman Rd. Wilsonville, OR 97070 [email protected]

Vice Chair Ambar Sarkar, Ph.D.eInfochips2025 Gateway Place, Suite #270, San Jose, CA 95110. [email protected]

Panel Chair Vanessa CooperVerilab, Inc.609 Castle Ridge Rd., Ste. 210Austin, TX 78746512-537-3136, ext. [email protected]

Program ChairTom FitzpatrickMentor Graphics Corp. 18 Whistle Post Ln. Groton, MA 01450 [email protected]

Publicity/Marketing ChairBarbara BenjaminHighPointe Communications246 SE Spokane St.Portland, OR 97202 [email protected]

Conference ManagerNannette JordanMP Associates, Inc.1721 Boxelder St., Ste. 107 Louisville, CO 80027 [email protected]

Tutorial Co-Chair Aparna DeyCadence Design Systems, Inc.2655 Seely Ave., Bldg. 9 San Jose, CA, 95134 [email protected]

Poster ChairSrivatsa VasudevanSynopsys, Inc. [email protected]

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technical program committee

Mark AzadpourWestern Digital Corp.

Kamel BelhousTeradyne, Inc.

Dan BenuaCmma Inc.

Clifford CummingsSunburst Design, Inc.

Stephen D’OnofrioParadigm Works

Charles DawsonCmma Inc.

Joanne DeGroatOhio State University

John DickolSamsung Austin R&D Center

Harry FosterMentor Graphics Corp.

Manish GajjarLight

Ning GuoAdvanced Micro Devices, Inc.

Kaiming HoIndependent

Phu HuynhCmma Inc.

Tor JeremiassenTexas Instruments, Inc.

Neyaz KhanCadence Design Systems, Inc.

Kelly LarsonParadigm Works, Inc.

Kaowen LiuMediaTek, Inc.

Paul MarriottVerilab

Don MillsMicrochip Technology, Inc.

Nagi NaganathanBroadcom Corporation

Karen PieperMicrosemi Corp.

Mitchell PoplingherMicrosemi Corp.

Logie RamachandranVeriKwest Systems Inc.

Josh RenschSuperion Technology

Dave RichMentor Graphics Corp.

Imtiyaz RonBroadcom Corp.

Ambar SarkareInfochips

Erik SeligmanIntel Corp.

Amit SharmaSynopsys, Inc.

Robert TroyON Semiconductor

Greg TumbushTumbush Enterprises LLC

Antonio VazSynopsys India Pvt. Ltd.

Srinivasan VenkataramananCVC Pvt., Ltd.

Program ChairTom FitzpatrickMentor Graphics Corp. 18 Whistle Post Ln. Groton, MA 01450 [email protected]

Poster ChairSrivatsa VasudevanSynopsys, Inc. [email protected]

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conference sponsorS

Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the

worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.

Our MissionAt Accellera our mission is to provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products.

The purposes of the organization include:

• Provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process.

• Collaborate with our community of companies, individuals,and organizations to deliver standards that lower the cost of designing commercial IC and EDA products and embeddedsystem solutions, as well as increase the productivity of designersworldwide.

• Encourage availability and adoption of next-generation EDA andIP standards that encompass system-level, RT-level, and gate-leveldesign flows.

• Collaborate with the electronic design community to deliverstandards that increase designer productivity and lower the costof product development.

• Provide mechanisms that enable the continued growth of theAccellera Systems Initiative user community including SystemC,Universal Verification Methodology (UVM), and IP-XACT.

• Standardize technical implementations developed by Accellera Systems Initiative through the IEEE.

MembershipAccellera members directly influence development of the most important and widely used standards in electronic design. Member companies protect and leverage their investment in design languages through their funding of a proven, effective and responsible organization. In addition, our members have a higher level of visibility in the EDA industry as active participants in Accellera-sponsored activities and as contributors to its decisions, which impact the EDA industry. For a full list of technical activities that are supported by Accellera, and for information on how to join us, please visit our website at www.accellera.org.

Accellera wishes to recognize the outstanding achievements of its Working Group members by selecting outstanding contributors to our standards development process as recipients of the Accellera Systems Initiative Technical Excellence Award.

This annual award recognizes major contributions to the development of Accellera standards. Examples of such contributions may include leadership in standardization of new technologies, assuring achievement of standards development goals, and identifying opportunities to better serve the needs of the community through standards.

Any member of an Accellera Working Group is eligible for the award. Candidates can be nominated by Working Group chairs and are

endorsed and selected by participants of the Accellera Technical Excellence Award Committee, which is a subcommittee of the Technical Committee.

Past Recipients:2016: Erwin de Kock 2015: Justin Refice 2014: Andrew Goodrich 2013: Janick Bergeron 2012: John Aynsley

For more information about Accellera awards programs and to find out how to submit a nomination, visit accellera.org/about/awards.

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About Accellera Systems Initiative

Accellera Systems Initiative Technical Excellence Award

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Sponsored by: Accellera Global Sponsors:

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endorsed and selected by participants of the Accellera TechnicalExcellence Award Committee, which is a subcommittee of theTechnical Committee.

Past Recipients:2016: Erwin de Kock2015: Justin Refice2014: Andrew Goodrich2013: Janick Bergeron2012: John Aynsley

For more information about Accellera awardsprograms and to find out how to submit a nomination,visit accellera.org/about/awards.

event sponsors

Thank you to our Luncheon Sponsors

Thank you to our Thursday Tutorial Sponsors

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Accellera Systems Initiative Technical Excellence Award

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Coffee BreakRoom: Gateway Foyer

monday’s agenda

9:00am - 12:00pm

8:00am - 11:00am

12:00pm - 1:30pm

2:00pm - 5:00pm

3:00pm - 4:00pm

5:00pm - 7:00pm

Tutorial 1Creating Portable Stimulus Models with the Upcoming Accellera Standard Room: Oak

Sponsored LuncheonAccellera Lunch Featuring the 2017 Technical Excellence Award and an Update on Accellera Standards, Including a Town Hall DiscussionRoom: Pine/Cedar

Tutorial 2Introducing IEEE 1800.2 –The Next Step for UVMRoom: Oak

Tutorial 3SystemC Design and Verification – Solidifying the Abstraction Above RTLRoom: Fir


DVCon Expo & Booth CrawlRoom: Bayshore Ballroom

DVCon is doing it again! You won’t want to miss the annual DVCon Booth Crawl on the exhibit floor. Cocktails and conversations in a casual environment with the DVCon exhibitors. By attending the Booth Crawl you’ll be automatically entered into a drawing for a $500 VISA gift card. The winner must be present to win and will be announced Monday night.Mingle from booth to booth while enjoying food and drinks.

Look for the flag to find a participating company!

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Monday Tutorials and Luncheon Sponsored by

MONDAY + Thursday tutorials

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tutorial overview

Monday, February 27Tutorial 1: Creating Portable Stimulus Models with the

Upcoming Accellera Standard ...........................................................................14

Tutorial 2: Introducing IEEE 1800.2 – The Next Step for UVM ..........................................15

Tutorial 3: SystemC Design and Verification – Solidifying the Abstraction Above RTL ...16

Thursday, March 2Tutorial 4: Reinventing SoC Verification – It Is about Time ..............................................33

Tutorial 5: Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify My Rescue Drone’s RTL? .........................................................34

Tutorial 6: Practical Applications for Managing Low Power Verification Complexity and Debug of Advanced SoCs .......................................................35

Tutorial 7: Optimizing IP Verification – Which Engine? .....................................................36

Tutorial 8: Testbench Automation : How to Create a Complex Testbench in a Couple of Hours ........................................................................37

Tutorial 9: Formal Verification Methodology: Maximizing Productivity and Achieving Formal Closure with Confidence .............................................38

Special Thanks to Our Tutorial Sponsors

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Tutorial 1 - Creating Portable Stimulus Models with the Upcoming Accellera StandardTime: 9:00am - 12:00pm | Room: Oak

Portability of reusable test cases has long been a goal for semiconductor verification and validation teams. No one wants to “reinvent the wheel” by having to rewrite similar tests again and again. While the widely accepted, Accellera Universal Verification Methodology (UVM) standard, enabled reuse of testbench components and constrained-random tests at the IP and block level, limitations in terms of reuse at subsystem and full-chip level, and lack of portability across execution platforms required a fresh look at addressing the portable stimulus and test challenge. Accellera Systems Initiative formed the Portable Stimulus Working Group (PSWG) in early 2015 to do just that. The group’s charter is to define a portable test and stimulus standard specification to permit the creation of a single representation/model, usable by a variety of users across different levels of integration under different configurations, enabling the generation of different implementations that run on a variety of execution platforms, including, but not limited to, simulation, emulation, FPGA prototyping, and post-silicon. With such a specification in place, EDA vendors can produce tools that automatically generate stimulus, results checks, and coverage metrics tuned for a particular target. The first version of the Accellera Portable Test and Stimulus Standard (PSS) is nearing completion. This timely tutorial presents an introduction to the standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs. The tutorial will show with actual coding examples how the verification and portability challenges of these examples are met using the standard.

Attendees will learn how to:

• Understand and develop abstract, portable testand stimulus models for their chip designs

• Use PSS constraints to guide randomization ofboth data and control flow to describe a legalscenario space to be verified

• Target use of existing low-level sequences ordrivers in the generation of tests

• Execute generated tests across platforms fromsimulation, emulation, FPGA prototype, andpost-silicon to verify a complete chip ormulti-chip system

• Specify and gather coverage metrics at every stepto assess verification completeness

Speakers:David Brownell - Analog Devices, Inc.Sharon Rosenberg - Cadence Design Systems, Inc.Tom Fitzpatrick - Mentor Graphics Corp.Adnan Hamid - Breker Verification Systems, Inc.Srivatsa Vasudevan - Synopsys, Inc.Karthick Gururaj - Vayavya Labs Pvt., Ltd.Faris Khundakjie - Intel Corp.

Organizer:Barbara Benjamin - Accellera Systems Initiative


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MONDAY, FEBRUARY 27

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Tutorial 2 - Introducing IEEE 1800.2 - The Next Step for UVMTime: 2:00pm - 5:00pm | Room: Oak

By all measures, UVM is the most successful verification standard ever created in the EDA community. And that’s no boast. From inception to today, it has swept through project teams worldwide which makes it ready for the next step with the IEEE. The IEEE 1800 committee is completing the work on UVM as the 1800.2 standard. This rigorous review of the Accellera work has resulted in some changes that improve UVM as a standard for interoperability. The tutorial will focus on those changes and how you can prepare for the IEEE standard today. As we

review those changes, we will also examine the impact it will have on your existing verification environments including how to debug and regold those environments improving your ability to share verification IP among globalized teams.

Speakers:Tom Alsop - Intel Corp.Srivatsa Vasudevan - Synopsys, Inc.Mark Glasser - NVIDIA Corp.Srinivasan Venkataramanan - CVC Pvt., Ltd. Krishna Thottempudi - Qualcomm, Inc.

Organizer:Adam Sherer - Accellera Systems Initiative

Accellera Lunch Featuring the 2017 Technical Excellence Award and an Update on Accellera Standards, Including a Town Hall DiscussionTime: 12:00pm - 1:30pm | Room: Pine/Cedar

Accellera Day 2017 at DVCon will be filled with exciting technical insights you’ll be able to apply immediately to your projects. In the middle of the day we’ll take a break and gather for lunch where we will have a presentation by Accellera that will include the 2017 Technical Excellence award, a look forward to the worldwide DVCon events, latest news, and working group activities. After that, we will have a town hall meeting covering topics including:

• Follow up questions from the Portable Stimulusmorning tutorial

• Future directions for the UVM Working Group

• SystemC working groups activity includingwhat’s new

Speakers:Mark Glasser - NVIDIA CorporationTrevor Weiman - Intel Corp.David Brownell - Analog Devices, Inc.


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DVCon-China.org

DVCon 2017

Join us at the Parkyard HotelShanghai for DVCon Chinachina

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2017

join us in China, April 19, 2017

专家级的学习平台

Tutorial 3 - SystemC Design and Verification - Solidifying the Abstraction Above RTLTime: 2:00pm - 5:00pm | Room: Fir

Each year the EDA community makes critical advances in SystemC. As we do, the momentum toward SystemC as the primary point of entry above RTL becomes more tantalizing. Will this be the year your team makes the leap? This tutorial could answer that question for you.

We will focus on three key components that could help you make that decision: design, modeling, and testbench. We’ll start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation will follow to complete our view of the overall design. Of course, we need to verify this fast-running design with a testbench approach

that can be reused at RTL so we’ll discuss how to apply the emerging UVM-SystemC standard. We’ll complete the tutorial with a Q/A session with all of our presenters focusing on the remaining work they see to help you make the leap to the SystemC abstraction.

Speakers:Trevor Wieman - Intel Corp.Peter Frey - Mentor Graphics Corp.



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DVCon-China.org

DVCon 2017

Join us at the Parkyard HotelShanghai for DVCon Chinachina

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2017

join us in China, April 19, 2017

专家级的学习平台

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10:30am - 11:00am

Special SessionTrends in Functional Verification: A 2016 Industry StudyRoom: Fir

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Opening SessionRoom: Oak



DVCon ExpoRoom: Bayshore Ballroom

9:00am - 10:30am

8:15am - 8:45am

7:30am - 11:00am

12:00pm - 1:15pm

1:30pm - 2:30pm

10:30am - 12:00pm

3:00pm - 4:30pm

2:30pm - 3:00pm

2:30pm - 6:00pm

5:00pm - 6:00pm

Session 1UVM StimulusRoom: Oak

Session 2Optimizing VerificationRoom: Fir

Session 3Power OptimizationRoom: Monterey/Carmel

Session 5UVM Register Layer ApplicationsRoom: Oak

Session 6Exploring SystemVerilogRoom: Fir

Session 7Coverage OptimizationRoom: Monterey/Carmel

Sponsored LuncheonApplication Specific Verification From Edge Nodes Through Hubs, Networks And Servers – Are The Requirements All The Same? Room: Pine/Cedar

Keynote Address: Tomorrow’s Verification TodayAnirudh Devgan - Senior Vice President and General Manager of the Digital & Signoff Group (DSG) and System & Verification Group (SVG)Room: Oak/Fir

Poster SessionRoom: Gateway Foyer

DVCon ReceptionRoom: Bayshore Ballroom

dvcon expo

tuesday’s agenda


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tuesday, February 28

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Opening SessionTime: 8:15am - 8:45am | Room: OakJoin us as we set the stage for the 2017 DVCon Conference and Exhibition. DVCon’s Steering Committee will highlight the conferences events.

Session 1 - UVM StimulusTime: 9:00am - 10:30am | Room: Oak

How to use UVM to Generate Interesting Stimulus.

1.1 Error Injection: When Good Input Goes BadKurt Schwartz - Aletheia Design Services & Willamette HDLTim Corcoran - Willamette HDL

1.2 ASimplifiedApproachUsingUVMSequence ItemsforLayeringProtocolVerificationHaiqian Yu, Christine Thomson - Microsoft Corp.

1.3 KeepingYourSequencesRelevantNicholas Zicha, Eric Combes - Accedian Networks

Session Chair:Clifford Cummings - Sunburst Design, Inc.

Session 2 - Optimizing VerificationTime: 9:00am - 10:30am | Room: Fir

Interesting Approaches to Optimizing Various Aspects of Verification.

2.1 DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit K. Jain, Hui Yin - Mentor Graphics Corp.

2.2 EfficientSCE-MIUsagetoAccelerateTBAPerformancePonnambalam Lakshmanan - Analog Devices, Inc., Prashantkumar Ravindra, Rajarathinam Susaimanickam - Aceic Design Technologies

2.3 NewConstrainedRandomandMetric- DrivenVerificationMethodology using PythonMarek Cieplucha, Witold Pleskacz - Warsaw Univ. of Technology

Session Chair:Erik Seligman - Intel Corp.

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Session 3 - Power OptimizationTime: 9:00am - 10:30am | Room: Monterey/Carmel

Low Power Verification Applications.

3.1 RandomDirectedLow-PowerCoverageMethodology: A Smart Approach to Power AwareVerificationClosureAwashesh Kumar, Madhur Bhargava - Mentor Graphics Corp.

3.2 Emulation Based Full Chip Level Low Power ValidationatPre-SiliconStageKyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, Suk Won Kim - Samsung Electronics Co., Ltd.

3.3 Automatic Investigation of Power InefficienciesKuo-KaiHsieh - Univ. of California, Santa BarbaraWen Chen, Monica Farkash, Jayanta Bhadra - NXP SemiconductorsLi-C. Wang - Univ. of California, Santa Barbara

Session Chair:Charles Dawson - Cadence Design Systems, Inc.

Session 4 - Poster SessionTime: 10:30am - 12:00pm | Room: Gateway Foyer

4P.1 SystemResponsivenessVerificationoflargeMulti-ProcessorSystem ConfigurationsusingMicro-Benchmarks andaMulti-LevelAnalysisRalf Winkelmann - IBM Deutschland Research & Development GmbHEdward Chencinski - IBM Corp.Hanno Eichelberger - IBM Deutschland Research & Development GmbHMichael Fee - IBM Corp.Carsten Otte, Christoph Raisch - IBM Deutschland Research & Development GmbH

4P.2 Functional Coverage of Register Access via Serial Bus Interface using UVMDarko M. Tomusilovic

4P.3 NovelTestCaseDesignTechniquesforLogicalSpecificationsofSafetyCriticalSystems Software in Aerial VehicleLakshmi Kvns, Sanjeev Kumar - Advanced Systems Laboratory

4P.4 A Dyadic Transformation Based Methodology to Achieve Coverage Driven VerificationGoalSwapnajit Mitra - Broadcom Corp.

4P.5 AssertionbasedVerificationforAnalogand Mixed Signal Designs.Srinivas R. Aluri - Texas Instruments, Inc.

4P.6 EndtoEndFormalVerificationStrategiesforIPVerificationJacob R. Maas, Nirabh R. Regmi, Ashish Kulkarni, Krishnan Palaniswami - Microsoft Corp.

4P.7 SystematicSpeedupTechniquesforFunctionalCDCVerificationClosureAuthor order is Sulabh K. Khare, Ashish Hari, Anwesha Choudhary - Mentor Graphics (India) Pvt. Ltd.

4P.8 CoverageModelsforFormalVerificationXiushan Feng - Oracle LabsXiaolin Chen, Abhishek Muchandikar - Synopsys, Inc.

4P.9 Use of Portable Stimulus to Verify Task Dispatching Functions in an LTE DesignAdnan Hamid - Breker Verification Systems, Inc.

4P.10DebugAPIs-NextWaveofInnovationinDV SpaceSrinivasan Venkataramanan, Ajeetha Kumari - VerifWorks & CVC Pvt., Ltd.

Session Chair:Srivatsa Vasudevan - Synopsys, Inc.

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Session 4 - Poster SessionTime: 10:30am - 12:00pm | Room: Gateway Foyer

4P.11 System Level Fault Injection Simulation Using SimulinkWai Tang, Marcelo Mizuki, Fengying Qiao, Mitch Norcross - Melexis

4P.12 Transparent SystemC Model Factory for Scripting LanguagesRolf Meyer, Bastian Farkas, Mladen Berekovic,Syed Abbas Ali Shah - Technische Univ. Braunschweig

4P.13 Free Yourself from the Tyranny of Power StateTablewithIncrementallyRefinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey III, Rick Koster - Mentor Graphics Corp.Madhur Bhargava - Mentor Graphics (India) Pvt. Ltd.

4P.14IncreasedRegressionEfficiencywithJenkins Continuous Integration Before You FinishYourMorningCoffeeThomas Ellis - Mentor Graphics Corp.

4P.15Mixed-SignalVerificationMethodologytoVerifyType-CUSBVarun R, Vinayak Hegde, Somasunder Kattepura Sreenath - Cadence Design Systems, Inc.

4P.16 A Novel Approach to Create Multiple Domain Based DV Architecture to Address TypicalVerificationChallenges,fortheDUT with Mutual Exclusive Functionalities, Using UVM DomainsSubham Banerjee - Xilinx Inc.Keshava Krishna Raja Sooryambail - Cisco Systems, Inc.

4P.17 Automatic Debug Down to the Line of CodeDaniel Hansson, Patrik Granath - Verifyter AB

4P.18 A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, Wolfgang Ecker -Infineon Technologies AG & Technische Univ. München

4P.19 Power Aware CDC Analysis at Top Level Using SOC Abstract FlowPramod Rajan K S, Venkatesh Ranga - NXP Semiconductors

Special Session: Trends in Functional Verification: A 2016 Industry StudyTime: 10:30am - 11:00am | Room: Fir

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into design and verification trends at that point in time. However, after the 2004 study, no additional Collett studies were conducted. Three private functional verification studies were commissioned in 2007, 2010, and 2012. Although the data from these studies has been referenced in various publications and blogs, these studies were never officially published. To address this dearth of knowledge, two

new studies were commissioned in 2014 and 2016. The 2014 study was a world-wide, double-blind, functional verification study covering all electronic industry market segments. The findings from this study were published in the proceedings of the 2015 Design Automation Conference. The 2016 study followed the format of the 2014 study and is the focus of this invited talk. The findings from the 2016 functional verification study provide invaluable insight into the state of today’s electronics industry.

SpeakerHarry Foster - Mentor Graphics Corp.

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Sponsored Luncheon - Application Specific Verification from Edge Nodes through Hubs, Networks and Servers – Are the Requirements all the Same?Time: 12:00pm - 1:15pm | Room: Pine/Cedar

With the “Internet of Things” (IoT) connecting billions of “things”, all of them aggregating data through hubs and sending them through networks to cloud servers for big data analytics across different application domains, how does that change verification of the different components involved? Do the same flows and development requirements apply to designs that enable the cloud, networks, hubs and edge nodes? With the IoT spanning across a variety of application domains, how do those requirements play into verification?

After an introduction of the different application domains and how they relate to the IoT, the panel will discuss application specific aspects for verification of the different designs at the IP, Sub-system, Chip and System-level. Are the key drivers different? Is power optimization more critical in

some designs than it is in others? Are the design cycles forcing early software development and different forms of prototyping in some application areas more than in others? Are safety critical design flows as important in IoT edge nodes as in automotive?

Panelists:James Hogan - Vista VenturesChristopher Lawless - Intel Corp.David Lacey - Hewlett Packard EnterpriseFrank Schirrmeister - Cadence Design Systems, Inc.

Moderator:Ed Sperling - Semiconductor Engineering

Organizer:Frank Schirrmeister - Cadence Design Systems, Inc.


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Keynote: Tomorrow’s Verification Today Time: 1:30pm - 2:30pm | Room: Oak/Fir

Over the past decade, verification complexity and demands on engineering teams have continued to raise rapidly. However, the supporting automation tools and flows have been only improving incrementally, resulting in a verification gap. It is time to redefine how verification should be approached to accelerate innovation in the next decade.

In his presentation, Dr. Devgan will review the latest trends which are redefining verification from IP to System-level, with an increasingly application-specific set of demands changing the landscape for hardware and software development.

Biography: Anirudh Devgan serves as the Senior Vice President and General Manager of the Digital & Signoff Group (DSG) and System & Verification Group (SVG). As the leader of DSG, he is responsible for the core digital design, implementation, and silicon signoff business, which encompasses logic synthesis, formal verification, test, physical synthesis, place and route, electrical signoff, physical signoff, and design for manufacturing (DFM) technologies. In his role as leader of SVG, he is responsible for delivering the System Development Suite, including technologies from Advanced Verification Solutions featuring the Incisive® platform, hardware system verification

with Palladium®and Protium™ platforms, formal and automated verification with JasperGold®Apps, system-level design, and system verification solutions.

Prior to joining Cadence in 2012, Devgan spent seven years at Magma Design Automation as General Manager and Corporate Vice President of Magma’s Custom Design Business Unit, leading the development and introduction of several successful products. Prior to his tenure at Magma, he spent 12 years at IBM in various management and technical positions at the IBM Thomas J. Watson Research Center, IBM Server Division, IBM Microelectronics Division, and IBM Austin Research Lab, where he received numerous awards including the IBM Outstanding Innovation Award and IBM Outstanding Research Accomplishment. In 2003, he was awarded the IEEE/ACM William J. McCalla Award and in 2005, the ACM Design Automation Conference Best Paper Award. He was named an IEEE Fellow in 2006. Devgan has published more than 90 research papers and holds 27 U.S. patents.

Devgan received a bachelor of technology degree in electrical engineering from the Indian Institute of Technology, Delhi, and M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University.

SpeakerAnirudh Devgan - Senior Vice President and General Manager of the Digital & Signoff Group (DSG) and System & Verification Group (SVG)

Session 5 - UVM Register Layer ApplicationsTime: 3:00pm - 4:30pm | Room: Oak

Tips and Tricks for Using the UVM Register Layer.

5.1 Flexible Indirect Registers with UVMUwe Simm - Cadence Design Systems, Inc.

5.2 Modeling a Hierarchical Register Scheme with UVMJoshua Hardy - Pensar Development

5.3 DoingFunnyStuffwiththeUVMRegisterLayer: Experiences Using Front Door Sequences,Predictors,andCallbacksJohn Aynsley - Doulos

Session Chair:Stephen D’Onfrio - Paradigm Works, Inc.

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Session 7 - Coverage OptimizationTime: 3:00pm - 4:30pm | Room: Monterey/Carmel

Using Coverage to Optimize Verification.

7.1 Improving Constrained Random Testing by AchievingSimulationVerificationGoals through Objective Functions, Rewinding and Dynamic Seed ManipulationEldon G. Nelson - Intel Corp.

7.2 Optimizing Random Test Constraints Using Machine Learning AlgorithmsStan Sokorac - ARM, Inc.

7.3 Dynamic Regression Suite Generation UsingCoverage-BasedClusteringShahid Ikram, Jim Ellis - Cavium, Inc.

Session Chair:Harry Foster - Mentor Graphics Corp.

Session 6 - Exploring SystemVerilogTime: 3:00pm - 4:30pm | Room: Fir

6.1 Architecting “Checker IP” for AMBA protocolsAjeetha Kumari, Srinivasan Venkataramanan - VerifWorks & CVC Pvt., Ltd.

6.2 Is the Simulator Behavior Wrong for my SystemVerilog Code?Weihua Han - Synopsys, Inc.

6.3 Statically Dynamic or Dynamically Static? Exploring the Power of Classes and Enumerations in SystemVerilog Assertions for Reusability and Scalability

Sachin Scaria, Sreenu Yerabolu - Intel Corp Don Mills - Microchip Technology, Inc.

Session Chair:Dave Rich - Mentor Graphics Corp.

Looking at Interesting Aspects of the SystemVerilog Language.

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wednesday’s agenda


DVCon ExpoRoom: Bayshore Ballroom


10:00am - 12:00pm

8:00am - 10:00am

2:30pm - 6:00pm

12:00pm - 1:15pm

8:30am - 9:30am

1:30pm - 2:30pm

3:00pm - 4:30pm

2:30pm - 3:30pm

4:45pm - 5:00pm

5:00pm - 6:00pm

Session 8Virtual Platforms and High-Level LanguagesRoom: Oak

Session 9Formal Verification Case StudiesRoom: Fir

Session 10AMS VerificationRoom: Monterey/Carmel

Session 11UVM Registers at the System LevelRoom: Oak

Session 12Formal Verification ApplicationsRoom: Fir

Session 13Verification Reuse and DebugRoom: Monterey/Carmel

Sponsored LuncheonIndustry Leaders Verify with SynopsysRoom: Pine/Cedar

PanelUsers Talk Back on Portable StimulusRoom: Oak/Fir

PanelSystemVerilog Jinxed Half My Career: Where Do We Go From Here?Room: Oak/Fir

Best Paper & Poster Awards PresentationRoom: Bayshore Ballroom

DVCon ReceptionRoom: Bayshore Ballroom


dvcon expo

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1Panel: Users Talk Back on Portable StimulusTime: 8:30am - 9:30am | Room: Oak/Fir

DVCon is a global event for verification engineers to exchange ideas, identify new solutions or clever ways to better utilize existing tools in the design flow and, sometimes, commiserate. One of the more exciting areas in verification is Portable Stimulus, a standard means to specify verification intent and behaviors reusable across target platforms. It’s real, growing in adoption and promoted by Accellera’s Portable Stimulus Working Group (PSWG), an active group of users and EDA vendors. DVCon will be a showcase for PSWG’s efforts. Vendors will exhibit the latest Portable Stimulus software. A tutorial will summarize how portable stimulus is evolving technologically. Equally important is giving users a forum to share their perspectives on Portable Stimulus, many of whom are not represented on PSWG.

Topics include:

• What do users expect?

• What impact could Portable Stimulus have on chipdesign verification?

• Is Portable Stimulus evolving in a way that will suittheir needs?

• How urgent is the finalization of a PortableStimulus standard?

While the format will include a panel moderated by user advocate Adnan Hamid of Breker Verification Systems, audience participation will be encouraged. The audience should bring questions, concerns and gripes for a lively exchange of what is working in the verification space. Panelists will describe some of their biggest headaches related to tools, vendor support, standards efforts or budget. The goal is to provide constructive feedback to tool vendors, DVCon exhibitors and Accellera to ensure Portable Stimulus meets the needs of the verification community.

Panelists:Asad Khan - CaviumDave Brownell - Analog Devices, Inc.Mark Glasser - NVIDIA Corp.Wolfgang Roesner - IBM Corp.Sanjay Gupta - Qualcomm, Inc.

Moderator:Adnan Hamid - Breker Verification Systems, Inc.

Organizer:Nanette Collins - Nanette V. Collins Marketing and Public Relations

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Session 8 - Virtual Platforms and High-Level LanguagesTime: 10:00am - 12:00pm | Room: Oak

Moving Beyond SystemVerilog.

8.1 Automatic Exploration of Hardware/ Software PartitioningSyed Abbas Ali Shah, Sven A. Horsinka, Bastian Farkas, Rolf Meyer, Mladen Berekovic - Technische Univ. Braunschweig

8.2 Accelerated Simulation through Design Partition and HDL to C++ CompilationTheta Yang, Sga Sun - Advanced Micro Devices, Inc.

8.3 Micro-processorVerificationUsingaC++11 Sequence-BasedStimulusEngineStephan Bourduas, Chris Mikulis - Cavium, Inc.

8.4 Early Software Development and VerificationMethodologyUsingHybrid Emulation PlatformWoojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, Sukwon Kim - Samsung Electronics Co., Ltd.

Session Chair:Robert Troy - Cadence Design Systems, Inc.

Session 9 - Formal Verification Case StudiesTime: 10:00am - 12:00pm | Room: Fir

User Experiences with Formal Verification.

9.1 Making Formal Property VerificationMainstream: An Intel® Graphics Experience.Achutha Kiran Kumar V. Madhunapantula, Aarti Gupta, Bindumadhava S. Singanamalli, Abhijith A. Bharadwaj, Erik Seligman - Intel Corp.

9.2 UsingFormal-basedApplicationstoMakePristine IPsDavidCrutchfield, Lee Burns, Bob Metzler, Hithesh Reddy Velkooru - Cypress Semiconductor Corp.

9.3 Formal Proof for GPU Resource ManagementJia Zhu, Chuanqing Yan, Nigel Wang - Advanced Micro Devices, Inc.

9.4 EfficientandExhaustiveFloating PointVerificationUsingSequential EquivalenceCheckingTravis Pouarz - Mentor Graphics Corp.Vaibhav Agrawal - ARM, Inc.

Session Chair:Dan Benua - Cadence Design Systems, Inc.

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1Session 10 - AMS VerificationTime: 10:00am - 12:00pm | Room: Monterey/Carmel

Analog & Mixed-Signal Verification Using UVM (or not).

10.1 Machine Learning based PVT Space Coverage and Worst Case Exploration In AnalogandMixed-SignalDesign VerificationHonghuang Lin, Zhipeng Ye, Asad Khan - Texas Instruments, Inc.

10.2 Advances in RF Transceiver SoC Verification–AWalk-Throughovera 2.4GHzMulti-ModalIntegratedTransceiver VerificationCycleCharul Agrawal, Ashwin Vijayan, Jakub Dudek - Analog Devices, Inc.

10.3 Real Number Modeling of RF CircuitsJakub Dudek, Joshua Nekl, Keith O’Donogue - Analog Devices, Inc.

10.4 ConnectingUVMwithMixed-SignalDesignIvica B. Ignjic - Elsys Eastern Europe d.o.o.

Session Chair:Neyaz Khan - Maxim Integrated

Sponsored Luncheon - Industry Leaders Verify with SynopsysTime: 12:00pm - 1:15pm | Room: Pine/Cedar

Synopsys has worked with SoC leaders to define and deploy breakthrough technologies that not only increase the speed and throughput of verification (effectively lower the IT cost of verification) but also offer innovative approaches to avoid bugs altogether, detect them as early as possible and debug more efficiently. At this luncheon, you will

hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as discussions about the latest developments in the verification landscape and advanced technology.

Moderator:Piyush Sancheti - Synopsys, Inc.


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Panel: SystemVerilog Jinxed Half My Career: Where Do We Go From Here?Time: 1:30pm - 2:30pm | Room: Oak/Fir

SystemVerilog will be pretty close to 15 years old at the time of DVCon-2017 (the first rumblings on the eda.org email reflectors date from spring 2002). There are plenty of working verification engineers who have used little else. This panel session calls SystemVerilog’s hegemony into question from several viewpoints. Has it provided our industry with the best we could have wished for? Has the huge R&D investment by tool vendors been justified? What kind of language or environment can we look forward to as SystemVerilog’s ultimate replacement, and how much appetite does the industry have for any such change? A panel of expert users,

implementers and other stakeholders will bring their combined experience to this discussion. Expect strongly held views, radical alternative suggestions, and insights into how the needs of our industry will be served – and maybe not served – by our choice of programming languages.

Panelists:CliffCummings - Sunburst Design, Inc.Phil Moorby - Montana Systems, IncDave Rich - Mentor Graphics Corp.Arturo Salz - Synopsys, Inc.Adam Sherer - Cadence Design Systems, Inc.

Moderator:Jonathan Bromley - Verilab Ltd.

Organizer:Jonathan Bromley - Verilab Ltd.

Session 11 - UVM Registers at the System LevelTime: 3:00pm - 4:30pm | Room: Oak

Interesting UVM Register Applications.

11.1 One Stop Solution for DFT Register Modelling in UVMRui Huang - Advanced Micro Devices, Inc.

11.2 Yet Another Memory Manager (YAMM)Andrei Vintila, Ionut Tolea, Teodor C. Vasilache - AMIQ srlBecause this paper was previously presented at DVCon Europe, it is ineligible for the Best Paper award.

11.3 TacklingRegisterAliasingVerificationChallenges in Complex ASIC DesignShan Yan, Jie Wu, Jing Li - Broadcom Corp.

Session Chair:John Dickol - Samsung Austin R&D Center

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September 14-15, 2017 | DVCon-India.orgLeela Palace, Bangalore India

Join us in Bangalore for DVCon India!2017

TM

Session 12 - Formal Verification ApplicationsTime: 3:00pm - 4:30pm | Room: Fir

Formal Verification Applications.

12.1 Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky - Intel Corp.

12.2 Ironic ButEffective:HowFormalAnalysisCan Perfect Your Simulation ConstraintsPenny Yang - MediaTek, Inc.Jin Hou - Mentor Graphics Corp.Yuya Kao, Nan-Sheng Huang - MediaTek, Inc.Ping Yeung, Joe Hupcey - Mentor Graphics Corp.

12.3 AcceleratingCDCVerificationClosureonGate-LevelDesignsAnwesha Choudhury, Ashish Hari - Mentor Graphics (India) Pvt. Ltd.

Session Chair:Ambar Sarkar - eInfochips

Session 13 - Verification Reuse and DebugTime: 3:00pm - 4:30pm | Room: Monterey/Carmel

Optimizing Verification Through Reuse and Debug.

13.1 UVMInteractiveDebugLibrary–Speedupthe Debug Turnaround TimeHorace Chan - Microsemi Corp.

13.2 Making Legacy Portable with the Portable StimulusSpecificationMatthew Ballance - Mentor Graphics Corp.

13.3 Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of VerificationComponentsinAMBABasedSoC Design.Ieryung Park, Nara Cho, Yonghee Im - SK hynix Inc.

Session Chair:Josh Rensch - Superion Technology

Best Paper & Poster Awards PresentationTime: 4:45pm - 5:00pm | Room: Bayshore Ballroom2017 Recipients of the Best Paper and Poster are announced by Technical Program Chair, Tom Fitzpatrick.


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September 14-15, 2017 | DVCon-India.org Leela Palace, Bangalore India

DVCo

n In

dia

Join us in Bangalore for DVCon India!2017

TM

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THURSDAY’s agenda



8:30am - 12:00pm

2:00pm - 5:30pm

8:00am - 11:00am

12:15pm - 1:45pm

3:00pm - 4:00pm

Tutorial 4Reinventing SoC Verification – It Is about TimeRoom: Donne

Tutorial 5Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify My Rescue Drone’s RTL?Room: Siskiyou

Tutorial 7Optimizing IP Verification – Which Engine?Room: Donner

Tutorial 8Testbench Automation : How to Create a Complex Testbench in a Couple of HoursRoom: Siskiyou

Tutorial 6Practical Applications for Managing Low Power Verification Complexity and Debug of Advanced SoCsRoom: Cascade

Tutorial 9Formal Verification Methodology: Maximizing Productivity and Achieving Formal Closure With ConfidenceRoom: Cascade

Sponsored LuncheonEnterprise Verification Platform RequiredRoom: Sierra/Cascade








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Tutorial 4 - Reinventing SoC Verification - It Is about TimeTime: 8:30am - 12:00pm | Room: Donner

Let’s face it, at the end of the day projects are ruled by time and one of the leading stresses on project time is verification. It is time to take a fresh look at how we do verification, how we measure progress, and how we manage throughput. In this tutorial we will examine how to reinvent verification to best achieve end-to-end productivity, performance, and throughput using a goal-driven approach. This tutorial will introduce a metric-driven design flow for SoC development, spanning from proper definition of project goals, through the creation of portable stimulus that can be used for software-driven SoC verification across the various dynamic engines, formal verification, and planning and management automation.

What you will learn:

• New methodologies to drive throughput –software-driven testing, formaloptimization techniques

• New planning and management optimizations toimprove server farm utilization

• Attaching project based metrics management toyour test and coverage driven flow

• Utilizing formal technology at IP level and system-on-chip (SoC) level, beyond connectivity

Who should attend:

• Developers of SoC designs

• Verification engineers/leads responsible for IP,block, subsystem and system-level verification

• Verification managers and design managersresponsible for delivering quality SoCs on time

Speakers:Lawrence Loh - Cadence Design Systems, Inc.Larry Melling - Cadence Design Systems, Inc.Sharon Rosenberg - Cadence Design Systems, Inc.Frank Schirrmeister - Cadence Design Systems, Inc.Uri Tal - Cadence Design Systems, Inc.John Brennan - Cadence Design Systems, Inc.

Organizers:Larry Melling - Cadence Design Systems, Inc. Tom Anderson - Cadence Design Systems, Inc.


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Tutorial 5 - Stuck on a Desert Island without Simulation - Only Formal! How Do I Verify My Rescue Drone’s RTL?Time: 8:30am - 12:00pm | Room: Siskiyou

It could happen to any of us: your plane is stricken by mechanical failure and is forced on a desert island. Your only hope of rescue is to verify the RTL for a solar powered drone that will fly to the nearest civilization with your message. All you have for your EDA usage is a solar powered Linux laptop, your DUT’s RTL, some planning & management tools, and formal & CDC apps -- no simulation! The questions before you include:

How do you translate verification requirements into a machine-readable verification plan and related coverage goals?

• How do I create the corresponding “formaltestbench”?

• Are there any formal apps that can expedite orexpand the scope my verification?

• The drone’s FPGA design will call for multipleasynchronous clocks – will this be a problem?

• Is my drone’s RTL sensitive to any logicfaults, and how can I verify that the internalsafety mechanism handles them to avoid acatastrophic failure?

• How can I be confident that my verification iscomplete, and it is safe to launch the drone?

In this tutorial you will learn how to:

• Map your verification requirements to a humanand machine readable verification plan

• Select & run automated formal apps toexpedite your verification effort without writingany SVA code

• Setup a formal testbench and relatedverification methodology efficient propertychecking and analysis. This includes howto translate your requirements into SVAassertions, constraints, and “covers” that willbe optimized for formal analysis. Not all formalruns get a complete proof on the first pass, sowe will also share methodologies for dealingwith “inconclusives” and how to leverage“bounded proofs” to meet your verificationobjectives even if a formal proof isn’t obtained.

• Use formal-based CDC analysis to makesure none of the inter-clock domain signalsgo metastable

• Use formal to check your drone’s sensitivity tologic faults so it will endure its trip to civilization

• Close the verification loop by electronicallymapping all your progress back to youroriginal plan

Save yourselves and come to this tutorial!

Speakers:Joe Hupcey III - Mentor Graphics Corp.Mark Eslinger - Mentor Graphics Corp.Mitchell Poplingher- Microsemi Corp.Kartik Raju - Knowles Corp.


Organizer:Rebecca Granquist - Mentor Graphics Corp.

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Tutorial 6 - Practical Applications for Managing Low Power Verification Complexity and Debug of Advanced SoCsTime: 8:30am - 12:00pm | Room: Cascade

With the explosion in design complexity of advanced SoC designs, power management has become a key issue. Each new generation of consumer electronic devices is expected to have a longer battery life than before, and even compute servers now focus on reduced power consumption to lower cooling costs. In order to address the need for power optimization, SoC teams have adopted advanced low power design techniques for power management. However, these low power design techniques including: power gating, isolation, retention, standby etc., bring with them a unique set of challenges.

In this session, users will learn the latest advancements in power architecture specification, specifically complex power states, leveraging existing UPF standards and emerging low-power design methodologies. Users will also learn the recommended methodology and best practices for use at different stages in the design flow. Additionally, a panel of leading-edge SoC companies and Synopsys low power experts will discuss the new trends in next generation verification solutions. These solutions address the static and functional verification along with seamless debug of power managed designs, to enable advanced performance and accelerated turnaround times.

The following will be discussed in the tutorial, using real life examples:

• Accurately capturing power intent with IEEE1801for design implementation & verification

• SoC integration challenges with respect toPower State Tables (PST)

• Static checks for targeted verification at RTL,post synthesis and post-layout stages

• Advances in power aware RTL simulationaddressing new challenges

• Effective debug of low power violations withindustry leading solutions

• Methodology for IP to SoC validation

• Risks in hierarchical waiver management for lowpower verification

• Practical applications and industry bestpractices for low power design/verification

Speakers:Satya Ayyagari - Intel Corp.Vikas Gupta - Samsung Electronics America, Inc.YC Wong - Broadcom Corp.Amol Herlekar - Synopsys, Inc.Ankush Bagotra - Synopsys, Inc.


Organizer:Kiran Vittal - Synopsys, Inc.

Sponsored Luncheon - Enterprise Verification Platform RequiredTime: 12:15pm - 1:45pm | Room: Sierra/Cascade

To stay competitive in today’s electronics industry, it is critical that design projects periodically assess emerging functional verification trends. The knowledge gained through trend analysis will help you identify new opportunities with emerging solutions, mitigate risk, and spur innovation in your own processes. This session will discuss the

very latest in trends and provide you with valuable technology insights to address the requirements for a complete Enterprise Verification Platform.

Speakers:Harry Foster - Mentor Graphics Corp.Stephen Bailey - Mentor Graphics Corp.

Organizer:Rebecca Granquist - Mentor Graphics Corp.


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Tutorial 7 - Optimizing IP Verification - Which Engine?Time: 2:00pm - 5:30pm | Room: Donner

IP verification is too-often mistakenly tagged as a solved problem. The reality is that IP verification is plagued with a wide variation in effectiveness – the ability to confirm that new IP fulfils function, is of high quality, and is bug-free; and efficiency – the ability to assure IP quality in reasonable project timescales, and to be able to repeat easily when the IP is reconfigured for use in derivative designs. All of this is exacerbated by the fact that today, we’re dealing with IPs and subsystems as big as yesterday’s chips, and tomorrow’s IPs will be as big as today’s chips. In short, the barrier to realizing true IP reuse is verification, not design. This tutorial shares best practices and gives real actionable guidelines for how and where to apply UVM-based dynamic and formal verification engines, within a common metric-driven framework, to optimize IP verification efficiency and effectiveness.

Choosing the Appropriate Engine

We can optimize verification by knowing which IP blocks are best verified with formal and which are best done using UVM; based on design type, sequential depth and interface type to reduce the number of dynamic verification cycles needed. We offer practical guidelines for choosing the appropriate engine, and best practices for verification reuse based on that method. We also highlight verification IPs that can be used by multiple engines to streamline verification of common interface protocols. Further guidelines are given for optimizing dynamic and formal

regressions, maximizing compute-farm resources, and applying innovative bug-hunting techniques to attain greater confidence that IP is bug-free.

What you will learn:

• Best practices for rigorous reusable UVM-baseddynamic verification for IPs

• Practical methodologies to select and fully verifyIPs with formal verification

• New planning and management optimizations toimprove farm utilization

• How to apply formal and simulationcoverage results in a coherent metric-drivenverification flow

Who should attend:

• IP Developers

• Verification engineers/leads responsible for IP,Block, and Subsystem level verification

• Verification managers and design managersresponsible for delivering quality IPs and SOCson time

Speakers:Chris Komar - Cadence Design Systems, Inc. Meir Solomon - Cadence Design Systems, Inc.

Organizer:Pete Hardee - Cadence Design Systems, Inc.


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In 2014, the semiconductor industry passed an important milestone. For the first time, the average engineering team had more verification engineers than designers. This means that any improvement in the efficiency of verifications teams has a significant impact on overall project costs and time to market. In the past two decades, the industry has converged on two complementary strategies to verify increasingly complex SoCs : the reuse of testbenches from subsystem level to SoC level, and the use of advanced verification techniques such constrained random, assertions, and verification management. The key technology that enables these two strategies is the UVM. Despite its success and proliferation, experience shows us that there are two main problems with this approach. The first is that there is a learning curve associated with the adoption of UVM, and the second is that even for UVM experts, creating the necessary infrastructure, getting it up and running, and achieving coverage closure is a time consuming and error prone process. This tutorial introduces three new technologies which significantly reduce the time to create a reusable testbench infrastructure. These three technologies are integrated into a single comprehensive flow that significantly

improves the efficiency of the whole testbench creation process. In this tutorial, you will learn how to create a complex testbench that can be targeted at simulation or emulation in a couple of hours. •

You will learn:

• How to use the UVM-Framework code generationto rapidly build reusable testbench infrastructure

• How to use a VIP Configurator to shorten the bringup time for industry standard protocols

• How Portable Stimulus shortens the time to createefficient, systematic scenario-level stimulus

You will also hear from industry experts who have successfully used this testbench automation flow on their projects.

This tutorial is intended for verification engineers, architects and managers who are interested in making significant improvements to the overall efficiency of their verification process.

Speakers:

Matthew Ballance - Mentor Graphics Corp.Hans van der Schoot - Mentor Graphics Corp.Bob Oden - Mentor Graphics Corp.

Tutorial 8 - Testbench Automation : How to Create a Complex Testbench in a Couple of HoursTime: 2:00pm - 5:30pm | Room: SiskiyouOrganizer:

Rebecca Granquist - Mentor Graphics Corp.

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Holiday Inn Munich City CentreMunich, Germany

DVCon-Europe.org

join us in europe!October 16-17, 2017EUROPE

TM

2017Tutorial 9 - Formal Verification Methodology: Maximizing Productivity and Achieving Formal Closure With ConfidenceTime: 2:00pm - 5:30pm | Room: Cascade

Rapidly growing design functionality has an explosive impact on verification complexity. As a result of this growing complexity, verification teams are looking for innovative technologies that complement and accelerate their flows. The latest advances in formal verification are a powerful driver for this. In this tutorial, we will discuss how to use formal technologies for faster verification flows and the methodology for how to measure and achieve formal verification closure.

Industry experts from Qualcomm, Oski and Synopsys will use real world design scenarios to showcase how certain verification problems are extremely well suited to be solved with formal verification. These include applications such as Connectivity Checking, Register Validation, and Design Navigator. With these apps, users save significant time, effort and resources across all

design types and sizes (including SoC’s). In addition, the tutorial will provide guidance on a methodology for users to define and metrics to provide insight on coverage and provide confidence on formal verification closure and assess the completeness of their formal environment. Applications such as the Formal Testbench Analyzer and Formal Core provide the visibility and confidence needed for functional sign-off.

Speakers:Mandar Munishwar - Qualcomm, Inc.Vigyan Singhal - Oski Technology, Inc.Sean Safarpour - Synopsys, Inc.Pratik Mahajan - Synopsys, Inc.

Organizer:Prapanna Tiwari - Synopsys, Inc.


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Holiday Inn Munich City CentreMunich, Germany

DVCon-Europe.org

join us in europe!October 16-17, 2017EUROPE

TM

2017

Collaborate with vendors at the pinnacle of innovation! Learn about new, cutting-edge technology and network with vendors well-tuned to today’s

verification needs, and see how collaboration can take your design to the next level.

Welcome to the DVCon 2017 Expo!

BOOTH CRAWL

• Attend the Booth Crawl

• Get automatically entered into a drawing for a $500 Visa gift card

• Winner announced Monday at 6:45pm on the exhibit floor!(Must be present to win)

WIN $500!

THANK YOU TO OUR SPONSORS:

DVCON2017

C oc ktails

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4th Annual

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Monday, February 27: 5:00pm - 7:00pm Join us for the 4th Annual Booth Crawl!

Tuesday, February 28: 2:30pm - 6:00pm

Wednesday, March 1: 2:30pm - 6:00pm

DVCon 2017 Exhibitors

Exhibit Hours

DVCON2017

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* Denotes First-time Exhibitor

Agnisys, Inc. .................................................. 805

Aldec, Inc. ...................................................... 904

AMIQ EDA ...................................................... 405

Avery Design Systems, Inc. ......................... 304

Blue Pearl Software ................................... 1001

Breker Verification Systems ....................... 504

Cadence Design Systems, Inc. .................... 702

DINI Group .................................................... 604

Doulos ........................................................... 501

EDACafe.com ................................................ 801

HyperSilicon Co., Ltd.* .............................. 1004

InnovativeLogic, Inc. .................................... 505

Magillem Design Services* ......................... 602

MathWorks ................................................. 1002

Mentor Graphics Corp. .............................. 1101

OneSpin Solutions ....................................... 701

Oski Technology, Inc. ................................... 205

ProDesign Electronics .................................. 905

Real Intent, Inc. ............................................ 605

Runtime Design Automation* .................... 404

S2C Inc. .......................................................... 402

Sandstrom Engineering* ............................. 401

Semifore, Inc. ................................................ 502

Sigasi* ............................................................ 601

SmartDV Technologies ................................ 302

Synopsys, Inc. ............................................... 101

Test and Verification Solutions LLC ........... 901

Truechip Solutions Pvt. Ltd. ........................ 902

VeriFast* ....................................................... 301

Verific Design Automation .......................... 705

Verifyter ........................................................ 305

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Tuesday, February 28:2:30pm - 6:00pm

Wednesday, March 1:2:30pm - 6:00pm

Exhibitor Floor Plan

Networking ReceptionsOne of the main reasons you came to DVCon: NETWORKING! Introduce yourself and leave DVCon with a deeper professional network!

Monday, February 27: 5:00 - 7:00pm Join us for the 4th Annual Booth Crawl!

Tuesday, February 28: 5:00 - 6:00pm Networking Reception

Wednesday, March 1: 5:00 - 6:00pm Networking Reception

DVCON2017

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EMPLOYEE AREA

REGISTRATION

UP TOSECONDFLOOR

FOYERENTRANCE

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WOMEN MEN

SERVICE CORRIDOR

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Exhibitor Listing

Agnisys, Inc.Booth: 805www.agnisys.comAgnisys has products to take customers from Specification to Realization with certainty of functionality and time to market. IDesignSpec generates RTL, UVM, C/C++ API from registers/sequence specification. DVinsight is a smart editor purposefully built for SV/UVM based verification.Agnisys is now offering its Consulting and Training Services in SV/UVM/SystemC for SoC, ASIC, IP and FPGA in Design and Verification space.

Aldec, Inc.Booth: 904www.aldec.comEstablished in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design and Mixed-Language Simulation (VHDL, Verilog, SystemVerilog/UVM), FPGA-based Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, Embedded Development Kits, High-Performance Computing/Acceleration, DO-254 Functional Verification and Military/Aerospace solutions.

AMIQ EDABooth: 405www.amiq.comAMIQ EDA provides worldwide adopted software tools for hardware design and verification. Its solutions, DVT Eclipse IDE, DVT Debugger Add-On, Verissimo Linter, and Specador Documentation Generator, enable design and verification engineers to increase the speed and quality of new code development, simplify legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices. For further information visit: www.dvteclipse.com

Avery Design Systems, Inc.Booth: 304www.avery-design.com

Blue Pearl SoftwareBooth: 1001www.bluepearlsoware.comBlue Pearl Software, Inc., an industry leading provider of design automation software for ASIC, FPGA and IP RTL verification, offers Linting, debug, and CDC solutions proven to improve quality of results, accelerate RTL error find/fix rates while ensuring uniform coding styles. Blue Pearl provides out-of-the-box consistent results, easy setup, SDC generation, management dashboard views and runs on Linux and Windows.

Breker Verification SystemsBooth: 504www.brekersystems.comBreker Verification Systems is the Portable Stimulus leader, adding GPS to your verification. Compliant with the upcoming Accellera Portable Stimulus standard, Breker automates the generation of target-specific, multi-threaded tests cases, by taking as inputs a single, executable Graph-based, Portable stimulus or spec of your verification intent, Shareable across platforms and projects.

Cadence Design Systems, Inc.Booth: 702www.cadence.comCadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. For more information, visit www.cadence.com.

DINI GroupBooth: 604www.dinigroup.comLocated in La Jolla, California, Dini Group is a professional hardware and software engineering firm specializing in FPGA-based high performance digital circuit design and application development. We have products targeted to ASIC prototyping, High Performance Computing, Algorithmic Acceleration (including Data Center), and Low Latency Networking.

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Exhibitor Listing

DoulosBooth: 501www.doulos.comDoulos has set the industry standard for high quality training and KnowHow for over 25 years in design and verification languages and methodologies for system, hardware, and embedded software designers. The essential choice for 3500+ companies across 60+ countries, Doulos provides scheduled classes across North America and Europe, and delivers on-site and live online training worldwide. Find out more: www.doulos.com

EDACafe.comBooth: 801www.edacafe.comEDACafe.Com is the #1 EDA web portal. Thousands of IC, SoC, FPGA, PCB, System designers and top level decision-makers visit EDACafe.Com daily to learn about the latest industry trends, design tools and services. Sign up for the industry’s best daily newsletter at www10.edacafe.com/nl/newsletter_subscribe.php.

HyperSilicon Co., Ltd.Booth: 1004www.hypersilicon.comHyperSilicon is one of the leading suppliers of FPGA based rapid system prototype and desktop emulator for SoC design industry. We provide flexible, reliable SoC/ASIC verification platform, fastest desktop emulator and FPGA based customizing design services. With over 10 years in SoC/ASIC verification market, we have built excellent long term partnership with an impressive number of customers worldwide, like Huawei, AMD and Fujitsu etc.

InnovativeLogic, Inc.Booth: 505www.inno-logic.comInnovative Logic is the leading provider of ASIC, FPGA, Firmware, Software & IT services and Soft IP. We have very flexible model to offer on-site, offsite or turnkey solutions to our customers. We also provide complete soft IP solution that includes source code, verification environment, firmware, documentation, prototyping and extensive support to ensure that you have successful product. We are in business of offering the best quality services and soft IP to many Fortune 500 companies for last 10 years.

Magillem Design ServicesBooth: 602www.magillem.comMagillem is a leading EDA software provider. Internationally renowned, we are present in 12 countries. 90% of our turnover is realized in the export. Our innovative solution, introducing a XLM-based collaborative platform, supports our customers’ R&D from specification of their product to the documentation, and connects all business experts, especially in IoT and embedded systems’ domain.

MathWorksBooth: 1002www.mathworks.comMathWorks is the leading developer of mathematical computing software. Engineers and scientists worldwide rely on its products to accelerate the pace of discovery, innovation, and development. MATLAB and Simulink are used throughout the automotive, aerospace, communications, electronics, and industrial automation industries as fundamental tools for research and development. They are also used for modeling and simulation in increasingly technical fields, such as financial services and computational biology. For more information visit www.mathworks.com

Mentor Graphics Corp.Booth: 1101www.mentor.comMentor Graphics delivers the most comprehensive Enterprise Verification Platform™ (EVP), delivering performance and productivity improvements ranging from 400X to 10,000X. Tightly integrated combining Questa® for high performance simulation, verification management and coverage closure, low-power, CDC & Formal Verification, Veloce® for hardware emulation and HW/SW system verification, Catapult® for High-Level Synthesis, PowerPro® for RTL Low-Power unified with the Visualizer™ debug environment.

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Exhibitor Listing

OneSpin SolutionsBooth: 701www.onespin-solutions.comOneSpin Solutions, a leader in formal verification, is creating the industry’s most advanced formal platform, encompassing agile design evaluation, coverage-driven ABV, and automated DV apps. The world’s leading electronics companies partner with us to pursue design perfection in areas where reliability really counts: safety-critical verification, SystemC/C++ HLS code analysis, and FPGA equivalence checking. OneSpin: Making Electronics Reliable

Oski Technology, Inc.Booth: 205www.oskitechnology.comOski Technology has established itself as the unsurpassed global leader in the domain of formal verification methodology and services. Founded in 2005, Oski serves six out of the top seven semiconductor design companies, yielding accelerated verification schedules and higher quality designs than what is possible through simulation alone. Visit us at DVCon and discover how we can help with your design.

ProDesign ElectronicsBooth: 905www.profpga.comProDesign Electronics products and services include the proFPGA family of ASIC Prototyping and FPGA systems. The proFPGA system is a complete, scalable and modular multi FPGA solution, which fulfills highest needs in the area of FPGA based Prototyping. It addresses customers who need a scalable and most flexible high performance ASIC Prototyping solution for early software development and real time system verification.

Real Intent, Inc.Booth: 605www.realintent.comReal Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.

Runtime Design AutomationBooth: 404www.rtda.comRuntime, headquartered in Santa Clara, California, is the leading supplier of high-performance computing infrastructure and workflow optimization solutions, dramatically improving resource utilization and efficiency, enabling faster time to market for our customers. Our family of high-performance schedulers offer optimum performance for all aspects of design verification including simulations (NetworkComputer), full-chip regressions (WorkloadXelerator) and hardware emulation (HERO). For more information, visit www.rtda.com.

S2C Inc.Booth: 402www.s2cinc.comS2C has been successfully delivering rapid SoC prototyping solutions since 2003. Our portfolio includes prototyping hardware and automation software, IP, and system-level design verification and acceleration tools. With over 200 customers and more than 800 systems installed, S2C systems have been deployed by leaders in consumer electronics, communications, computing, image processing, data storage, research, defense, education, automotive, medical, design services, and silicon IP. For more information, visit www.s2cinc.com.

Sandstrom EngineeringBooth: 401www.sandstrom.orgUVM doesn’t need to be drinking-from-a-firehose complicated. I’ve developed techniques to simplify the UVM bloatware while still being UVM compliant. I demystify the entire UVM environment and development.

Semifore, Inc.Booth: 502www.semifore.comSemifore Inc. provides the CSRSpec language and the CSRCompiler, a complete register design solution for hardware, software, verification, and documentation. Collaboratively manage your design from a single source specification. CSRSpec, SystemRDL, IP-XACT, or Spreadsheet inputs generate: Verilog and VHDL RTL; Verilog, or C headers; Perl, IEEE IP-XACT, UVM, HTML web pages, and Word or Framemaker documentation.

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Exhibitor Listing

SigasiBooth: 601www.sigasi.comSigasi radically redefines digital design. Our design entry tool, Sigasi Studio, drastically improves hardware designer productivity by helping to write, inspect and modify digital circuit designs in the most intuitive way. Advanced features such as intelligent autocompletes and code refactoring, make VHDL and SystemVerilog design easier, more efficient. Sigasi was founded in 2008 and has customers worldwide in all fields of industry.

SmartDV TechnologiesBooth: 302www.smart-dv.comSmartDV creates standard and custom verification intellectual property (VIP), memory models and simulation acceleration VIPs designed to work with coverage-driven verification flows. All SmartDV VIPs ship with compliance test-suite and comprehensive functional coverage models. All VIPs are native UVM or language of customer choice. For more information on SmartDV’s products, see www.smart-dv.com/products.html

Synopsys, Inc.Booth: 101www.synopsys.comSynopsys delivers comprehensive verification solutions spanning the complete design cycle, including simulation, emulation, advanced debug, static/formal verification, FPGA-based prototyping and virtual prototyping. Synopsys’ Verification Continuum combines best-in-class technology, verification IP, and advanced methodologies enabling users to address rapidly escalating SoC complexity, accelerate time-to-market, and bring innovative products to market sooner.

Test and Verification Solutions LLCBooth: 901www.testandverification.comT&VS provides hardware verification and software testing products and services to the worldwide semiconductor and embedded systems industries to help improve their product time-to-market and quality. T&VS applies well proven methodologies, tools and processes to ensure the thoroughness of the verification, generating metrics to track progress and enable a go-to-market decision thus enabling our customers to focus their R&D resources on feature development rather than QA.

TRUECHIPBooth: 902www.truechip.netTruechip is a leading provider of Verification IP Solutions. Truechip has enabled its customers to bring superior products to market with reduced cost and time-to-market.All Truechip VIPs come with Spec-tagged features and Testplan for the robust Verification of Design. Truechip’s portfolio of Verification IPs includes USB, PCIe, Ethernet, Memory, Display, AMBA, MIPI VIPs. For more details visit us at www.truechip.net.

VeriFastBooth: 301www.verifasttech.comVeriFast Technologies is a Design Verification company specializing in Training and Consulting with a focus on the latest technologies such as SystemVerilog and UVM. Our training courses are offered in an online learn-as-you-go format complete with state of the art Questa tools from Mentor Graphics. Add horsepower to your project by adding our DV engineers to your team.

Verific Design AutomationBooth: 705www.verific.comSupport your own RTL tools with Verific’s industry standard (System)Verilog, VHDL, and UPF parsers ! Verific Design Automation has provided (System)Verilog and VHDL front-ends to EDA, FPGA, and semiconductor computers for many years. With more than 60 active licensees worldwide, Verific’s parsers are found everywhere. And all our APIs are available in Python, Perl, and C++.

VerifyterBooth: 305www.verifyter.comVerifyter was founded 2010 with the mission to transform the development process by automating debug of regression test failures, especially targeting the ASIC market. PinDown, Verifyter’s automatic debugger, is currently used by both ASIC and ASIC IP companies and has proven to speed-up the bug fixing cycle by up to 400% and bring in the project release date by as much as 10%.

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*Note Exhibitor Listing as of January 30, 2017

Thank You to Our Event Sponsors

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Dvcon expo

Exhibiting Companies

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*Note Exhibiting Companies as of January 30, 2017

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