universal reconfigurable processing platform for space rev voice4
DESCRIPTION
MAPLD 2009 Presentation of a universal reconfigurable multi processor hardware platform for spaceTRANSCRIPT
Universal Reconfigurable Processing Platform for Space
Presented by Dorian Seagrave
Gordonicus LLC
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Introduction An increasing number of spacecraft system engineers and scientists are demanding:
More processing power Flexible architecture Standard / COTS communication interfaces Multiple Mission Modes / Reconfigurability Small form factor Mission hardware reuse Low power High speed SERDES High Reliability
• Reconfigurable State-of-the-Art High Speed Data Processing Capabilities
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Features
STS125 Mission
No blind and buried viasFlight Board meets NASA and IPC 6012 class 3 standards
• 1553• 100 Mb Ethernet • 200 Mb Spacewire routers• COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2
This hardware platform provides these needs by combining:
• A Rad Hard LEON3FT Processor• 1 Gbyte protected SDRAM
Aeroflex
LEON3FT
UT699
Aeroflex
LEON3FT
UT699
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LEON3FT Processing Applications Guidance, Navigation and Control (GNC) Control and Data Handling (CDH) Xilinx Monitoring and Reconfiguration
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Xilinx Processing Applications High Speed DSP Algorithm Processing Image Processing Pose Estimation Algorithms Communications / Radio Data Encryption / Decryption Waveform Processing Instrument Data Validation and Compression Application Reconfigurable While in Flight
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SPECIFICATIONS5 PROCESSORS
LEON3FT ASIC AeroFlex UT699 SPARCTM V8/LEON
3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg
4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO)
STANDARD I/O INTERFACES
10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations
CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors
Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP
CONSOLE PORT LEON3FT UART Rate configurable
FRONT PANEL DEVELOPMENT / DEBUG PORTS
DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet portDEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port JTAG
MEMORY
1 GByte SDRAM Reed Solomon Protected corrects for 2
nibble upsets8 GByte FLASH stored in two banks16 Gbit SDRAM 4Gbits per PPC4052 MBbyte SRAM Protected (Self Scrubbing)32 KByte PROM
CONFIGURABLE I/O
10 RS422/LVDS Transmit Ports Xilinx configured (Quad redundant)
10 RS422/LVDS Receive Ports Xilinx configured (Quad redundant)
39 Xilinx Backplane I/O12 Actel I/O2 LEON GPIO2 Backplane Spacewire Backplane Ethernet
SMALL SIZE
DIMENSIONS
Standard 3U cPCI Single slot front panel configuration
supports: 4 SpaceWire, 1553 A/B , Console port and Debug.
Dual slot front panel configuration supports additional SpaceWire ports.
LOW POWER
LEON3FT 2.5Volt CoreXilinx 1.2Volt Core
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LEON3FT PROCESSOR & MEMORY
LEON 3FT
AeroFlex UT699 SPARCTM V8 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-
cm2/mg
MEMORY
1GByte SDRAM Reed Solomon Protected
corrects for 2 nibble upsets8GByte FLASH Stored in two banks2MBbyte SRAM Protected (Self Scrubbing)32KByte PROM
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LEON3FT PROCESSOR & MEMORY
LEON3FTAeroflex UT699
2MByte SRAM(Internal EDAC)
32KB PROM
1GByte SDRAM(Reed Solomon)
4GByte FLASH
Actel RTAX
TID: 300 krad (Si)SEL Immune >110 MeV-cm2/mg
52.8 MIPS
4GByte FLASH
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Xilinx QV4 FX60 FPGAs & MEMORY
Quad redundant or independent PPC processing
Mixed operating systems Partial or Full reconfiguration
CONFIGURABLE LOGIC per FX60
Logic Cells: 56,880 Slices: 25,880 Distributed RAM: 395kb XtremeDSP Slices: 128 Block RAM: 4,176Kb
EMBEDDED PowerPC 405 350 MHz operation 16 KB instruction cache 16 KB data cache 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO)
MEMORY 16Gbit SDRAM 4Gbits per PPC405
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Xilinx QV4 FX60
PPC405
PPC405
Xilinx QV4 FX60
XILINX PPC405 PROCESSORS & MEMORY
PPC405
512MByte SDRAM
200Mbps SpaceWire(4)
Dual Xilinx QV4 FX60
PPC405700 DMIPs
TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mgSEFI: 1.5E-6 Upsets/device/day (GEO)
512MByte SDRAM
512MByte SDRAM
512MByte SDRAM
LEON3FTAeroflex UT699
Based on Heritage Architecture Implementation
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Xilinx DSP Processing Architecture
PPC1
PPC3
PPC0
PPC2
• 4 Designs = Quad Redundant or Single Strand• 2 Designs = 1 Design per Xilinx • 1 Design TMRed using both Xilinx
Flexible Design Options :
Node Interconnections
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Xilinx Reconfiguration
A Singe Node can be reconfigured with
PPC1
PPC3
PPC0
PPC2
Bottom Xilinx QV4 FX60
Top Xilinx QV4 FX60
Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric.
Control LogicSDRAM SelectMap
•PPC Operating system•PPC application code or •Xilinx fabric reconfiguration
WITHOUT disruption to the other nodes
FLASH
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STANDARD INTERFACES
CompactPCI Console Port Async UART 1553 SpaceWire
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CompactPCIMIL-STD-1553 A/B LEON3FT Console Port
Actel RTAX2000
LEON3FT
AMBA BUS AMBA BUS
1553 A/BTransceiver
Aeroflex UT63M143
AMBA 1553 Core
FRONT
PANEL
MIL-STD-1553 A/B
cP
CI
CO
NN
EC
TO
RS
32 Bit 33 MHz
CompactPCI
LEON RS422 Console Port
AMBA Bus Bridge via
LEON Memory Bus
READY
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SpaceWire Ports
LEON3FT
SpW Router 5 Port
SpW Router 5 Port
RTAX
200Mbps Configurable
200/100/50 Mbps200Mbps
Front Panel Conn. Thru-hole Jumpers
FRONT PANEL
CPCI
P2
Xilinx
200Mbps
10 Front Panel
4 Backplane
2 Backplane via Jumpers
200Mbps Configurable
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Configurable I/O
What if my instrument interface is not SpaceWire?
What if I need a custom interface on the backplane? ie: I2C
What if I forgot to add a control line to a device?
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LVDS OR
RS422
73 User Defined I/O
LEON3FT
FRONT PANEL
CPCI
P2
Xilinx
39 User Defined I/O
LVDS OR
RS422
LVDS OR
RS422
LVDS OR
RS422
LVDS OR
RS422
Sync / Async Serial IF I2C 1 Wire Protocol
10 Bi-Dir User Defined I/O
2 GPIO
ACTEL
12 User Defined I/O
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Development & Debug Ports LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) LEON and Xilinx Ethernet ports can be connected LEON Dedicated Debug Port (DSU) Xilinx I/O to be used as serial ports Xilinx JTAG LEON JTAG ACTEL JTAG
All Debug / Development ports are accessible from the front panel.
Facilitates Hardware Reuse
GSE reconfiguration without opening the box
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RTAX 2000 CONFIGURATIONS
CG624 Package Supports ALDEC RTAX development Suite.
Flexible architecture using Gaisler/Aeroflex Cores
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RADCLK
33MHz66MHz
100MHz
LEON_3FT66MHz
Ethernet MII
SpaceWire
SpaceWire
SelectMAP
4 GByteFLASH
2MB_ EDACSRAM
ACTELRTAX2000
CG624
4 GByteFLASH
Data
cPC
I
DebugSerial Port & JTAG
32KROM
23Kx8
512MB
SDRAM256Mx16
Xilinx1a Xilinx1b Xilinx2a Xilinx2b
RS 422 Outputs
RS 422 Inputs
66MHz33MHz
Addr
1553Driver
1553Transformer
1553Transformer
1GB_ EDACSDRAM
256Mx48
RS 422 Console Port5 Port SpW
Router
5 Port SpW Router
SpaceWire
LVDS / RS422 Front Panel Transceivers
8 RX8 TX
2 Backplane GPIO
200MHz
12 Backplane GPIO
512MB
SDRAM256Mx16
512MB
SDRAM256Mx16
512MB
SDRAM256Mx16
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
Eth
erne
t MII
(P2) 39 Backplane I /O
Front Panel & Backplane
(2 Backplane)
PPC 405uP
512MB PPC 405uP
512MB PPC 405uP
512MB
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Application
LEON3FT RTAX SpW Router
DownLink0
PPC 405uP
512MB
SpaceWire
SpaceWireSpW Router
DownLink1
MissionCrd0
MissionCrd1
MissionCrd2
MissionCrd3
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Availability
Contact Aeroflex Colorado Springs
Future ….
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Xilinx SIRF V5
Xilinx SIRF V5
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Next Effort
LEON3FT 16 MBytes EEPROM8 Port SpW Router16 GBytes FLASH1 GByte SDRAM15533U cPCI
Gordonicus LLC www.gordonicus.com
Hardware
Gordon Seagrave [email protected]
Dorian Seagrave [email protected]
Software
Peter Cavender [email protected]
John Gemmill [email protected]
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