K.J. Somaiya Institute Of Engineering And

Information Technology, Sion, Mumbai-22.

Project Report On Workshop .

Submitted By:

Kirti Palekar.

Suchita Deb.

Abhishek Gajra.

Academic Year : 2009-2010.

Student Information.

Sr. No. Topic Information1. Student name Kirti Palekar

Suchita debAbhishek Gajra

2. Address C-3/19, Rajawadi Colony, Chitranjan Nagar,

Ghatkopar(E), Mumbai-7731/C/8, Navjivan Society,

Chembur, Mumbai-74402, Sai Flora, Sai Complex, Navghar Road, Mulund(E),

Mumbai-813. Phone No. 9870562438

99207603639773312753

4. Email Palekar.kirti@gmail.comsuchitadeb@rocketmail.co

mabhishekgajra@gmail.com

The Above Information Given Is In With Respect To The Order Of The Group Members.

Acknowledgement

A Vote Of Thanks To Our Beloved Electronics Workshop Incharge And Our Parents Who Have Encouraged Us In Preparing This REPORT…

I Would Also Like Thank Our College As Well As The Teachers, Especially Electronics Branch’s Professors. Because Of Which We Got An Excellent

Opportunity To Show Our Skills And Also Our Talent…

Table Of Contents

1. Major Project (Analog Project).

2. VHDL Project (Digital Project).

Major Project

Fastest finger first

Components List

Circuit Diagram Of Fastest Finger First.

VHDL diagram

Thank

You

Technical Specification

Circuit Layout

Assembly Layout Of Main Board

Circuit Explanation & General Description

References

www.google.com

www.allaboutcircuits.com

www.vegakitindia.com

www.wikiepedia.com

VHDL Project

Sequence Detector

(Mealy

Machine)

Introduction

VHDL is the VHSIC HARWARE DESCRIPTION LANGUAGE. VHSIC is an abbreviation for VERY HIGH SPEED INTEGRATED CIRCUIT.

It can describe the behavior &structure of electronic systems, but is particularly suited as a language to describe the structure & behavior of digital electronic hardware(h/w) designs, such as ASICs & FPGAs as well as conventional digital circuits. VHDL is an international standard, regulated by the IEEE. Simulation & synthesis are the 2 main kinds of tools which operate on the VHDL language.

VHDL allows designs to be described using any methodology-top down, bottom up or middle out! VHDL can be used to describe h/w at the gate level or in a more abstract way.

Design

VHDL is a fairly general-purpose language,& it doesn’t require a simulator on which to run codes. There are many VHDL compilers, which build executable binaries. It can read & writefiles on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design developed. Because of this general-purpose nature, it is possible to use VHDL to write atestbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with user & compares results with those expected.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than d-type f/f as storage elements.

VHDL is not a case sensitive language. One can design h/w in a VHDL IDE (such as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software (such as ModelSim) which shows the w/f of i/ps & o/ps of the circuit after generating the appropriate testbench. To generate an appropriate testbanch for a particular circuit or VHDL code, the i/ps have to be defined correctly. For eg), for i/p, a loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described

(modeled) & verified (simulated) before synthesis tools translate the design into real h/w (gates & wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C & assembly code which all run sequentially, one instruction at a time.

A final point is that when a vhdl model is translated into the “gates & wires” that are m,apped onto a programmable logic device such as a CPLD or FPGA, then it is the actual h/w being configured, rather than the VHDL code being “executed” as if on some form of a processor chip.

Getting Started

Although background in a computer programming language (such as c & c++) is not essential. Free VHDL simulators are readily available & although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user’s goal is to learn RTL coding (i.e. design h/w circuits[ckt] in VHD, as opposed to simply document or simulate ckt behavior), then a synthesis/design package is also needed.

As with VHDL simulators, free FPGA synthesis tools are readily available & are more than adequate for independent study. Feedback(f/b) from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design i/p methods, such as block-diagram (schematic) & state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures or complex state-transition diagrams. Finally, the included tuturials & e.g. are valuable aids.

Nearly all FPGA design &simulation flows support both VHDL & Verilog, another h/w description language, allowing the user to lear n either or both languages.

Sequence Detector

If a given i/p sequence is detected using a state diagram then it is called as a sequence detector. In sequence detector the o/p goes to high, when given sequence is detected. There are 2 types of sequence detector. Namely :-

1). Non Over Lapping Sequence Detector:

In this type of sequence detector on the completion of the sequence state diagram will go back to the starting state.

2). Over Lapping Sequence Detector:

In this type of sequence detector, on completion of the seq the state machine goes to the state which detects the over lapping part.

Even it is further classified considering its o/p. Namely :-

1).Mealy Sequence Detector:

If the o/p of the system is directly depended on the actual i/p then the system is said to be mealy system.

2).Moore Sequence Detector:

If the o/p of the system is not directly depended on the actual i/p then the system is said to be moore system.

Here we have used Mealy Machine as the sequence detector.

Code For Sequence Detector “1011” (Mealy Machine)

Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;

Entity mealy isPort (x: in bit;

Reset: in bit;Clk: in bit;Z: out bit);

End mealy;

Architecture behavioral of mealy isType state is (a,b,c,d);Signal nxt, present : state;

BeginReg: process (clk, reset)

Begin If reset=’1’ then

Present<=a;Elsif (clk’event and clk=’1’) then

Present<=nxt;End if;

End process;Logic: process (present,x)Begin

Z<=’0’;Case present is

When a=>If x=’0’ then

Nxt<=a;Else

Nxt<=b;End if;When b=>

If x=’0’ thenNxt <=c;

ElseNxt<=b;

End if;When c=>

If x=’0’ then Nxt <=a;

Else

Nxt<=d;

End if;When d=>

If x=’0’ thenNxt <=c;

ElseNxt <=b;

End if;End case;

If present=d and x=‘1’ thenZ<=’1’;

End if;End process;End behavioral;

Block Diagram OF Sequence Detector

Output Waveform

Block Diagram Of Fastest Finger First.

List Of Figures

1). Photocopy Of F.M. Transmitter.

2). Block Diagram Of F.M. Transmitter.

3). Circuit Diagram Of F.M. Transmitter.

4). Circuit Layout Of F.M. Transmitter.

5). Assembly layout Of F.M. Transmitter.

6). Circuit Diagram Of Sequence Detector.

7). Output Waveform Of Sequence Detector.

Source Code.

Applications Of Sequence Detection

Data Sheets Of The

Components Used