university science instrumentation centre

8/10/2019 University Science Instrumentation Centre

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UNIVERSITY SCIENCE INSTRUMENTATION CENTRE

(USIC)

JVD COLLEGE OF SCIENCE AND TECHNOLOGY,

ANDHRA UNIVERSITY

M.Sc(Tech.) VLSI Design( !!" # $$)

DETAILED SYLLABUS

Course duration: 3 yearsNo of semesters: 6



Semester 1



VL $!$ % A&&'ie *+he *+ics $

VL $! % A *nce igi+*' s-s+e esign C/ &0+e1 *1chi+ec+01e

VL $!2 % 31/g1* ing c/nce&+s C '*ng0*ge

VL $!4 % De ice / e''ing

VL $!5 % 31*c+ic*' C &1/g1* ing '*6



(VL !$ # A&&'ie *+he *+ics )

$. S3ECIAL FUNCTIONS :Bessel’s equation – Bessel functions, Legendre’s equation- Legendre polynomials,Roadridue’s formula - recurrence relations – Generating functions & Orthogonal roperty forBessel’s !unction of the !irst "ind#

. FUNCTIONS RELATIONS AND GRA3H THEORY$ypes of functions, in%erse functions and composition of functions, relations and their

properties Graph $heory: ntroduction and types of graphs, 'asic terminology, representationof graphs and graph isomorphism# (onnecti%ity, paths, indirect and undirected graphs andisomerism#

2. CALCULUS AND VARIATIONSntroduction, functionals, )uler’s equations, solutions of )uler’s equations, soperimetric

pro'lems, se%eral dependent %aria'les, !unctional in%ol%ing higher order deri%ati%es,*ppro+imation solutions of 'oundary %alue pro'lems, Rayleigh – Rit ethods – Galer"inmethod#

4. LINEAR INTEGRAL E7UATIONS 3RO8A8ILITY THEORYntroduction definition, different "inds of integral equations, !redholm and .olterra integral

equations, con%ersion of a linear differential equation to an integral equation and %ice-%ersa,Green’s functions, solutions of !redholm equations and !redholm integral equations 'y themethod of successi%e appro+imations#

5. Basic terminology, concept of pro'a'ility, additi%e la/, multiplicati%e la/ and 'ayerstheorem 0/ith out proof1 Random %aria'les, classification of random %aria'les, discrete andcontinuous random %aria'les#

9. 2istri'ution functions, conditional distri'ution functions and their properties# oments of arandom %aria'le and generating functions#(orrelation coefficient Basic distri'utions:Binomial, poision and normal distri'ution and momentum generating functions

Te:+ 8//;s<2iscrete athematics and its *pplications 'y 3enneth#4#Rosem, $ata cGra/ u'lications,

5e/ 2elhi .(Uni+%II)

ro'a'ility $heory and 6tochastic process 'y #6anthos'a'u and 2# alathi 2e%i, 67R)u'lications 8!ormerly 6pectrum u'lications9 -;-<<=, 5alla"unta, 4ydera'ad->># (Uni+%IV)

4igher )ngineering athematics 'y B 6 Gre/al# ( Uni+%I,Uni+%III, Uni+%IV)



(VL ! # Digi+*' sign*' &1/cessing)

$. DISCRETE # TIME SIGNALS AND SYSTEMS <6ampling of *nalogue signals-Basic sequences and sequence operations- aliasing –standard discrete time signals – classification – discrete time systems – Linear timein%ariant sta'le casual discrete time systems – classification methods – linear andcircular con%olution – difference equation representation – 2!6, 2$!$, 2!$ – !!$computations using 2 $ and 2 ! algorithms# ?-transforms and its properties – n%erse?- transforms-$ime response and frequency response analysis of discrete timesystems to standard input signals#

S+10c+01es =/1 Disc1e+e%Ti e S-s+e s<6ignal flo/ graph representation of linear constant coefficient difference equations#Basic R structures# $ransposed forms# Basic structures for ! R systems# O%er%ie/of finite-precision numerical effects#

. INFINITE IM3ULSE RES3ONSE DIGITAL FILTERS<Re%ie/ of design of analogue Butter/orth and (he'yshe% !ilters, !requencytransformation in analogue domain – 2esign of R digital filters using impulsein%ariance technique – 2esign of digital filters using 'ilinear transform – pre /arping

– !requency transformation in digital domain – Reali ation using direct, cascade and parallel forms#

2. FINITE IM3ULSE RES3ONSE DIGITAL FILTERS<6ymmetric and *nti symmetric ! R filters – Linear phase ! R filters – 2esign using!requency sampling technique – @indo/ design using 4amming, 4anning andBlac"mann @indo/s – (oncept of optimum equiripple appro+imation – Reali ationof ! R filters – $rans%ersal, Linear phase and olyphase reali ation structures#

4. FINITE >ORD LENGTH EFFECTS <Auanti ation noise – deri%ation for quanti ation noise po/er – !i+ed point and 'inaryfloating point num'er representations – (omparison – O%erflo/ error – truncationerror – coefficient quanti ation error – limit cycle oscillations- signal scaling –analytical model of sample and hold operations#

5. S3ECIAL TO3ICS IN DS3<2iscrete Random 6ignals- ean, .ariance, (o-%ariance and 62 – eriodiogram(omputation – rinciple of ulti rate 26 – decimation and nterpolation 'y integerfactors – $ime and frequency domain descriptions – 6ingle, ulti stage, polyphasestructures – A ! filters – 6u' 'and (oding

TE?T 8OO@<;# ohn G# roa"is and 2imitris G# anola"is, C2igital 6ignal rocessing, *lgorithmsand *pplications C, 4 of ndia Ltd#, 5e/ 2elhi < rd )dition DDD#

REFERENCES<;# 6anEit 3# itra C2igital 6ignal rocessing’, * (omputer Based *pproach, $ata

cGra/-4ill, 5e/ 2elhi, ;FF=##*llan # Oppenhein & Ronald @# 6chater , H2igital 6ignal rocessingI, 4 , DD>#

<# # R# hohnson, J ntorduction to 2igital 6ignal rocessingI, 4 , DDD#># 6ignal processing 'y B# # Lathi



(VL !2 # S-s+e / e'ing 0sing VHDL Ve1/'ig)

$. 8ASICS OF VHDL<ntroduction to .42L - Le%els of a'straction - 2esign !lo/

. LANGUAGE FUNDAMENTALS<Basic code structure of .42L - Le+ical elements of .42L - 2ata o'Eects - 2atatypes - Operators – *ttri'utes - dentifiers

2. 8EHAVIORAL DESCRI3TION<2elay odel - 6equential 6tatements

4. STRUCTURAL DESCRI3TION AND DATA FLO> DESCRI3TION<(oncurrent 6tatements

5. MODELING COM8INATIONAL LOGIC CIRCUITS USING VHDL 3AC@AGE<*dders, ultiple+ers, 2ecoders, )ncoders, riority encoders, (omparators, *L7

9. MODELING SE7UENTIAL LOGIC CIRCUITS USING VHDL 3AC@AGE<Latch - !lip-flops0R-6, 3,$,21 - (ounters: -'it counter using 3 flip-flop,>-'itcounter using 3 flip-flop, (ounter /ith parallel load, 2ecade counter, ohnsoncounter, Ring counter, Ripple counter, 7p-2o/n counter Registers:=-'it register /ith ena'le input, 6hift registers, 6erial-in 6erial-out, 6erial-in

arallel-out, arallel-in 6erial-out, arallel-in arallel-out, and ultiplier 6tate achines: ;D;o%er lapping ealy sequence detector, ;D; o%er lapping ooresequence detector, ;D; non o%er lapping oore sequence detector, ;D; non o%erlapping ealy sequence detector

. INTRODUCTION TO VERILOG<

2esign function using .erilog - Le%els of synthesi ing .erilog - 2esigning 5K@ using.erilog - 6imple design - /ires - /ire assignments

". Tes+ %8enches - Response capture - R$L .erilog, f - statement – synthesis

Te:+ 8//;s;# *shenden J$he 2esigners Guide to .42LI $ata cGra/ 4ill u'lications, nd )dition#

# ohammed smail J*nalog .L6 ntegrated (ircuitsI, rentice 4all of ndia#<# Grey, 4urst Lu/is, ayer, J*nalysis and 2esign of *nalog ntegrated (ircuitsI

ohn @illey 6ons#



(VL !4 # Ne+B/1; *n*'-sis s-n+hesis)

$. An*'-sis /= Ne+B/1;s in S D/ *in 5et/or" elements, $ransient and sinusoidal steady state analysis using Laplace$ransformation, 5et/or" functions, $/o port net/or"s: arameters and transfer

function, nterconnection of t/o ports#

. Me+h/ s =/1 C/ &0+e1 Ai e Ne+B/1; An*'-sis6tate .aria'le ethod, *nalytic & numerical solutions, Graph theoretic analysis forlarge scale net/or"s, !ormulation and solution of net/or" graph of simple net/or"s,6tate space representation, *nalysis using 6 ()#

2. E'e en+s /= Ne+B/1; S-n+hesis 5et/or" reali a'ility, 4ur/it olynomials, ositi%e real functions, roperties of R(,RL & L( net/or"s, !oster & (auer forms of reali ation, $ransmission eroes,6ynthesis of transfer functions, !requency and impedance denormalisation, $ypes offrequency selecti%e filters, linear phase filters#

4. 3*ssi e Fi'+e1 DesignButter/orth and (he'yshe% appro+imations, 5ormali ed specifications, !requencytransformations, !requency and impedance denormalisation, $ypes of frequencyselecti%e filters, Linear phase filters#

5. Ac+i e Fi'+e1 Design(ontrolled sources, Op-amp as a controlled sourse, 6allen & 3ey structure, 6ingleamplifier L , 4 , B & BR !ilters, rinciple of design, 6ensiti%ity#

Te:+ 8//;s<;# 6omesh/ar (# Gupta, ohn @ Bayless, Behrou ei"ari, J(ircuit *nalysis-/ithcomputer applications to pro'lem sol%ingI, @iley-)astern Ltd,;FF;#

# Louis @ein'erg, J5et/or" *nalysis & 6ynthesisI, cGra/ 4ill Boo" (ompanync#, ;F #

<# .asude% 3# *atre,I5et/or" $heory & !ilter 2esignI, @iley-)astern Ltd, 6econd)dition, ;FF<#

Re=e1ences<;# !ran"lin !# 3uo, J5et/or" *nalysis & 6ynthesisI, ohn @iley#

# .an .al"en'erg, J 5et/or" *nalysisI, rentice 4all ndia %t# Ltd#, 5e/ 2elhi,

;FF>#<# La/rence # 4uelsman, J*cti%e and assi%e *nalog !ilter 2esignI, cGra/4ill,;FF<#



(VL !5 # VHDL Ve1i'/g '*6)

$. 8*sic '/gic g*+es

. F'i& # F'/&s

2. A e1s(*) H*'=% A e1(6) F0'' #A e1(c) CLA

4. M0'+i&'e:e14<$ M0'+i&'e:e1"<$ M0'+i&'e:e1

5. Dec/ e1

9. Enc/ e1

. ALU

". C/0n+e1s4 6i+ 6in*1- 0& /Bn c/0n+e1M/ #N c/0n+e1C/0n+e1 Bi+h 3*1*''e' L/* *n c'e*1 =*ci'i+-

. Shi=+ Regis+e1sSe1i*' in Se1i*' O0+

Se1i*' in 3*1*''e' O0+3*1*''e' in Se1i*' O0+3*1*''e' in 3*1*''e' O0+

$!. Me*'- M//1e *chines

$$. RAM ROM

$ . Se 0ence e+ec+/1



Semester 3



(VL 2!$ # VLSI Techn/'/g-)

$. VLSI Design F'/B <2esign hierarchy concepts of regularity, modularity & locality# .L6 2esign styles – ( O6!a'rication $echnology- ntroduction, !a'rication rocess flo/- 'asic steps, ( O6 n-/ell

process, *d%anced ( O6 fa'rication technologies, layout design rules – ntroduction – !ullcustom as" Layout design – ( O6 Layout design rules- ( O6 in%erter Layout design –Layout of ( O6 5*52 & 5OR gates – (omple+ ( O6 Logic gates#

. 3*1*si+ic e:+1*c+i/n &e1=/1 *nce es+i *+i/n =1/ &h-sic*' s+10c+01e <ntroduction – Reality /ith interconnection – O6!)$ capacitances- interconnect

capacitance estimation – interconnect resistance estimation#

2. C'/c; sign*'s s-s+e +i ing<On chip cloc" generation & distri'ution using ring & pierce crystal oscillator, non –o%erlapping cloc" signals and gate le%el implementation - 4-tree cloc" distri'ution 5K@-cloc" s"e/ reduction-?ero – 6"e/ cloc" routing 5K@- (loc" distri'ution 5K@ for 2)(alpha chips#

4. Tes+*6i'i+- /= In+eg1*+e s-s+e s # VLSI =/1 F0 - '/gic s-s+e s<2esign constraints- $esting - $he rule of ten – terminology – !ailures in ( O6 –(om'inationalLogic $esting – ractical *d- 4oc 2!$ Guidelines – 6can design techniques-

ntegrated implementation of !L(, 2igital mplementation of !L(s, *nalog implementationof !L(s, i+ed digital K analog implementations of !u y systems, (*2 automation for!L( 2esign, 55 implementing fu y systems#

5. A1i+h e+ic =/1 Digi+*' S-s+e s <ntroduction-notation systems - rinciples of generation & ropagation, ; 'it full adder –

)nhancement $echniques for *dders- multi-operand *dders- ultiplication- *ddition andultiplication in Galois !ields G! 0 n1#

Re=e1e1ence 8//;s<(heng#, 6?) #, J.L6 $echnologyI#, rentice 4all of ndia,2ouglas *# uc"nell and 3amran )shraghian, J Basic .L6 2esign 6ystems and circuits,I

rentice 4all of ndia %t Ltd#, ;FF<#4orspool#, Gorman#, J $he *6 ( 4and'oo"I $ata c-Gra/ u'lication#, ;FFFRandall#L# Geiger and #)#*llen, - .L6 2esign $echniques for *nalog and 2igital (ircuits,

cGra/ 4ill nternational (ompany, ;FFD3lir#, an#, J!u y 6ets and !u y logic #,I rentice 4all of ndia



(VL 2! # VLSI Sign*' &1/cessing)

$.3I3ELING AND 3ARALLEL 3ROCESSING <ntroduction – ipelining of ! R 2igital !ilters- arallel rocessing- ipelining and

parallel rocessing for Lo/ o/er#

.RETIMING<ntroduction – 2efinitions and roperties – 6ol%ing system of nequalities – Retiming

$echniques#

2.UNFOLDING <ntroduction – *n algorithm for unfolding – properties of unfolding – (ritical path, unfolding

and retiming- *pplication of unfolding#

4.SYSTOLIC ARCHITECTURE DESIGN<ntroduction - systolic *rray 2esign ethodology – ! R systolic *rrays- 6election of

scheduling %ector- atri+ ultiplication and 2 systolic array 2esign – 6ystolic design for space representations containing 2elays#

5.FAST CONVOLUTION<ntroduction- (oo" –$oom algorithm- @inogard algorithm – terated con%olution – cyclic

(on%olution – 2esign of fast con%olution *lgorithm 'y nstpection#

9.SCALING AND ROUNDOFF NOISEntroduction – 6caling and Round off noise- 6tate %aria'le 2escription of digital filters-

6caling and Round off noise computation - Roundoff 5oise in iplined 4R filter- Roundoff 5oise (omputation 7sing 6tate %arianle description – 6lo/ do/n, retiming, and pipelining

REFERENCES<3esha'#3# arhi, J.L6 2igital signal processing systems- 2esign and mplementationsI/iley- nter science, ;FFF#

ohammed smail, $erri, !ie , C *nalog .L6 signal and nformation rocessing, ;FF>cGra/ 4ill#

3esha' 3# arhi, .L6 2igital signal processing systems 2esign# *nd mplementation@iley- nter science, ;FFF#3ung#6# # 4# # @hile house, $#3ailath, J .L6 and odern signal processing, rentice hall,;F=M#

ose )# !rance, annis $si%idisI 2esign of *nalog- 2igital .L6 circuits for $elecommunications and signal processingI- rentice 4all, ;FF>#



(VL 2!2 # VLSI esign)

$. MOS T1*nsis+/1 The/1-GaEs"i (hart in .L6 design domain, O6 structure, Biasing and operation of O6, 6calingin O6 ("ts, 6mall geometry effects, O6 capacitances, o'ility %ariations, 4ot electron

effect#

. MOS In e1+e1 Design *n O&+i i *+i/n6tatic and 6/itching characteristics, Resisti%e Load n%erters, n%erter /ith n-type O6!)$load, ( O6 n%erters, ntroduction to 6/itching characteristics, n%erter 2elay $imedefinitions and calculations, 2elay constraints and in in%erter#

2. CMOS C/ 6in*+i/n*' Ci1c0i+ Designntroduction, O6 Logic (ircuits /ith depletion O6 load, ( O6 5*52 and 5OR gates,

(omple+ Gate 2esign, ass transistor logic, $ransistor gate logic 8<9#

4 CMOS Se 0en+i*' L/gic DesignBista'le elements, 6R latch c"t, (loc"ed Latch and !lip-!lop c"ts, ( O6 2-latch edgetriggered flipKflop, ( O6 6R* design, ( O6 2R* design#

5. D-n* ic L/gic *n C'/c;ing C;+s.2ynamic ass $ransistor c"ts#, 2ynamic $ransmission gate design, 4igh erformancedynamic logic c"ts 02ynamis ( O6 Logic,( O6 Logic, ( O6 2omino logic, 5domino, ?ipper ( O6 c"t1 6etup and 4old $ime ,(loc" 6"e/ in ( O6 c"ts, LL techniquefor cloc" synchroni ation8 9#

9. CMOS Chi& Design O&+i/ns *n I O Design.rogramma'le Logic, rogramma'le Logic 6tructures, rogramma'le nterconnect,

Reprogramma'le Gate *rrays, 6ea-of-Gate and Gate *rray 2esign, 6tandard (ell 2esign8 9 ,

KO 2esign- ntroduction, )62 rotection, nput ("ts, Output ("ts and L0 di/dt) noise, Latch-

7p pre%ention#

Re=e1ence 8//;s<;# 6ung- o 3ang, usuf Le'le'ici J( O6 .L6 2esignI2. H.E. Weste, Kamran Eshrigian “Principles of CMO !" # $esign% & 'stem

Perspecti(e *eil, econd Edition,"o+ Price Edition, Pearson ed cation,&sia .<# an Ra'ey J2igital ntegrated ("tsI#># Ra'aey, (handra"asan, 5i"olic, J2igital ntegrated (ircuits-- * 2esign erspecti%eI nded#,

rentice 4all, c# DD<, 6B5 D-;<-MFN>>>-M

M# @este, )shraghian, J rinciples of ( O6-.L6 2esign-- * 6ystems erspecti%eI, nded# *ddison-@esley, c# ;FF>, 6B5 D- D-;M<<N -



(VL 2!4 # VLSI esign +//'s)

$. In+1/ 0c+i/n +/ VLSI Me+h/ /'/gies.L6 hysical 2esign *utomation - 2esign and !a'rication of .L6 2e%ices - !a'rication

process and its impact on hysical 2esign#

. A 70ic; T/01 /= VLSI Design A0+/ *+i/n T//'s2ata structures and Basic *lgorithms, *lgorithmic Graph theory and computationalcomple+ity, $racta'le and ntracta'le pro'lems#

2. Gene1*' &01&/se e+h/ s =/1 c/ 6in*+i/n*' /&+i i *+i/n<artitioning, floor planning and pin assignment, placement, routing#

4. Si 0'*+i/n%'/gic s-n+hesis<.erification-4igh le%el synthesis - (ompaction# hysical 2esign *utomation of ! G*s,

( 6-.42L-.erilog- mplementation of 6imple circuits using .42L and .erilog#5. Design Tes+ing T//'s(ommercial .L6 2esign $ool 0*%aila'%le in the La'1

Re=e1ence 8//;s :

;# 5#*# 6her%ani, J*lgorithms for .L6 hysical 2esign *utomationI, ;FFF## 6#4#Gere , J*lgorithms for .L6 2esign *utomationI, ;FF=#

<# (ommercial .L6 2esign $ools 2ocumentation0*%aila'%le in the La'1



(VL 2!5 # VLSI esign '*6)

3h-sic*' Design +//'s *1e e:+ensi e'- 0se =/1 +he =/''/Bing E:e1cises.

;# 2esign and testing of !lip flops#

# 2esign and testing of registers, counters#

<# 2esign and testing of R* , RO 6ingle (ells#

># 2esign and testing of memory units#

M# 2esign and testing of circuits for com'inational logic circuits#

# 2esign and testing of programming logic arrays#

N# 2esign and testing of adders, multipliers#

=# 2esign and testing of Operational *mplifier

F# 2esign and testing of *K2, 2K* con%erters#

;D# 2esign and testing of applications 'ased on synchronous logic#



Semester 4



(VL 4!$ # Design *n *n*'-sis /= IC s)

$. CIRICUIT CONFIGURATION FOR LINEAR IC<(urrent 6ources, analysis of difference amplifiers /ith acti%e load, supply and temperatureindependent 'iasing technique, %oltage references#

. O3ERATIONAL AM3LIFIERS <*nalysis of Operational amplifier circuits, sle/ rate model and high frequency analysis,operational amplifier noise analysis and lo/ noise operational amplifiers#

2. ANALOG MULTI3LIER AND 3LL <*nalysis of four quadrant and %aria'le transconductance multiplier, %oltage controlledoscillator, closed loop analysis of LL#

4 MOS ANALOG ICS <2esign of O6 Operational *mplifier, ( O6 %oltage references, O6 o/er amplifier andanalog s/itches#

5. MOS S>ITCHED CA3ACITOR FILTERS <2esign $echniques for s/itched capacitor filters, ( O6 s/itched capacitor filters and O6integrated acti%e R( filters#

Re=e1ence 8//;s<Beha ad Ra a%i, J rinciples of 2ata (on%ersion 6ystem 2esign,I 6# (hand & (ompany Ltd,

DDDGrey and eyar, J *nalysis and 2esign of *nalog cs#I @iley nternational, ;FF #3enneth R# La"er, @illy #(# 6ansen, @illiam #(# 6ansen, J 2esign of *nalog

ntegrated(ircuits and 6ystemsI, cGra/ 4ill, ;FF>Grey, @olley, Brodersen, J *nalog O6 ntegrated (ircuitsI, )))



(VL 4! # E'ec+1/ *gne+ic in+e1=e1ence c/ &*+i6i'i+- in esign)

$. EMI ENVIRONMENT<6ources of ) , conducted and radiated ) , $ransient ) , ) – ) ( definitions andunits parameters# ) (oupling rinciples conducted, Radiated and $ransient (oupling,

(ommon impedance Ground (oupling, Radiated (ommon ode and Ground loop couplingRadiated 2ifferential mode coupling, 5ear field ca'le to ca'le to coupling, o/er mains and

po/er supply coupling#. EMI S3ECIFICATION STANDARDS LIMITS <

7nits of specification, ci%ilian standards ilitary standards#

2. EMI MEASUREMENT<) $est nstruments, 6ystems, ) test, ) shielded cham'er# Open *rea test site, $)(ell *ntennas, (onductors 6ensors K nEectors K(ouplers, ilitary test methods and

rocedures, (ali'ration roducers#

4. EMI CONTROL TECHNI7UES <6hielding, !iltering,Grounding , Bonding, solation $ransformer, $ransient 6uppressors,(a'le Routing , 6ignal control, (omponent selection and ounting#

5. EMI DESIGN OF 3C8 <(B $races (ross $al", mpedance control, o/er 2istri'ution 2ecoupling, ?oning other

'oard 2esign and ropagation delay performance models#

REFERENCE 8OO@S<;## Bernhard 3eiser J rinciples of )lectromagnetic (ompati'ilityI, *rtech 4ouse, rd )d,;F= #

# 4enry @# Ott#, J5oise education $echniques in )lectronic 6ystemI, ohn @iley and 6ons, 5e/

or",;F==#<# .# #3odali, J)ngineering ) ( rnciples, easurements and $echnologiesI, )))

ress,;FF #



(VL 4!4 #VLSI Ci1c0i+ +es+ing *n e1i=ic*+i/n)

$. In+1/ 0c+i/n +/ Tes+ingntroduction- 2igital and *nalog $esting, $ypes of $esting, $esting )quipments, $est

)conomics#

. F*0'+ M/ e'ing *n Si 0'*+i/nntroduction, Le%els of !ault odels, 6imulation for 2esign .erification and $est )%aluation,odeling (ircuits for 6imulation, algorithms for fault simulation#

2. Tes+ Gene1*+i/n(om'inatorial (ircuit $est Generation, 6equential (ircuits test generation#

4. An*'/g Mi:e Sign*' Tes+ingemory $est - emory $est Le%els, emory $esting, 2efinitions, 6tatic *2( and 2*(

$esting ethods#

5. Design =/1 Tes+*6i'i+-2esign !or $est !undamentals, Built-in 6elf $est !undamentals, 6ystem $est andarchitecture, !uture of $esting#

Re=e1ence <;# ichel L Bushnell and .ish/ani 2 *gra/al, J)ssentials of electronic testing for 2igital,

emory andi+ed-signal .L6 circuits, 3lu/er *cademic u'lishers, DDD# # *'ramo%ici, # *# Breuer and *# 2# !riedman, H2igital 6ystems $esting and $esta'le

2esignH, ))) ress, ;FFD#0 *%aila'le as * (O u'lication1<# $#3ropf, H ntroduction to !ormal 4ard/are .erificationH, 6pringer .erlag, DDD#># 6amiha ourad and er%ant ?orian, J rinciples of $esting )lectronic 6ystemsI, @iley0 DDD1#M# # Rashin"ar, aterson and L# 6ingh, H6ystem-on-a-(hip .erification- ethodology and$echniquesH,3lu/er *cademic u'lishers, DD;#

(VL 4!5 #VLSI in/1 &1/ ec+ $)



(VL 5!$ # F3GA esign)

$. In+1/ 0c+i/n +/ 3LDs< RO s, Logic array 0 L*1, rogramma'le array logic, G*L, 'ipolar L*, 5 O6 L*, *L;>L >, e+amples

. 31/g1* *6'e g*+e *11*-sPilin+ logic cell array 0L(*1 KO Bloc" rogramma'le interconnect Pilin+ <DDD series and>DDD series ! G*s# *ltera ( L2s, altera !L)P ;D 3 series L2s#

2. 3'*ce en+ *n 1/0+ing <incut 'ased placement iterati%e impro%ement placement Routing: 6egmented channel

routing a e routing Routa'ility and routing resources 5et delays

4. Ve1i=ic*+i/n *n +es+ing<.erification $iming %erification $esting concepts !ault co%erage *$ G $ypes of tests $esting! G*s 2esign for testa'ility#

5 Recen+ e e'/& en+s < 5e/ architectures !ield programma'le interconnect (onfiguring logic arrays and prototyping 'oards (*2 support#

Te:+ 6//;s ;# #3# (han & 6# ourad, 2igital 2esign sing !ield rogramma'le Gate *rray rentice 4all,;FF>#

# # .# Old !ield & R#(# 2orf, !ield rogramma'le Gate *rray, ohn @iley, ;FFM#References;# # Bolton, 2igital 6ystem 2esign /ith rogramma'le Logic, *ddison @esley, ;FFD#

#$homas )# 2illinger, .L6 )ngineering, rentice 4all#



(VL 5! # ASIC esign)

$. INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LI8RARY DESIGN<$ypes of *6 (s –2esign flo/-( O6 transistors ( O6 2esign rules- (om'inational Logic(ell- 6equential logic cell – 2ata path logic cell- $ransistors as Resistors- $ransistor arasitic

(apacitance- Logical effort- Li'rary cell design - Li'rary architecture#

. 3ROGRAMMA8LE ASICS, 3ROGRAMMA8LE ASIC LOGIC CELLS ANDROGR* *BL) *6 ( KO ()LL6#

*nti fuse- static R* – ) RO and )) RO technology - R) 'enchmar"s- *ctel*($- Pilin+ L(*- *ltera !L)P- *ltera *P 2( & *( inputs and outputs- (loc" &

o/er inputs- Pilin+ KO 'loc"s#

2. 3ROGRAMMA8LE ASIC INTERCONNECT, 3ROGRAMMA8LE ASICDESIGN6O!$@*R) *52 LO@ L).)L 2)6 G5 )5$R*ctel *($ – Pilin+ L(* – Pilin+ ) L2 – *ltera *P MDDD and NDDD- *ltera *PFDDD- *ltera !L)P- 2esign systems- Logic 6ynthesis – 4alf gate *6 ( – 6chematic entry

– Lo/ le%el design language – L* tools- )2 !- (! design representation#

4. LOGIC SYNTHESIS, SIMULATION AND TESTING.erilog and logic synthesis- .42L and logic synthesis – types of simulation – 'oundaryscan test- fault simulation - automatic test pattern generation#

5. ASIC CONSTRUCTION, FLOOR 3LANNING, 3LACEMENT AND ROUTING6ystem partition - ! G* partitioning – partitioning methods, floor planning – placement-

physical design flo/- glo'al routing - detailed routing – special routing – circuit e+traction – 2R(#

Te:+ 8//; <;# # #6# 6mith,-J*pplication- 6pecific ntegrated (ircuitsI–*ddison -@esley Longman nc#,;FFNReference Boo"s:*ndre/ Bro/n,- J.L6 (ircuits and 6ystmes in siliconI , cGra/ 4ill, ;FF;#6#2# Bro/n, R# # !rancis, # Ro+, ?#G# 7ranesic, J !ield rogramma'le Gate *rraysI -3lue%er *cademic u'lishers, ;FF #

ohammed smail and $erri !ie , J*nalog .L6 6ignal and nformation rocessingI , cGra/ 4ill, ;FF>#6# # 3ung, 4# # @hilo 4ouse, $# 3ailath, J .L6 and odern 6ignal rocessingI, rentice4all , ;F=M#

ose )# !rance, annis $si%idies, J 2esign of *naloig- 2igital .L6 (ircuits for $elecommunication and 6ignal rocessing J, rentice 4all, ;FF>



(VL 5!2 # L/B &/Be1 VLSI esign)

$. INTRODUCTION < 5eed for Lo/ po/er .L6 chips- Lo/ o/er 2esign ethodology – Logic synthesis forLo/ po/er – 6ources of po/er dissipation#

. 3O>ER ESTIMATION<6tatistical $echniques- )stimation of Glitching o/er- 6ensiti%ity *nalysis - (ircuitRelia'ility - o/er )stimation at the circuit le%el- 4igh – le%el po/er )stimation -

nformation $heory 'ased approaches - )stimation of ma+imum po/er#

2. SYNTHESIS FOR LO> 3O>ER<Beha%ioral Le%el $ransforms- Logic le%el optimi ation for lo/ po/er - (ircuit le%el$ransforms#

4. DESIGN AND TEST OF LO> VOLTAGE AND LO> 3O>ER CIRCUITS<(ircuit 2esign style – Lea"age current in 2eep su'-micrometer $ransistors- 2esign ssues-

inimi ing 6() – Lo/ %oltage circuit design techniques –$esting 2eep su'-micrometer (s – ultiple supply %oltages – Lo/ energy computing - sources of soft/are po/er dissipation-soft/are po/er estimation- soft/are po/er optimi ation – *utomated Lo/ po/er codegeneration - (O2)6 G5 for lo/ po/er#

REFRENCES <3aushi" Roy and 6harat (# rasadI Lo/ o/er ( O6 .L6 circuit 2esignI ohn @iley &6ons, DDD#Gary# B eap# 3#, J ractical Lo/ o/er 2igital .L6 2esign, 3lu/er academic

pu'lishers, ;FF=#6asan man and assoud edram, JLogic synthesis for Lo/ po/er .L6 2esignsI 3lu/er academic pu'lishers, ;FF=#



(VL 5!4 # Mi:e sign*' esign)

$. In+1/ 0c+i/nntroduction to ( O6 analog circuits, O6 transistor 2( and *( small signal parameters

from large signal model, (ommon source amplifier /ith resisti%e load, diode load and current

source load, 6ource follo/er, (ommon gate amplifier, (ascode amplifier, !olded (ascode#

. F1e 0enc- 1es&/nse!requency response of amplifiers, (urrent sourceKsin"Kmirror, atching, @ilson currentsource and Regulated (ascode current source, Band gap reference, 2ifferential amplifier,Gil'ert cell, Op-*mp, 2esign of stage Op-*mp, 2( and *( response, !requencycompensation, sle/ rate, Offset effects, 6RR, 5oise, (omparator, 6ense *mplifier#

2. M*+ching

6ources of mismatch, 6ystematic layout errors, 6i ing and ratio strategy, 7nit elements andcommon, centroid layout and Random mismatch models

4. D*+* C/n e1+e12ata (on%erter !undamentals, *nalog .ersus 2iscrete $ime signals, (on%erting analogsignals to 2igital signals, 6ample and 4old (haracteristics, 2ata *rchitectures, 2*( and*2( specifications# i+ed 6ignal Layout ssues, 2*( *rchitectures,R- R Ladder 5et/or"s,(urrent steering, ipeline 2*(# *2( *rchitectures, !lash, $he $/o step !lash *2(, $he6uccessi%e *ppro+imation *2(, R! amplifier, Oscillator, LL, i+er#

5. N- 0is+ A D *n D A C/n e1+e1s C/ &*1*+/1s 5on-linearity specs, .oltage scaling 2K*, settling, (urrent scaling 2K*, matching,segmentation, (harge redistri'ution, !lash *K2, )5OB %s B@, spar"le code elimination,"ic"'ac", *synchronous, Regenerati%e 'and Offset cancellation

9. A D C/n e1+e1s *n Mi:e Sign*' L*-/0+ Iss0es Basic principles, 6ample & 4old characteristics, ractical implementations, 6( %scontinuous time, ? domain model, 6ingle 'it %s multi-'it !KB, 4igher order - *64 %s singleloop and 2K* principle#

Rec/ en e Te:+s;# La"er & 6ansen - H2esign of *nalog ntegrated (ircuits and 6ystemsH , cGra/ 4ill#

# Gray 4urst, Le/is & eyer- H*nalysis and 2esign of *nalog ntegrated (ircuits 0>th )d1H<# Geiger, *llen & 6trader-J .L6 2esign $echniques for *nalog and 2igital (ircuitsH,

cGra/-4ill#

># *llen & 4ol'erg –J( O6 *nalog (ircuit 2esignH, O+ford 7 #M# hillip# )# *llen, 2ouglas R# 4ol'erg, J( O6 *nalog circuit 2esignI O+ford 7ni%ersityress, DD# Ra a%i B#, JR! icroelectronicsI, rentice 4all, ;FF=#

N# Ba"er, Li, Boyce, J( O6: (ircuit 2esign, Layout and 6imulationI, rentice 4all of ndia, DDD

=# Bosco Leung, J.L6 for @ireless (ommunicationI, 4, DDReferences:Ra a%i B#, J2esign of *nalog ( O6 ntegrated (ircuitsI, $ 4, DD<

u"herEee, J.L6 6ystem 2esign: ntroduction to 5 O6 and ( O6 .L6 6ystem 2esignI,rentice-4all, ;F=

university science instrumentation centre

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