uP2201

Architecture:

8 Bit ALU

64 8-bit Data Registers(R0-R63)

Data Bus => d0-7

(f0-5) => 64 Operations

AR –Address Register

AS -Address Select

DR –Data Register

A0-5 Address Line

SR- Shift Register

L0-7 Status or Flag lines

Instruction Set:

MOV Rx-> Ry : Move any Rx to any Ry.

MVI (Rx)-> Ry : Move register pointed by value of Rx to Ry.

MVI Rx-> (Ry) : Move register Rx to a register pointed by value in Ry.

LD D0-7,Rx :Load immediate any 8-bit value in to any Rx.

AND : Performs bit wise AND operation between R0 and R1 and stores the

result in R2.

OR : Performs bit wise OR operation between R0 and R1 and stores the result

in R2.

XOR : Performs bit wise XOR operation between R0 and R1 and stores the

result in R2.

ADD : R2=R0 plus R1. L0 stores the carry.

ADC : Add R0, R1 and L0 values and store it in R2. L0 stores the carry.

If Lx=1 Jump xxxx : If any Lx flag is equal to one then jump to instruction line xxxx.

If Lx=0 Jump xxxx : If any Lx flag is equal to zero then jump to instruction line xxxx.

CMP Rx,Ry : Is Rx≥Ry; If true, L3=1 else L3=0.

INC Rx : Increment any Rx register. L0 is set if the operation results in overflow.

DEC Rx : Decrement any Rx register. L0 is set if the operation results in

underflow.

Lshift0 Rx : Left shift the data in any Rx register with zero. L1 stores the bit which is

shifted out.

Rshift0 Rx : Right shift the data in any Rx register with zero. L1 stores the bit which is

shifted out.

Lshift1 Rx : Left shift the data in any Rx register with one. L1 stores the bit which is

shifted out.

Rshift1 Rx : Right shift the data in any Rx register with one. L1 stores the bit which is

shifted out.

SUB : R2=R0 minus R1. L0 is set if borrow is resulted.

SBB : R2=R0 minus (R1+L0 [previous borrow]). L0 is set if borrow is resulted.

NOT : Performs bit wise NOT operation on R0 and Stores the result in R2.

Flags:

L0 : Carry/Borrow/Overflow/underflow.

L1 : Shifted out bit.

L2 : is set if any ALU operation results in Zero

L3 : If result of compare is true then L3 is set to 1, If result of compare is false then L3 is set

to 0.

Sample instructions and control signals:

Instruction Wr Rd AI A0-5 LD D0-7 F0-5

MOV R38-> R1 0 1 0 010110 0 X 000000

1 0 1 000001 0 X 000000

MOVI (R38)-> R1 0 1 0 010110 0 X 000000

0 1 1 X 0 X 000000

1 0 0 000001 0 X 000000

MOVI R1-> (R38) 0 1 0 010110 0 X 000000

0 1 1 X 0 X 000000

0 1 0 000001 0 X 000000

1 0 1 X 0 X 000000

LD D0-7,R5 0 0 0 X 1 11010110 000000

1 0 0 000101 0 X 000000

AND 0 0 0 X 0 X 000001

OR 0 0 0 X 0 X 000010

XOR 0 0 0 X 0 X 000011

ADD 0 0 0 X 0 X 000100

ADC 0 0 0 X 0 X 000101

If Lx=1 Jump xxxx 0 0 0 X 0 X 000000

If Lx=0 Jump xxxx 0 0 0 X 0 X 000000

CMP 0 0 0 X 0 X 000110

INC Rx 0 0 0 X 0 X 000111

DEC Rx 0 0 0 X 0 X 001000

Lshift0 Rx 0 0 0 X 0 X 001001

Rshift0 Rx 0 0 0 X 0 X 001010

Lshift1 Rx 0 0 0 X 0 X 001011

Rshift1 Rx 0 0 0 X 0 X 001100

SUB 0 0 0 X 0 X 001101

SBB 0 0 0 X 0 X 001110

NOT 0 0 0 X 0 X 001111