US006721207B2

(12) United States Patent Tsujikawa et al.

(10) Patent N0.: (45) Date of Patent:

US 6,721,207 B2 *Apr. 13, 2004

(54) NON-VOLATILE MEMORY SYSTEM INCLUDING A CONTROL DEVICE TO CONTROL WRITING, READING AND STORAGE AND OUTPUT OPERATIONS OF NON-VOLATILE DEVICES INCLUDING MEMORY CELLS AND DATA LATCHES

(75) Inventors: Tetsuya Tsujikawa, Hamura (JP); Atsushi Nozoe, Hino (JP); Michitaro Kanamitsu, Ome (JP); Shoji Kubono, Akishima (JP); Eiji Yamamoto, Kodaira (JP); Ken Matsubara, Ome (JP)

(73) Assignees: Renesas Technology Corp., Tokyo (JP); Hitachi ULSI Systems Co., Ltd., Tokyo (JP)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

This patent is subject to a terminal dis claimer.

(21) (22) (65)

Appl. No.: 10/211,342

Filed: Aug. 5, 2002

Prior Publication Data

US 2002/0191459 A1 Dec. 19, 2002

Related US. Application Data

(63) Continuation of application No. 10/011,723, ?led on Dec. 11, 2001, now Pat. No. 6,507,520, which is a continuation of application No. 09/539,633, ?led on Mar. 30, 2000, now Pat. No. 6,233,174, which is a continuation of application No. 09/250,157, ?led on Feb. 16, 1999, now Pat. No. 6,046,936.

(30) Feb. 16, 1998

Foreign Application Priority Data

(JP) ........................................... .. 10-32776

(51) Int. Cl.7 .............................................. .. G51C 16/04

(52) US. Cl. ............................ .. 365/185.28; 365/185.29

(58) Field of Search ..................... .. 365/185.28, 185.29, 365/18501

STATUS REGISIHJ

5* L MODE CONIROL CWT/UH

(56) References Cited

U.S. PATENT DOCUMENTS

5,570,315 A 10/1996 Tanaka et al. ....... .. 365/185.22

5,602,789 A 2/1997 Endoh et al. ........ .. 365/185.03

5,761,122 A 6/1998 Nakamura et al. 365/185.21 5,768,191 A 6/1998 ch01 et al. 5,870,218 A 2/1999 Jyouno et al. ....... .. 365/18503 5,982,667 A 11/1999 Jyouno et al. ....... .. 365/185.22 6,222,763 B1 4/2001 Sato et al. 6,226,708 B1 5/2001 McGoldrick et al. ..... .. 711/103

FOREIGN PATENT DOCUMENTS

JP 62-099996 5/1987 JP 9297996 11/1997

OTHER PUBLICATIONS

“Flash Memory—Multi—Level Memory, US Makers Set About Technological Development Precedent and Bring to the Commercial Stage in 1995, Getting Over Reliability,” (with English translation).

Primary Examiner—Hoai Ho (74) Attorney, Agent, or Firm—Antonelli, Terry, Stout & Kraus, LLP

(57) ABSTRACT

A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and ?rst and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then veri?es storage. When the control device supplies the ?rst read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.

4 Claims, 57 Drawing Sheets

MEMORY MAIv DATA LATCH CIRCUIT‘ SENSE LATCH C‘RCUW

U.S. Patent Apr. 13, 2004 Sheet 1 0f 57 US 6,721,207 B2

8 9 6

5 3 4 f3 MEMORY MAT,

x x DATA LATCH ADDREss ADDRESS CIRCUIT, BUFFER DECODER SENSE LATCH

CIRCUIT

I

7 (Ff-‘3%) Q _ ___’___A,‘)’\_/5 \ ~ 17 16 21 r13

I/OOII? S 1' DRTA ) I Y (RATEDIRDUTT/ ’ UTPUT I MULTI— *7 INPUT AR Y 0 V07 PLEXER- BUFFER 3%? Y ADDREss BUFFER

~" A F DEcoDER . R/Bb N L ‘ 1 \11 ~

‘ Y ADDRESS 7

x2: - 2' COUNTER ‘v12

CEb 18 2O 21

‘3g; CONIAFEOL S 5 5f SIGN ,

S0 BUFFER +MODE CONTROL CIRCUIT * INTERNAL POWER +

gggggcmcm ‘’ sTATUs REGISTER I SUPPLY CIRCUlT M; 5 E ,_ g

1 180

U.S. Patent

FIG.

SOURCE POTENTIAL

Apr. 13, 2004

2

Sheet 2 0f 57 US 6,721,207 B2

CONTROL GATE POTENTIAL

CONTROL GATE /CG INTERLAYER INSULATING FILM

FG

FLOATING GATE J DRAIN

POTENTIAL

TUNNEL OXIDE FILM ‘I S\ * SOURCE I

MEMORY WELL

I DRAIN _/0

é WELL POTENTIAL sue

FIRST SECOND MODE COMMAND COMMAND

READ OUR NO NEED

RECOVERY READ 01H NO NEED

EHASE 20H BOH

PROGRAM TFR 40H

ADDITIONAL PROGRAM ‘0H 40H

RETRY PROGRAM IAH NO NEED

PARTIAL ERASE 2FH BOH

REWRITE 11H 40H

U.S. Patent Apr. 13, 2004 Sheet 3 0f 57 US 6,721,207 B2

FIG. 4

TITLE DEFINITION

1/07 Ready/IE? “VOH“=Ready “VOL"=Busy I/O6 Reserved

[/05 Erase Check “VoH"=Fai| “VOL“:Pass

1/04 Program Check “VOH"=FaIl “VOL"=Pass

[/03 Reserved

I/O2 Reserved

I/ O1 Reserved

[/00 Reserved

STATUS REGISTER

U.S. Patent Apr. 13, 2004 Sheet 5 0f 57

FIG. 6

PROGRAM DATA DLL DLR

DOA 11

OD oo

VH3 ------------ -

VH2 ------------ —

vm -- ---------- -

VWV3 VWE2

VWV2 VWE1

VWV1 VWDS

OV MEMORY CELL’ NUMBER

US 6,721,207 B2

U.S. Patent Apr. 13, 2004 Sheet 6 0f 57 US 6,721,207 B2

FIG. 8

-17v _ ‘ SELECTED ---------- wORD LINE

SEOTOR BATCH 5‘ +111 P11 j= ERASE 0V ------- ----- - NON-SELECTED (1 WORD ERASE & & WORD LINE AT SAME TIME)

0v IN

IN ‘ _ SELECTED --------- WORD LINE

WRITE EvERY 0v NON—SELECTED BIT L J: wORD LINE (1 WORD WRITE AT SAME TIME) W W

SELECTED NON-SELECTED BIT LINE BIT LINE

OPERATION VOLTAGE

FIG. 9 WHITE

Case1 Case2 Case3 Case4 CaSeS

(1) (3) (3) (2) (3)

(31 (HT (1) I I I I II

ERASING STATE

U.S. Patent Apr. 13, 2004 Sheet 8 0f 57 US 6,721,207 B2

FIG. 1 1 AND TYPE MEMORY MAT M1

/ SOURCE LINE l

l 4

SDI BIT LINE [ (CONTROL GATE) FIJI 1| {MC

WL (WORD LINE) j. g) SUB-BIT LINE ‘ /\/MC ‘

WL (WORD LINE) mv/ _T_ i

‘klzqvMc ‘AL-LI SUB-BIT LINE _ l /

'l;____.___;_.—j>'/ WL (WORD LINE) I 11/ MC

farm 2 SSi (sOuRcE LINE I __ 1 /\/M2

CONTROL GATE) ILL 01

BIT LINE BIT LINE

NEARIIOTFIIFTMAT SOURCE LINE

MC‘\ u-" ‘

wORO LINE WORD LINE A\_/MC

WORO LINE A‘VMC

WORO LINE MCf '

BIT LINE BIT LINE

U.S. Patent Apr. 13, 2004 Sheet 9 0f 57 US 6,721,207 B2

DiNOR TYPE MEMORY MAT

>—-SOURCE LINE

WORD LINE §\_,MC WORD LINE WORD LINE Hp/MC

WORD “NE SUB-BIT LINE

5 5 ' : j . FF . _ _j

WORD LINE \\_M_(_;--. 4| \¥MC SELECTED GATE- ____ _-__I

BIT LINE BIT UNE

NAND TYPE MEMORY MAT

sOuRcE LINE r1 ---- -- - SOURCE LINE

CONTROL GATE I ME" 2]

WORD LINE -#€/::i .... --_.__“ WMC WORD LINE II ..... ..__D|

WORD LlNE- ----- --___|| WMC

WORD LINE- \ Mé-_-___I|

' 12/ MC WORD LINE ~7 I ____ .____" \\_MC

BIT LINE .... -. D

OONTROL GATE .,_5 ‘ ‘

BIT LINE BIT LINE

U.S. Patent Apr. 13, 2004 Sheet 10 0f 57 US 6,721,207 B2

HiCFI TYPE MEMORY MAT SOURCE LINE SOURCE LINE

BIT LINE ‘ I "Jab ‘TLII II'TF" CONTROL GATE T|| MC II_ rJl MC IL_

WORD LINE l’ l l’ i SUB-SOURCE Fur/MC LINE \<~ ,7

a MC WORD LINE l l l l

Ii ITLI. r71 TTLI SUB-BIT “MM??- 5% Q

WORD LINE l l l l ___ ._ _ __

BIT LINE MC5"— {MC MC5H'TT AMC CONTROL GATE I LL

BIT LINE BIT LINE BIT LINE BIT LINE

U.S. Patent Apr. 13, 2004 Sheet 11 0f 57 US 6,721,207 B2

FETCH FIRST COMMAND 5'81 '

FETCH SECTOR ADDRESS F‘SQ

FETCH PROGRAM DATA ‘53

FETCH SECOND COMMAND 84

i LATCH '01" DATA 5 TS‘ § 5 (SEE FIG 23)

'01- 5 PROGRAM '00- DATA = PROGRAMING 5 OPERATION -;

: l : VERIFY vwv3 FAIL; g ? I ‘11' WORD FAIL -_,-._PP_S_S_ ________________ _. ?lswwgggcm T84

T52 LATCH '00" DATA ________________________ _'

' PROGRAM *oo- DATA ERRATIC/ PROGRAMING OISTURB OPERATION DETECTION

OPERATION

T53 LATCH '10‘ DATA

"0' P OGRAM "1()' DATA PROGRAMING R OPERATION

SET PASS FLAG SET FAIL FLAG ,38 TO STATUS TO STATUS I

55‘? REGISTER REGISTER I I

( END TOTO) C ENDINGI) PROGRAM FLOW (CASE 1)

U.S. Patent Apr. 13, 2004 Sheet 12 0f 57 US 6,721,207 B2

FIG. 17

Vth

> "01" VWV3 ---------------- __

> "H" BIT NUMBER

"01" PROGRAM DATA

FIG. 18

Vlh 1 > ~01»

WW2

BIT NUMBER

7190i EBQQBAM DATA

U.S. Patent Apr. 13, 2004 Sheet 13 0f 57 US 6,721,207 B2

FIG. 19

V

BlT NUMBER

"10" PROGRAM DATA

FIG. 20

"1.M0_m munmu?l “,7 ‘m as

V

WW >

_ w . . _ _ _ _ _ . _ _ _ _ _ _ _ VWD

v 0 BIT NUMBER

MQ/DISTURB DETECTION OPERAT‘ON

U.S. Patent Apr. 13, 2004 Sheet 14 0f 57 US 6,721,207 B2

FIG. 21

CALCULATION CONTENT DATA LATCH PROCESS (SENSE LATCH DATA OF

SELECTED MAT SIDE)

'01- PROGRAM DATA A+§

'00" PROGRAM DATA A+B

'10" PROGRAM DATA 5+8

"0o" ERRATIC DETECTION DATA A—+B_

"10" ERRATIC DETECTION DATA A . §

'11" DIsTuRB DETECTION DATA A - B

A: UPPER DlGlT DATA BILOWER DIGIT DATA

FIG. 22

UPIIXDER LOIENER A+B' A+B K+B m A-é' A-B DIGIT DIGIT

0 1 0 1 1 0 0 0

0 0 1 0 1 1 0 0

1 0 1 I 0 0 1 0

I 1 1 1 'I 0 0 1

U.S. Patent Apr. 13, 2004 Sheet 15 0f 57 US 6,721,207 B2

§ START '01" PROGRAMING ? 5 OPERATION -

§ I 5 S101 EXECUTE DATA LATCH ; PROcEss

V

8'11 APPLY "o1" PROGRAMING BIAS VOLTAGE

7

S121 EXECUTE PROGRAM VERIFY vwvs

813 ALL

JUDGIEIAENT PASS

END "01" PROGRAMING)

------_

OPERATION

sTART "I0" ERRATIO i DETECTION

II 5 S201 EXECUTE DATA LATCH E

PROCESS I I E

5211 EXECUTE ERRATIO VERIFY VWE1

5 522 § 3 \- ALL \\ FAIL E 5 JUDGMENT 5 : ? :

PASS 5

END "10" ERRATID ; DETECTION 5

l ' _ . _ . . _ _ _ _ _ , _ _ _ _ _ _ . _ _ _ _ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ -__l

U.S. Patent Apr. 13, 2004 Sheet 17 0f 57 US 6,721,207 B2

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U.S. Patent Apr. 13, 2004 Sheet 18 0f 57 US 6,721,207 B2

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U.S. Patent Apr. 13, 2004 Sheet 19 0f 57 US 6,721,207 B2

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