US

Status of GbE Peripheral Crate Controller

Ben Bylsma

EMU meeting Fermilab, October 21, 2005

Section 1: Hardware

Section 2: Firmware Development

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 2

Hardware StatusHardware StatusHardware StatusHardware Status

10 Pre-Production Boards 5 at CERN (2 returning) 1 at Rice 3 at OSU

1 in DMB/DDU/DCC test setup 1 for Firmware Development 1 Problem Board (unsolved)

1 at UCD Radiation Test

“Real World” Experience OSU Rice B904

No Issues Reported

75 Production Boards in Hand

Scheduled to be Stuffed

Pre-Production Version

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 3

Radiation TestingRadiation TestingRadiation TestingRadiation Testing

63.3 MeV Proton Beam at Crocker Nuclear Laboratory (UCD) Irradiated all active components not previously tested. Main goal was TID for survivability (not SEUs). Exposed components to ~6 kRads. (exp. Max. ~.13 kRads)

Results: Boring. Mostly uneventful. Most failures recovered with reset (some need power cycle). All components survived.

SEU mitigation: Reset circuit uses discrete logic and majority voting. Data stored in FIFOs and FLASH uses ECC and majority voting.

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 4

75 PCBs produced

Stuffing: All components and PCBs at Dynalab for one month. Dynalab given OK to go, but are overloaded with jobs. Stencil is due Monday. Surface mounting run to start next week. Expect delivery of stuffed boards within two weeks.

Testing and Delivery: ASAP after delivery of stuffed boards.

Production StatusProduction StatusProduction StatusProduction Status

Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec

DMB 350 450 550TMB-RAT 10* 30 150 270 390 510 540CCB 10 20 40 60 70MPC 10 20 40 60 70LVRB 10 20 40 60 70Backplane 4* 10 20 40 60 70Controller 10 20 40 60 70

2005

Production Schedule

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 5

Firmware: What’s NewFirmware: What’s NewFirmware: What’s NewFirmware: What’s New

Firmware Revision 3.06 Programmable MAC address.

Device MAC address. 3 Group MAC addresses. Default Server MAC address.

Access to configuration registers. Storage for up to 21 different configurations in FLASH memory. Settable default configuration (for power up). New format of returned packet data headers.

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 6

New Data Header FormatNew Data Header FormatNew Data Header FormatNew Data Header Format

Returned Packet Data Header: Prior to Rev. 3:

As of Rev. 3

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 7

Firmware: What’s NextFirmware: What’s NextFirmware: What’s NextFirmware: What’s Next

Need for Feedback One at a time reads (built in feedback/data is expected) One at a time writes (when does command finish?) Stacked reads/writes in FIFO (when is FIFO almost full?)

Particularly a problem for programming PROMS with several MB of write commands.

Developing two methods for feedback.1) Warning packets (Error and Info packets as well):

Spontaneously generated packets when certain events occur (like when the “almost full” flag of the external FIFO is set).

Spontaneous packet sending can be enabled or disabled.

2) Acknowledgement Requests. Bit in header of every packet sent. Return packet with disposition of corresponding command. Under programmers control on packet by packet basis.

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 8

Firmware: What’s NextFirmware: What’s NextFirmware: What’s NextFirmware: What’s Next

Need for Easy Firmware Updates Currently must use IMPACT to program PROM through JTAG. Need to program PROM via Ethernet packets to JTAG interface. Handshaking scheme needs to be in place.

Next Revision Release Handshake mechanism (acknowledgements and warnings) PROM programming

B. Bylsma EMU Meeting, Fermilab Oct. 21, 2005 9

Documentation and UpdatesDocumentation and UpdatesDocumentation and UpdatesDocumentation and Updates

Web site for Documentation and Firmware Updates http://www.physics.ohio-state.edu/~cms/GbE_Ctrl/