useless memory allocation in system on a chip test: problems and solutions paul theo gonciari bashir...
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Useless Memory Allocation in System on a Chip Test: Problems and Solutions
Paul Theo Gonciari
Bashir Al-Hashimi
Electronic Systems Design
Group
University of
Southampton, UK
Nicola Nicolici
Electrical and Computer
Engineering
McMaster University,
Canada
Overview
• Memory problems in SOC test
• Useless memory allocation (UMA) – Problems:
• Multiple scan chain designs• Core wrapper design
– Solutions:• mUMA heuristic• ATE deployment procedure
• Experimental results
• Conclusions
Why Test Data Reduction ?
• Exponential increase in volume of test data
(ITRS)
• 60% of ATE upgrade caused by memory
(EETimes)
• Solutions– Built-in self-test (BIST)– Test data reduction
• Useful – test data compression• Useless
Useless Memory Allocation Problems
• Multiple scan chains - padded values
S3S2S1
1x x 010
010xxx
first bit
last bit
01 0 001
UMA – Core Wrapper Design
Core A
WSC2
WSC3
WSC1
WSC4
tb2
tb3
tb4
tb1 5FF
8FF
12FF
11FF 12FF11FF
8FF5FF
Solution 1
UMA – Core Wrapper Design
Core A
WSC2
WSC3
WSC1
WSC4
tb2tb3
tb4
tb1
5FF
8FF
12FF
11FF 12FF11FF
8FF5FF
Solution 2
UMA – Core Wrapper Design
TS 2
TS 1
first bit last bit
12FF11FF
8FF5FF
Solution 2
useless memoryfirst bit
12FF11FF8FF
5FF
Solution 1
• Wrapper dependent• Complex control
• Wrapper independent• Simple control
mUMA – minimum UMA heuristic
1. Partition the wrapper scan chains
(WSC)
2. Design a core wrapper • minimum area (mA) heuristic• compute UMA
3. Select the design with minimum UMA
mA – minimum Area heuristic
• Order SC in descending order
• Assign SC to WSC such that– maximum WSC remains the same– minimize area for selected partition
• Otherwise, select minimum WSC
• Compute UMA
12FF
12FF
mA – minimum Area heuristic
11FF
8FF
5FF
WSCsSCs
1
2
3
11FF
4
8FF
5FF
mA – minimum Area heuristic
11FF
8FF
5FF
12FF
WSCsSCs
1
2
3
4
12FF
8FF
5FF
11FF
ATE Deployment Procedure
• Requires 3 parameters– Maximum length partition (maxwsc)– Difference (diff)– Split point (sp)
• Simple procedure
TS 2
TS 1
12FF11FF
8FF5FF
12FF11FF
8FF5FF
diff maxwscsp
0 4 12 16 clk
mUMA performance
0
20000
40000
60000
80000
100000
120000
140000
160000
180000
s5378 s9234 s13207 s15850 s35932 s38417 s38584
Me
mo
ry
mUMA UMA for np=2
mUMA circuit s38584
150000
200000
250000
300000
1 6 11 16 21 26 31 36TAM width
Mem
ory
FFD [Marinissen, et al. ITC00] BFD [Iyengar, et al. ITC01] mUMA np=2
Minimum Memory Requirements Comparison
0
20000
40000
60000
80000
100000
120000
140000
160000
180000
200000
s5378 s9234 s13207 s15850 s35932 s38417 s38584
Me
mo
ry
min FFD [Marinissen, et al. ITC00] min BFD [Iyengar, et al. ITC01] min UMA np=2
Maximum Memory Requirements Comparison
0
50000
100000
150000
200000
250000
300000
s5378 s9234 s13207 s15850 s35932 s38417 s38584
Mem
ory
max FFD [Marinissen, et al. ITC00] max BFD [Iyengar, et al. ITC01] max UMA np=2
Average Memory Requirements Comparison
0
50000
100000
150000
200000
250000
s5378 s9234 s13207 s15850 s35932 s38417 s38584
Me
mo
ry
avg FFD [Marinissen, et al. ITC00] avg BFD [Iyengar, et al. ITC01] avg UMA np=2
Conclusions
• Illustrated the problem of Useless Memory
• Proposed a new methodology– mUMA core wrapper design algorithm– ATE deployment procedure
• Post-TAM optimization for minimum UMA
• Future work– Exploit the core wrapper design properties
DFT ATE
• Very low cost testers [Bedsole D&T01]– Reconfigurable memory pool– Reduced features per-pin– Memory management unit
• Sequencing per pin testers [Sivaram
ITC01]– Clock and data control per group of
pins– Central control unit
UMA - Core Wrapper Design – Case 2
wsc i = 11wsc o = 12
10 FF9 FF
useless memory
10 FF9 FF
wsc i = 12wsc o = 12
9 FF10 FF
TS 1
TS 2
9 FF
10 FF
Solution 1
Solution 2