ut oct. 2004 -- dehon sub-lithographic semiconductor computing systems andré dehon...
TRANSCRIPT
![Page 1: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/1.jpg)
UT Oct. 2004 -- DeHon
Sub-lithographic Semiconductor Computing
SystemsAndré DeHon
In collaboration with
Helia Naeimi, Michael Wilson, Charles Lieber, Patrick Lincoln, and John Savage
![Page 2: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/2.jpg)
UT Oct. 2004 -- DeHon
Approaching the Bottom
• In 1959, Feynman pointed out we had– “plenty of room at the bottom”
• Suggested:– wires ~ 10-100 atoms diameter– circuits ~ few thousands angstroms
~ few hundred nm
![Page 3: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/3.jpg)
UT Oct. 2004 -- DeHon
Approaching the Bottom
• Today we have 90nm Si processes– bottom is not so far away
• Si Atom – 0.5nm lattice spacing– 90nm ~ 180 atoms diameter wire
![Page 4: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/4.jpg)
UT Oct. 2004 -- DeHon
Exciting Advances in Science
• Beginning to be able to manipulate things at the “bottom” -- atomic scale engineering– designer/synthetic molecules– carbon nanotubes– silicon nanowires– self-assembled mono layers– designer DNA
![Page 5: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/5.jpg)
UT Oct. 2004 -- DeHon
Question
• Can we build interesting computing systems without lithographic patterning?
• Primary interest:
below lithographic limits
![Page 6: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/6.jpg)
UT Oct. 2004 -- DeHon
Why do we care?
• Lithographic limitations– Already stressing PSM– …xrays, electron projection…
• Lithographic costs
$0
$10,000,000
$20,000,000
$30,000,000
$40,000,000
$50,000,000
1980 1985 1990 1995 2000 2005
Year
Exp
osur
e to
ol p
rice
Source: Kahng/ITRS2001
![Page 7: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/7.jpg)
UT Oct. 2004 -- DeHon
Today’s Talk
Bottom up tour: from Si atoms to Computing• Nanowire
– growth– devices– assembly– differentiation– coding
• Nanoscale memories from nanowires• Logic: nanoPLAs• Interconnected nanoPLAs• Analysis
![Page 8: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/8.jpg)
UT Oct. 2004 -- DeHon
SiNWGrowth
• Atomic structure determines feature size
• Self-same crystal structure constrains growth
• Catalyst defines/constrains structure
![Page 9: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/9.jpg)
UT Oct. 2004 -- DeHon
SiNW Growth
![Page 10: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/10.jpg)
UT Oct. 2004 -- DeHon
SiNW Growth
![Page 11: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/11.jpg)
UT Oct. 2004 -- DeHon
Building Blocks
![Page 12: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/12.jpg)
UT Oct. 2004 -- DeHon
Semiconducting Nanowires
• Few nm’s in diameter (e.g. 3nm)– Diameter controlled by seed catalyst
• Can be microns long
• Control electrical properties via doping– Materials in environment during growth– Control thresholds for conduction
From: Cui…Lieber APL v78n15p2214
![Page 13: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/13.jpg)
UT Oct. 2004 -- DeHon
Radial Modulation Doping
• Can also control doping profile radially– To atomic precision– Using time
Lauhon et. al.Nature 420 p57
![Page 14: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/14.jpg)
UT Oct. 2004 -- DeHon
Devices
Diode and FET Junctions
Doped nanowires give:
Huang…LieberScience 294 p1313
Cui…LieberScience 291 p851
![Page 15: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/15.jpg)
UT Oct. 2004 -- DeHon
Langmuir-Blodgett (LB) transfer• Can transfer tight-packed, aligned SiNWs
onto surface– Maybe grow sacrificial outer radius, close pack,
and etch away to control spacing
+
Transfer aligned NWs to patterned
substrate
Transfer second layer at right
angle
Whang, Nano Letters 2003 (to appear)
![Page 16: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/16.jpg)
UT Oct. 2004 -- DeHon
Homogeneous Crossbar
• Gives us homogeneous NW crossbar– Undifferentiated wires– All do the same thing
![Page 17: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/17.jpg)
UT Oct. 2004 -- DeHon
Control NW Dopant
• Can define a dopant profile along the length of a wire– Control lengths by timed growth– Change impurities present in the
environment as a function of time
Gudiksen et. al. Nature 415 p617
Björk et. al. Nanoletters 2 p87
![Page 18: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/18.jpg)
UT Oct. 2004 -- DeHon
Control NW Dopant
• Can define a dopant profile along the length of a wire– Control lengths by timed growth– Change impurities present in the
environment as a function of time
• Get a SiNW banded with differentiated conduction/gate-able regions
Gudskien et. al. Nature 415 p617
Björk et. al. Nanoletters 2 p87
![Page 19: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/19.jpg)
UT Oct. 2004 -- DeHon
Enables: Differentiated Wires
• Can engineer wires– Portions of wire always
conduct) – Portions controllable
![Page 20: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/20.jpg)
UT Oct. 2004 -- DeHon
Coded Wires
• By selectively making bit-regions on wires either highly or lightly doped– Can give the wire an address
![Page 21: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/21.jpg)
UT Oct. 2004 -- DeHon
Unique Set of Codes
• If we can assemble a set of wires with unique codes– We have an address
decoder
![Page 22: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/22.jpg)
UT Oct. 2004 -- DeHon
Unique Set of Codes
• If we can assemble a set of wires with unique codes– We have an address
decoder• Apply a code
– k-hot code
• Unique code selects a single wire
![Page 23: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/23.jpg)
UT Oct. 2004 -- DeHon
Statistical Coding
• Unique Code set achievable with statistical assembly (random mixing)
• Consider: – Large code space (106 codes)– Large number of wires of each type (1012)– Small array (10 wires) chosen at random
• Likelihood all 10 unique? – Very high! (99.995%)
DeHon et. al. IEEE TNANO v2n3p165
![Page 24: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/24.jpg)
UT Oct. 2004 -- DeHon
Codespace: How Large?
• How large does code space really need to be?– Addressing N wires – With code space 100N2
– Has over 99% probability of all wires being unique
– For logarithmic decoder:• Need a little over 2 bits of sparse code
![Page 25: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/25.jpg)
UT Oct. 2004 -- DeHon
Switches / Memories
MolecularSwitches
Collier et. al.Science 289 p1172
Electrostatic Switches
Ruekes et. al.Science 289 p04
![Page 26: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/26.jpg)
UT Oct. 2004 -- DeHon
Common Switchpoint Properties
• Fit in space of NW crossing
• Hysteretic I-V curves
• Set/reset with large differential voltage across crosspoint
• Operate at lower voltage
![Page 27: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/27.jpg)
UT Oct. 2004 -- DeHon
Memories
![Page 28: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/28.jpg)
UT Oct. 2004 -- DeHon
Basis for Sublithographic Memory
![Page 29: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/29.jpg)
UT Oct. 2004 -- DeHon
Precharge all lines low
![Page 30: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/30.jpg)
UT Oct. 2004 -- DeHon
Drive Column Read Address
![Page 31: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/31.jpg)
UT Oct. 2004 -- DeHon
Pulls Single Column Line High
![Page 32: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/32.jpg)
UT Oct. 2004 -- DeHon
On xpoint allow to pull Row lines to be pulled high
Assume here: only the two points shown are “on”.i.e. column has 0 1 0 0 1 0
![Page 33: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/33.jpg)
UT Oct. 2004 -- DeHon
All Rows Disabled
Read outputnot driven;sees 0
![Page 34: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/34.jpg)
UT Oct. 2004 -- DeHon
Select Read Row 1010
Read outputnow pulledhigh; sees 1
![Page 35: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/35.jpg)
UT Oct. 2004 -- DeHon
Select Read Row 1100
Read outputnot driven;sees 0
![Page 36: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/36.jpg)
UT Oct. 2004 -- DeHon
…on to Logic…
![Page 37: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/37.jpg)
UT Oct. 2004 -- DeHon
Diode Logic
• Arise directly from touching NW/NTs
• Passive logic
• Non-restoring
• Non-volatile Programmable crosspoints
![Page 38: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/38.jpg)
UT Oct. 2004 -- DeHon
Use to build Programmable OR-plane
• But..– OR is not universal– Diode logic is non-restoring no gain, cannot
cascade
![Page 39: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/39.jpg)
UT Oct. 2004 -- DeHon
PMOS-like Restoring FET Logic
• Use FET connections to build restoring gates
• Static load– Like NMOS
(PMOS)
• Maybe precharge
![Page 40: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/40.jpg)
UT Oct. 2004 -- DeHon
Ideal vs. Stochastic Restore
![Page 41: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/41.jpg)
UT Oct. 2004 -- DeHon
Simple Nanowire-Based PLA
NOR-NOR = AND-OR PLA Logic
![Page 42: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/42.jpg)
UT Oct. 2004 -- DeHon
Defect Tolerant
All components (PLA, routing, memory) interchangeable;Have M-choose-N propertyAllows local programming around faults
![Page 43: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/43.jpg)
UT Oct. 2004 -- DeHon
Simple PLA Area• 60 OR-term PLA
– Useable
• 131 raw row wires– Defects
– Misalign
• 171 raw inverting wires– Defects
– Statistical population
• 60M sq. nm.– (2 planes)
90nm support lithography;10nm nanowire pitch
![Page 44: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/44.jpg)
UT Oct. 2004 -- DeHon
Crosspoint Defects• Crosspoint junctions may be
nonprogrammable– E.g. HPs first 8x8 had 85%
programmable crosspoints
• Tolerate by matching nanowire junction programmability with pterm needs
• Less than ~10% overhead for crosspoint defect rates up to 20%
Naeimi/DeHon, FPT2004
![Page 45: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/45.jpg)
UT Oct. 2004 -- DeHon
Interconnected nanoPLAs
![Page 46: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/46.jpg)
UT Oct. 2004 -- DeHon
Tile into Arrays
![Page 47: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/47.jpg)
UT Oct. 2004 -- DeHon
Manhattan Routing
![Page 48: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/48.jpg)
UT Oct. 2004 -- DeHon
Manhattan Routing
![Page 49: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/49.jpg)
UT Oct. 2004 -- DeHon
Tile into Arrays
![Page 50: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/50.jpg)
UT Oct. 2004 -- DeHon
Complete Substrate for Computing
• Know NOR gates are universal
• Selective inversion• Interconnect structure for
arbitrary routingCan compute any logic
function
• Can combine with nanomemories
![Page 51: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/51.jpg)
UT Oct. 2004 -- DeHon
Interconnected nanoPLA Tile
![Page 52: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/52.jpg)
UT Oct. 2004 -- DeHon
Analysis
![Page 53: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/53.jpg)
UT Oct. 2004 -- DeHon
Ideal vs. Stochastic Restore
![Page 54: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/54.jpg)
UT Oct. 2004 -- DeHon
Various Area Models
![Page 55: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/55.jpg)
UT Oct. 2004 -- DeHon
Technology:Lithographic Support
+ Diode Pitch
![Page 56: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/56.jpg)
UT Oct. 2004 -- DeHon
Area Mapped Logic
• Take standard CAD/Benchmark designs– Toronto20 used for FPGA evaluation
• Map to PLAs
• Place and Route on arrays of various configurations
• Pick Best mapping to minimize Area
![Page 57: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/57.jpg)
UT Oct. 2004 -- DeHon
Mapped Logic Density (105/10/5)
![Page 58: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/58.jpg)
UT Oct. 2004 -- DeHon
Cycle Delay:105/10/5/Ideal Restore/Pc=0.95
![Page 59: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/59.jpg)
UT Oct. 2004 -- DeHon
Power Density (per GHz)
• Vdd=1V• Active Power• Precharge
![Page 60: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/60.jpg)
UT Oct. 2004 -- DeHon
Construction Review
• Seeding control NW diameter• Timed growth controls doping profile along NW• LB flow to assemble into arrays• Timed etches to separate/expose features• Assemble on lithographic scaffolding• Stochastic construction of address coding allow
micronanoscale addressing• Differentiate at nanoscale via post-fabrication
programming• All compatible with conventional semiconductor
processing – Key feature is decorated nanowires
![Page 61: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/61.jpg)
UT Oct. 2004 -- DeHon
Summary• Can engineer designer structures at atomic scale• Must build regular structure
– Amenable to self-assembly
• Can differentiate– Stochastically– Post-fabrication programming
• Sufficient building blocks to define universal computing systems without lithography
• Reach or exceed extreme DSM lithography densities– With modest lithographic support
![Page 62: UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson,](https://reader035.vdocument.in/reader035/viewer/2022062322/56649e965503460f94b9a01e/html5/thumbnails/62.jpg)
UT Oct. 2004 -- DeHon
Additional Information
• <http://www.cs.caltech.edu/research/ic/>
• <http://www.cmliris.harvard.edu/>