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Intuitive, High Performance, High Capacity Debug Solution Mark Handover UVM Debug using Visualizer Debug Environment

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  • Intuitive, High Performance,

    High Capacity Debug Solution

    Mark Handover

    UVM Debug usingVisualizer Debug Environment

  • Restricted © 2018 Mentor Graphics Corporation

    Where Verification Engineers are Spending Time2 working days spent in debug every week

    ◼ Debugging (44%)— Complexity & Predictability

    ◼ Running Simulation (21%)— Speed & Capacity

    ◼ Testbench Development (19%)— Stimulus, Coverage, & Re-use

    ◼ Test Planning (14%)— Metrics, Analysis, & Process

    Source: Wilson Research Group and Mentor Graphics, 2018 Functional Verification Study

    44%

    21%

    19%

    14% Debug Simulation

    Testbench

    Planning

    Other

    2 DVClub 2019

  • Restricted © 2018 Mentor Graphics Corporation

    Top Debug ChallengesProductivity needs for today’s complex debug environment

    ◼ Capacity— Capacity to load 500M+ gate designs in seconds

    ◼ Debug efficiency— Full debug visibility + fast simulation— Load large designs in seconds

    ◼ Testbench debug — Debug dynamic objects — Post and Interactive debug mode

    ◼ Unified platform debugger— Single debugger for Simulation, Emulation, Low Power, Formal — Reduced learning curve

    3 DVClub 2019

  • Restricted © 2018 Mentor Graphics Corporation

    QUESTA FORMAL

    Visualizer - Tackling Debug ComplexitySingle debug solution for complex heterogeneous verification environment

    ◼ All Engines— Questa Simulation— Questa Formal Verification— Questa Clock Domain Checking— Questa Verification IP— Questa Low Power— Veloce Emulation— Veloce FPGA Prototyping— Calypto Synthesis

    ◼ All Technologies— UVM Debug— UPF Debug— RTL Design Debug— Transaction Level Debug

    Hardware & Software Views

    Transactions to Transistors

    VELOCE EMULATION

    QUESTA SIMULATION

    Interactive & Off-Line

    4

    FPGAPROTOTYPE

    DVClub 2019

  • Restricted © 2018 Mentor Graphics Corporation

    Visualizer Debug EnvironmentFeatures+ Performance + Memory Footprint + Capacity

    DVClub 20195

    Visualizer

    Power DB

    Wave DB

    GUI

    Design DB

    Analysis

    Reconstruction

    ◼ Simulation Performance— 2-4x simulation performance

    ◼ Memory — 2-3x reduction in memory footprint

    ◼ Capacity— Loads 500M+ gate designs in seconds— Go to debugger for large GLS designs

    ◼ UVM debug - live and Post sim

  • Restricted © 2018 Mentor Graphics Corporation

    Full Design/TB Visibility by defaultReducing the latency of root-cause analysis

    Regression Triage

    8am

    Run#2

    Enable Debug TraceWith 1st trace set

    9am

    Debug

    10am

    Run#3Add more traces& data collection

    11am

    Debug

    12pm

    Run#4Still More VisibilityAdd $display() Debug

    1pm

    Debug...

    2pm

    Run fast!(no trace)

    Enabling efficient debug

    ◼ Minimum trace set for fast simulation and compact results

    ◼ High performance “smart” reconstruction of signals

    ◼ Save Time by Capturing More Data, Faster, First Time

    Classic debug flow

    Visualizer debug flow

    DVClub 20196

  • Restricted © 2018 Mentor Graphics Corporation

    UVM DEBUG

  • Restricted © 2018 Mentor Graphics Corporation

    Debug UVM in Post Sim mode

    ◼ Traditional debug— I need interactive/live simulation to

    debug my UVM TB— Post Sim debug is for 1’s and 0’s

    ◼ Visualizer debug— Visualizer treats Class as a first class

    object

    DVClub 20198

  • Restricted © 2018 Mentor Graphics Corporation

    Simplified UVM Debug and NavigationIntuitive Navigation of UVM TB

    ◼ Traditional debug— Manually trace connectivity to view

    and debug UVM TB

    ◼ Visualizer –— Use UVM Schematic View as a Map

    – View existing TBs or use it as a navigation vehicle

    — View all handles and variables— Easy navigation by class hierarchy

    or schematic

    DVClub 20199

  • Restricted © 2018 Mentor Graphics Corporation

    Finding Config Database MismatchesSimplified debug of Config objects

    ◼ The Config DB is a data exchange— Can set or get values anywhere in the testbench

    DVClub 201910

  • Restricted © 2018 Mentor Graphics Corporation

    Understand Hierarchy of SequencesIntuitive Debug for Your UVM Sequences

    ◼ Traditional manual debug does not scale

    ◼ Visualizer Debug: Live sequence hierarchy activity by sequencer

    DVClub 201911

  • Restricted © 2018 Mentor Graphics Corporation

    UVM Class Debug in Waveform View

    ◼ Easy to drag into waveforms from source or object

    ◼ Add handles to waves, see member values over time

    ◼ Simple to see any Testbench transaction to your DUT

    DVClub 201912

  • Restricted © 2018 Mentor Graphics Corporation

    Live Simulation

    ◼ Interactively single step and add breakpoints

    DVClub 201913

  • Restricted © 2018 Mentor Graphics Corporation

    Visualizer – Enabling Cross-Platform DebugIntegrated UVM Questa and Veloce Debug

    ◼ Support TBX flow — Single GUI to view and debug waveform data from Simulator and emulator

    DVClub 201914

    Class Instances

    TB and DUT Waveform

  • Restricted © 2018 Mentor Graphics Corporation

    Visualizer™ Debug Environment

    ◼ Built for Speed— High Performance, Capacity, Visibility

    ◼ Increases Debug Flow Productivity— Intuitive and easy-to-use — Powerful automation, find bugs fast

    ◼ Supports Complex Projects— Native SV Class Debug— UVM Navigation and Debug

    ◼ Built for All Today’s Platforms— Questa Simulation, Veloce Emulation— Formal, System-level, UPF

    15 DVClub 2019

  • Restricted © 2018 Mentor Graphics Corporation

    The Verification Academy

    DVClub 201916

    ◼ www.verificationacademy.com

    http://www.verificationacademy.com/

  • Restricted © 2018 Mentor Graphics Corporationwww.mentor.com