vcsel arrays for high-aggregate bandwidth of up to 1.34 ... arrays for high aggregate... · vcsel...

VCSEL arrays for high aggregate bandwidth of up to 1.34 Tbps Martin Grabherr, Steffan Intemann, Roger King, Stefan Wabra, Roland Jäger, Michael Riedl

Philips Technologie GmbH U-L-M Photonics, Lise-Meitner-Str.13, 89081 Ulm Germany

Abstract Even though the lane speed of VCSEL based AOC and transceivers has reached 25 Gbps and beyond [1-7], parallel optics are getting even more important in order to meet the increasing demand for aggregate bandwidths in upcoming applications, among others, 100 Gigabit Ethernet, Infiniband EDR, or EOM (embedded optical modules). As 100 Gbps can be achieved by, e.g., 4 times 25 Gbps using standard QSFP form factor, different approaches are using large scale 2D VCSEL arrays operating at lower lane speeds. Early work on 2D VCSEL based transceivers has already been presented beginning of this century [8] and recent work also addressed the potential of this technology [9,10]. In 2013, Compass EOS has introduced a 1.34 Tbps core router solution [11,12,13] that incorporates 2D VCSEL arrays of 14x12 emitters designed and manufactured by Philips U-L-M Photonics. The VCSEL array is mounted face down onto a CMOS ASIC, directly on top of the analog area. The emission wavelength of 1000 nm allows for substrate side emission and thus for flip-chip mounting as well as the possibility of integrating 2D microlens arrays onto the stack of CMOS and VCSEL array. After briefly introducing the router with regard to the incorporated VCSEL technology we discuss the design and performance of the VCSEL array. Finally, the assembly solution for this most compact and dense transceiver solution is presented.

Keywords: VCSEL, VCSEL array, EOM, flip-chip, chip-on-chip

Introduction Within routers, data distribution between line cards has been identified as one main bottleneck for performance. In 2013 Compass EOS introduced the r10004 Router which incorporates an optical transceiver solution based on 12x14 channels and according fiber management for data distribution between line cards as well as racks [11]. The full duplex 1.34 Tbps transceivers provide 64 Gbps/mm² data density. Fig. 1 shows the compactness of the r10004 Router which also provides very low power consumption of only 10.2 pF/bit, incl. SERDES on smallest footprint. The transceiver is monolithically built into the CMOS ASIC by monolithic analog & digital ASIC design, and the VCSEL and PD arrays are flip-chip mounted onto the analog part of the ASIC [13]. The subassembly is then flip-chipped onto a substrate carrying the ball grid array (BGA) that allows for on board system integration. In Fig 2. the two step flip-chip assembled optical module is presented, revealing the optical interfaces of VCSEL and PD arrays in the

Vertical-Cavity Surface-Emitting Lasers XVIII, edited by James K. Guenter, Chun Lei, Proc. of SPIE Vol. 9001, 900105 · © 2014 SPIE · CCC code: 0277-786X/14/$18 · doi: 10.1117/12.2039226

Proc. of SPIE Vol. 9001 900105-1

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Conclusion The r10004 Router released by Compass-EOS is making use of a primary VCSEL technology promise: the stacking of ASIC and 2D VCSEL array together with micro lens arrays for 2D fiber coupling that results in a most compact optical transceiver. The further demand for higher aggregate bandwidth will have to be addressed by increasing lane speeds even beyond 25 Gbps, but upscaling in orders of magnitude will only be possible by highly parallel solutions. Both directions need to be further enhanced simultaneously. Combining already demonstrated building blocks, like 28 Gbps single lane data rates and the presented assembly solution, the aggregate bandwidth already provides the capability to reach 4.7 Tbps.

Aknowledgements We acknowledge the cooperation and support of Compass EOS, especially through Kobi Hasharoni and Shuki Benjamin. Pictures 1,2,8,9,10,11,12,13,14,15 are courtesy of Compass EOS.

References [1] D. M. Kuchta et al., “A 55Gb/s Directly Modulated 850nm VCSEL-Based Optical Link”,

IEEE Photonics Conference 2012 (IPC 2012) Post Deadline Paper PD 1.5 (2012). [2] S.A. Blokhin et al., “850 nm VCSELs operating at bit rates up to 40 Gbit/s“, Electronics

Letters 45, pp. 501-503 (2009). [3] Toshihito Suzuki et al., “Reliability study of 1060 nm 25 Gbps VCSEL in terms of high

speed modulation”, Proc. SPIE 8276, pp. 04-01 to 04-8 (2012). [4] AVAGO Technologies, http://www.avagotech.com/pages/video_ofc2011_25g_vcsel

(2011). [5] Neinyi Li et al., “Emcore’s 1 Gb/s to 25 Gb/s VCSELs”, Proc. SPIE vol. 8276, pp. 03-1 to

03-10 (2012). [6] M. Grabherr et al., "25 Gbps and beyond: VCSEL development at Philips", Proc. of SPIE

Vol. 8639, pp. 0J-1 to 0J12 (2013). [7] Afriat Gil et al., "VCSEL based optical transceiver module operating at 25 Gb/s and using a

single CMOS IC", Proc. of SPIE Vol. 8282, paper 06, pp. 1-6 (2012). [8] M. Grabherr et al., „Comparison of approaches to 850 nm 2-D VCSEL arrays“,Proc. of

SPIE Vol. 4994, pp. 83-91 (2003). [9] Clint L. Schow et al., "A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled

Optical Transceiver Module Based on a Single “Holey” CMOS IC," J. Lightwave Technol. 29, 542-553 (2011).

[10] Pinxiang Duan et al., "A novel 3D stacking method for Opto-electronic dies on CMOS ICs," Opt. Express 20, B386-B392 (2012)


[11] Kobi Hasharoni et al., “A high end routing platform for core and edge applications based on chip to chip optical interconnect”, OTu3H.2, OFC/NFOFC (2013).

[12] S. Benjamin et al., “Assembly of 1.3 Tb/s Full Duplex Optical Module“, Proc. IEEE 63rd Electronic Components and Technology Conference (ECTC), pp. 292-296 (2013).

[13] Kobi Hasharoni et al., “A 1.3 Tb/s parallel optics VCSEL link”, Proc. SPIE vol. 8991, paper 10 (2014).

Proc. of SPIE Vol. 9001 900105-10

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