VEDIC MATHEMATICS BASED MULTIPLIER ACCUMULATOR UNIT

PRESENTED BY

NAVYASHREE S

(1VK09TE018)Dept of TCE, VKIT

UNDER THE GUIDANCE OF

RAJANI NASSISTANT PROFESSOR,TCE DEPT

CONTENTS

• INTRODUCTION

• GENERAL CONSTRUCTION OF MAC UNIT

• THE MULTIPLIER ARCHITECTURE

• VEDIC MULTIPLIER

• ADVANTAGES

• DISADVANTAGES

• CONCLUSION

• REFERENCE

INTRODUCTION

• Vedic mathematics is the name given to the ancient system of mathematics

which was rediscovered from the vedas.

• It gives explanation of several mathematical terms including arithematics,

geometry, trignometry and even calculus.

• It was constructed by Shri Bharati krsna theertaji (1884-1960), after his

eight years of research on Vedas.

• He constructed 16 main sutras and 16 sub sutras.

• The beauty of vedic mathematics is to reduce complex calculations into

simple one.

CONTINUED…

• Vedic mathematics sutras are powerful and useful even for astrological

calculations.

• In most of the digital signal processing applications, the critical operations

are multiplication and accumulation.

• The DSP functions extensively make use of the multiply-accumulate

(MAC) operation, for high performance digital signal processing system.

• The main motivation behind this work is to achieve high speed through

VLSI design and implementation of MAC unit architecture using

multipliers based on Vedic mathematics.

Example: vertical and cross wise

GENERAL CONSTRUCTION OF MAC UNIT

• A basic MAC architecture consist of a mulitplier and a accumulate adder .

• The MAC unit computes the product of two numbers and adds the product

to an accumulator register.

• It provides high speed multiplication, saturation and clear –to-zero function.

• Here the multiplier used is a vedic multiplier based on Urdhva

Tiryagbhyam sutra.

Fig 2:MAC Architecture

THE MULTIPLIER ARCHITECTURE

• The multiplier is based on an algorithm Urdhva Tiryagbhyam(Vertical and

crosswise ).

• This sutras shows how to handle multiplication of larger number (N X N

bits) by breaking it into smaller sizes.

• For multiplier, first the basic blocks, that 2x2 multiplier are made and then,

4x4 block , 8x8 block and 16x16 block have been made.

• The device selected for synthesis is Device family spartan 3E, device is

xc3s500, package of fg320.

VEDIC MULTIPLIER

•The 2x2 Vedic multiplier modules has been implemented using two

half-adder modules as shown in Fig. 4. The total delay is 2-half adder

delays, once the bit products are generated.

• The Implementation Equations of 2x2 Vedic multiplier modules are:

• R0(1-bit)=b0a0

• R1(1-bit)=b0a1+b1a0

• R2(1-bit)=b1a1+c1

•Product=R2 & R1 & R0

Fig 4:BLOCK DIAGRAM OF 2x2 MULTIPLIER MODULE

Eg :Multiplication of 2 decimal numbers : 43*68

• Consider the multiplication of two decimal numbers (43*68).

•The digits on both sides of the line are multiplied and added with

the carry digit.

•This carry is added in the next step and hence the process goes on.

If more than one line are there in one step, all the results are added to

previous carry.

•In each step, unit’s place digit acts as the result bit while the higher

digits act as carry for the next step.

•Initially, the carry is taken to be zero..

4 3 4 3 4 3

Fig 3: Multiplication of 2 digit decimal numbers using Urdhva Tiryagbhyam sutra.

STEP 1 STEP 2 STEP 3

6 8 6 8 6 8

3 2

2 4

1 8

5 2final product

partial product

carry

2 4

2 9 2 4

Multiplicands

Fig 4:Using Urdhva Tiryagbhyam for Binary numbers

  STEP 1 STEP 2 STEP 3 STEP 4

1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

STEP 5 STEP 6 STEP 7

1 1 0 1 1 1 0 1 1 1 0 1

1 0 1 0 1 0 1 0 1 0 1 0

• LSB are multiplied which gives the LSB of the product (vertical).

• The LSB of the multiplicand is multiplied with the next higher bit of the

multiplier and added with the product of LSB and next higher bit of the

multiplicand (crosswise).

• The sum gives the second bit of the product and the carry is added to the next

stage sum obtained by crosswise and vertical multiplication.

• All four bits , are processed with crosswise multiplication and addition to give

sum and carry.

• The sum is corresponding bit of the product and carry is again added to the

next stage addition and multiplication of three bits except the LSB.

• The same operation continues until the multiplication of two MSBs to give

the MSB of the product.

CONTINUED…

Fig 5:Better implementation of Urdhva Tiryagbhyam sutra for binary numbers

Continued..

• A 4x4 multiplication is simplified into 4, 2x2 multiplication that can be

performed in parallel.

• This reduces the number of stages of logic and thus reduces the delay of the

multiplier.

• This example illustrates a better and parallel implementation style of

Urdhva Tiryagbhyam sutra.

ADVANTAGES• Vedic multiplier is faster than the array multiplier and booth multiplier.

• The area needed for vedic multiplier is very small as compared to other

multiplier architecture.

• MAC is used in modern digital signal processing.

• MAC always lie in the critical path that determines the speed of the overall

hardware systems.

DISADVANTAGES

• For complex multiplications, even the system becomes complex.

CONCLUSION• The proposed vedic mathematics based MAC unit proves to be highly

efficient in terms of speed. Due to its regular and parallel structure ,it can be

realised easily on silicon as well.

REFERENCE• Maharaja, J.S.S.B.K.T ., “VEDIC MATHEMATICS”, Motilal banarasidass

Publishers Pvt. Ltd, Delhi, 2009.

• Amandeep singh , “Design and hardware realisation of a 16-bit Arithematic

unit”,THAPAR UNIVERSITY(2010).

• B. Parhami, "Computer Arithmetic Algorithms and Hardware

Architectures", 2n d ed, Oxford University Press, New York, 2010.

THANK YOU