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Verification of a Cache Coherent system with an A53 cluster using ACE VIP with Graph Based StimulusGalen BlakePerry WobilAltera Corporation

September 18, 2015Austin, TX

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Agenda

Verification of Cache Coherent Access from an FPGA

Graph Based Multi Context Stimulus Concepts

Application to a Cache Coherent SOC-FPGA system

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Verification of Cache Coherent Access from an FPGA

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System Description

• An ARM quad A53 cluster

• A Cache Coherent Interconnect to coordinate coherent transactions

• Customer Defined V8 compliant ACE agent synthesized into the FPGA soft Logic

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Block Diagram of Test Bench & DUT

ACE

CPU0 CPU1 CPU2 CPU3

L2 CacheAC

ELite

System Memory

AXI4 Cache Coherent Interconnect

SCU

OC

RAM

ACELITE

ARM A53 MPU Cluster

ACE

L3 Interconnect

Cache

FPGACustomer Design

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Verification Challenges

• How do we model a customer defined ACE agent– In our case we chose the Synopsys ACE VIP– It can be configured in many different ways to match

potential customer configurations– A key feature needed is the local cache to support all ACE

coherent transactions that require data allocation.

• How do we generate C and UVM stimulus, coordinate and check cacheable transactions– In our case we chose the Breker Trek-SoC tool– It is capable of generating C code for the A53 and UVM

sequences for the ACE VIP and automatically coordinates and checks the coherent traffic from each of them

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Graph Based Stimulus Concepts

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Graph Construction

• Graphs are constructed from a C like language that describes a functional space or protocol

• The language is then used to construct a graph

• The graph can be used to review for accuracy and documentation

• This is an example of an ACE graph

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Graph Elements • Decision points• Transactions• Transaction Properties

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Graph Construction

• A big picture view of the complete ACE graph

• The language used is currently proprietary

• There is an active working group in Accelerra [pswg] working to standardize this type of language

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Application to a Cache Coherent Interconnect System

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DUT

Block Diagram of Test Bench & DUT

ACE

CPU0 CPU1 CPU2 CPU3

L2 Cache

ACELite

ACE_L_VIP_s(Memory)

AXI4 Cache Coherent Interconnect

SCU

OC

RAM

ACELITE

TrekSoc

AXI_master_trek_sequence

Trektest.c

Backdoor_access

ACE_VIP_MON

AXI4_VIP_MON

C-A53 MPUAC

E

ACE_L_VIP_m

Cache

SynopsysACE_VIP_m

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Stimulus Generation & Synchronization

ACE C-Based Transactions

CacheCoherencyApp

trek_test.c trek_test.tbx

Embedded C

ARM CPU ACE VIP Master

UVM VIP Sequence

Trek Mail BoxACE UVM Transactions

Cache Coherency Interconnect

TrekSoC

ACE ACE

import "DPI-C"

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Big picture view.Shows A53 and UVM events

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Tracing activity on one cache lineCoherent block transaction initiated on CPU which targets a memory cache line

Coherent transaction initiate on VIP to cause snoops on target address

Chain of Coherent TXNs that operate on target cache line

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Tracing activity on one cache line

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Details about CPU based events

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Tracing activity on one cache line

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Details about a VIP (UVM) event

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Runtime view of a failed eventSubtitle if Needed

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Conclusion• It only took one week to complete the following

– Install the Breker Trek tool– Integrate the tool into embedded SW (Make) flow– Integrate the tool with the Synopsys VIP UVM sequences– Develop highly complex coherent system traffic

• We also found an RTL bug that second week

• Since that time we have also deployed both the Breker Trek and Synopsys ACE and DDR VIP to develop complex traffic for our memory sub system

• Currently working to extend this verification methodology of graph based stimulus and UVM components to “non-AMBA” areas of SOC

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Thank You