Procedia Engineering 29 (2012) 1276 – 1280

1877-7058 © 2011 Published by Elsevier Ltd.doi:10.1016/j.proeng.2012.01.126

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Procedia Engineering 00 (2011) 000–000

ProcediaEngineering

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2012 International Workshop on Information and Electronics Engineering (IWIEE)

Verification of All-Digital SPARC Instruction Set Based on FPGA

Kai Cui*, KuanJiu Zhou, Jie Wang, Sun Hao, Chuang Lin

School of Software of Dalian University of Technology 116621 Dalian, P.R. China

Abstract

Due to the closeness of an embedded system, to test in the embedded software is extremely difficult, especially for real-time embedded software. It is no doubt that instruction set simulation(ISS) system based on embedded SoC will greatly reduce difficulties of embedded software testing. Therefore, to make sure the credibility of the instruction set simulation system it is especially important. The huge number of random test cases generated during testing makes it unable to determine the running results. A method of hardware and software collaborative verification based on FPGA Leon core and microcomputer software SPARC instruction set is proposed to solve both the efficiency in traditional software testing and the accuracy in determining running results problems effectively. Ten test cases from the Mibench standard test set are selected for hardware and software collaborative verification. The statistical results show the instruction coverage of all-digital SPARC V8 simulator reaches 97 percent.

© 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Harbin University of Science and Technology

keywords: SPARC Instruction Set, Hardware and Software Collaborative, FPGA, Leon ;

With the rapid development of embedded integrated circuit technology in aviation, highly integrated embedded systems are also applied in this field. Currently SoC (System on Chip) has become a trend in international VLSI (Very Large Scale Integrated circuits) and a mainstream in integrated circuits, which is becoming an essential solution to low-cost, low-power and high-performance embedded systems [1].Benefit from the progress of microelectronics technology, high-performance FPGA products have become the main support platform of processor technology research [2, 3], which provides important verification support for the debugging of embedded system simulation software, including its

* Corresponding author. Tel.: +86+13478727517 E-mail address: ck.dut@163.com

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transparency, credibility and correctness judgment of results. A software-hardware co-simulation verification method is discussed in this paper, which is based on all-digital SPARC instruction set simulator and hardware simulator. This method can verify the functions of the all-digital simulation system in each period of SoC design. It can not only improve the credibility of instruction set simulation system design and the accuracy of determining running results, but also can improve the efficiency of software simulation and verification.

1. All-digital SPARC ISS Platform

The SPARC 1.0 has been developed to simulate SPARC V8 architecture microprocessor, which implements 197 instructions (including integer instructions, floating instructions) simulation. According to simulation functions, SPARC microprocessor can be divided into the following modules: the five-stage instruction pipeline, the integer operation, the float operation, the load or store operation, the bus interface and so on. Figure 1 shows the framework of the all-digital SPARC instruction simulator, which includes the compilation function module and the instruction cycle accurate tracking module. The compilation function module is to fetch, decode and execute an instruction word, and track the executing process in a loop queue. The instruction cycle accuracy tracking module continues to track the instruction fetch and accurately simulates the instruction cycle. The all-digital SPARC instruction simulator is developed with C++ language.

Fig.1 Framework of the All-digital SPARC Instruction Simulator Fig.2 Software and hardware co-verification process

In order to verify the processor simulator is consistent with the FPGA-based Leon core, the Mibench standard test programs are respectively tested on the SPARC ISS and the FPGA-based Leon core. The function verification can be finished by comparing the test results. Figure 2 shows the software and hardware co-verification process based on SPARC ISS and FPGA-based Leon core.The test cases running on FPGA can also run in the simulation environment. And the errors found in FPGA can be reproduced, debugged, traced and located in the simulation environment.

2. The FPGA Collaborative Verification Platform

The Leon core is a microprocessor based on SPARC V8 [4] RISC architecture and designed with HDL, which is developed and supported by Gaisler Research, a unit of the European Space Agency. Leon core is the successor to SPARC V7 architecture and the mainstream processor of European aerospace industry. Leon3 which is not synthesized is adopted for the co-verification in the experiment. The Leon3 core is a SoC core based on AMBA bus and contains a large register bank. The registers are organized by the classic method called register window. The register bank contains 136 general-purpose 32-bit integer registers. But the instruction system can only access 32 registers at a certain

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moment. In the Leon3 architecture, the SEU mainly affects the sequential logic of register bank, latch and cache. Therefore, the following work mainly focuses on the fault injection to those sensitive parts to get their reliability assessment results [5].

3. Software-hardware Co-verification Method Research

3.1 Characteristics of Software-hardware Co-verification

The software-hardware co-verification method based on all-digital SPARC ISS and hardware simulator is a high reliability, low cost solution to processor function verification [6], due to the complicated structure and large-scale features of SoC. On the basis of C++ which is executed in the form of interpretation, this method can easily verify the all-digital simulation platform. A software- hardware co-verification environment for SoC is constructed on windows platform based on the above co-verification method. The instruction pipeline scheduling algorithm’s structure of this all-digital simulator is shown in Figure3.

Instruction pipeline algorithm is described as follows:

Fig.3 Instructions processing algorithm

The SPARC ISS based on SPARC V8 architecture is designed in C++ and the Leon core applies FPGA compiled event-driven VHDL simulation. Leon core, this verification tool, adopts the Leon3 [6]

designed by Gaisler, a unit of the Central European Space Agency. The implementation technologies of instruction set simulator and hardware simulator have been discussed in numerous literatures [7, 8]. The following discussion focuses on the dealing methods and the interactive events between software and hardware during the co-verification process. Beyond that, the synchronous optimization algorithms between software and hardware simulators will be referred, which are the key technologies in software-hardware co-verification method.

3.2 Composition of hard-software co-verification method

As shown in Figure 4, the entire SPARC processor software-hardware co-verification frame- work is composed of four modules, including standard test cases preparing module tested by C++ code detector, software simulation platform, hardware validation platform and simulation results collaborative comparison module.

Instruction set simulator, based on FPGA Leon core, is a tool used in simulating program execution process. The module is designed to compare the output of standard test program both on all-digital software simulation platform and hardware validation platform, obtain validation results, so as to analyze the accuracy of simulation system. We are able to gradually check execution results of upper level via single-step debugging function of software simulation platform if mistakes are found in comparison result,

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as shown in Figure 5. The SPARC all-digital ISS, developed in C++, applies the Leon core based on FPGA to verify the accuracy and adopts the MiBench as the standard test cases. Figure 6 shows the SPARC all-digital ISS, Table 1 shows the Running environment.

Fig.4 Validation process design Fig.5 SPARC all-digital simulation interface

3.3 Software- hardware co-verification experimental results

Fig.6 MiBench multiple data dynamic instructions distribution [9] Fig.7 Selection of test cases experimental results distribution

Tab.1 Running environment Tab.2 Other instructions coverage

Many benchmarks have been proposed such as Dhrystone [10], LINPACK [11], Whetstone [12], CPU2

[13], MediaBench [14] which are targeted towards specific areas of computation. Dhrystone is for system (integer) performance; LINPACK is for vectorizable computations; Whetstone and CPU2 are for numerical (floating point) intensive applications; and MediaBench is for multimedia applications. The other benchmarks are available to stress network stacks, data input/output and other specific tasks.

Several characteristics distinguish the Mibench from the existing commercially representative SPEC2000 benchmarks including instruction distribution, memory behaviour, and available parallelism. The literature [6] shows the instruction distribution of the MiBench programs as shown in Figure 6. The small data sets for MiBench are approximately 50 million dynamic instructions while the large data set has more than 750 million dynamic instructions. Mibench consists of six categories including Automotive,

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Network, Security, Consumer Devices, Office Automation, and Telecommunications. Six benchmarks in MiBench are applied to conduct experiments. The instruction distribution statistics are shown in Figure 7 and Table 2.

4. Conclusions

The SPARC all-digital ISS，developed in C++ language applies the Leon core based on FPGA to verify the accuracy and adopts the MiBench as the standard test cases. With the comparison between the test results of the all-digital IIS and the outcome of the Leon core, the similarity reaches 98%, which validates the reliability and accuracy of the all-digital SPARC ISS platform. The instruction coverage shows that the method is feasible, effective and accurate.The error rate of two percent is due to some orders of magnitude gap caused by the efficiency of all-digital SPARC ISS and the Leon core. This problem will be the focus of the future. The software-hardware co-verification method has good general applicability and can be applied to analyzing other digital instruction set simulation platform after modified which provides a basis for future verification on all-digital SPARC multi-core simulation and task scheduling, instruction processing in multi-core.

Acknowledgements

The research is supported by the National Natural Science Funds of China (91018003) and the Fundamental Research Funds for the Central Universities (1600-852007).

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