verification of hpes
TRANSCRIPT
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Verification of High Performance
Embedded Systems
Sisira K. Amarasinghe, Ph.D.
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex SystemsConclusionQuestions and Answers
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances , home automation ,
consumer electronics , ATMs , networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (2/4)
Designed for some specific tasks
Subjected to real time performanceconstraints that must be met
Feature tightly integrated combinationsof hardware and software
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex SystemsConclusionQuestions and Answers
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High Performance Embedded Systems (1/10)
Massive computational resources withrequirements of Small size Low Weight Very low power consumption.
Need to employ innovative, advancedsystem architectures
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High Performance Embedded Systems (2/10)
Architectures typically feature Multiple processor cores Tiered memory structures with multi-level
memory caching Multi-layer bus structures. Super-pipelining and/or super-scaling
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High Performance Embedded Systems (3/10)
The current state-of-the-art:Multiple computational and data-processing engines, memory, andperipherals, all constructed on a singlesilicon chip called a System-on-Chip(SoC) .
Designs to feature multiple general-purpose central processing unit (CPU)cores as well as special-purpose digitalsignal processor (DSP) cores
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High Performance Embedded Systems (5/10)
Embedded designs to include multiplegeneral-purpose central processing unit(CPU) cores as well as special-purpose
digital signal processor (DSP) cores
Firmware
Peripherals
Core 1 Core 2
Memory
Core 3
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High Performance Embedded Systems (6/10)
Multilayer Bus Structures CPU and DSP cores can have separate
buses for control, instructions, and data, DMA buses along with one or more
dedicated peripheral buses. Both the CPUs and DSPs can have
tightly-coupled memory buses, externalmemory buses, and shared memorybuse s.
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Increasing software content The software content of embedded systems
is increasing at a phenomenal rate software development and test often
dominate the costs, timelines, and risksassociated with today's embedded systemdesigns.
High Performance Embedded Systems (7/10)
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High Performance Embedded Systems (8/10)
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Decreasing design cycles Market windows are continually narrowing Competition gets more and more aggressive Consumer electronics markets are extremely
sensitive to time-to-market pressures
High Performance Embedded Systems (9/10)
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex Systems
ConclusionQuestions and Answers
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Validation
Validation confirms that the product, as
provided, will fulfill its intended use. Inother words, validation ensures that youbuilt the right thing .
Verification and Validation (2/7)
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Verification and Validation (3/7)
Why Verification and Validation? Business considerations
Legal Refutation Warranty / Recall
Regulatory issues FDA FAA DoD
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Safety considerations Life sciences Mission critical Automotive examples:
Drive by wireElectronic throttle controlElectronic steering
ABS Airbag Systems
Verification and Validation (4/7)
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Verification and Validation (5/7)
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Abstraction Levels of Design Under VerificationBehavioral Model
Example: c
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Importance of Verification in Early Design Stages
Behavioral RTL Gate Level Transistor
Revenue lossdue to delay inTime-To-Market
Remove as many bugs as possible in early designs stages
Ease of verification
Source: Verification Methodology Manual, 2000 - TransEDA
Verification and Validation (7/7)
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex Systems
ConclusionQuestions and Answers
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Determine the overall systemarchitecture
Design System Hardware
Construct hardware prototype
Install and test OS and/ormiddleware
Develop, port, integrate, anddebug embedded software
Conventional Verification of Embedded Systems(1/13)
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Important hardware/software tradeoffscan t be made before the designpartitioning is locked down and the chips
are manufactured System design must be largely based
on experience and intuition, as opposedto hard data .
Unacceptable in today's complexalgorithms, multi-core systems, tieredmemory systems, and multi-layered
bus structures.
Conventional Verification of Embedded Systems(4/13)
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Hardware acceleration and emulation as verification mechanism These typically involve arrays of field-
programmable gate arrays ( FPGAs ) orprocessors.
These solutions accept RTL
representations of the design andtranslate them into an equivalent suitablefor hardware acceleration .
The verification can get very costly
Conventional Verification of Embedded Systems(5/13)
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Issues in multi-processor designs Emulators also have problems with
limited visibility into the design Software development cannot commence
until a long way into the design cycle.(The hardware design is largelyestablished limitations with regard toexploring and evaluating alternativearchitectures)
Conventional Verification of Embedded Systems(6/13)
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RTL-based simulation as verificationmechanism An RTL simulation solution requires RTL
representations of the hardware Delays in meaningful softwaredevelopment until the RTL becomesavailable
It simply isn't possible to use softwaresimulation to determine how well thearchitecture performs on real software
workloads
Conventional Verification of Embedded Systems(7/13)
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A software simulation running on a onvery high-end (and correspondinglyexpensive) machine would hardly achieve
equivalent simulation speeds of morethan a few Hz That is, a few cycles of embedded system
clock for each second in real time
Detailed simulations can be performed on onlysmall portions of the software.
Conventional Verification of Embedded Systems(8/13)
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex Systems
ConclusionQuestions and Answers
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Verification of Complex Systems (1/15)
System-On-Chip (SoC) designs increasinglybecome the driving force of a number ofmodern electronics systems
A number of key technologies integratetogether in forming the highly complexembedded platformVerification need to account for integrationof a number of different IPs into newdesigns, the coupling of embedded softwareinto designs, and the verification flow from
core to the design, etc. 37 of
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IP Core Verification and System LevelVerification both need to be addressedadequately
On top of structural complexities, furtherbottlenecks are introduced by: Time to market pressures
Increasing software content Other stringent design constraints such assize, weight, low power levels, etc.
Verification of Complex Systems (2/15)
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The system level design strategies shouldbe considered together with the complextask of verification
Hardware , first, then software, is no longera viable themeAppropriate verification strategies need tobe employed from the outset to minimizedownstream defects including SoC re-spinsConcurrent hardware and softwaredevelopment would mandatory.
Verification of Complex Systems (3/15)
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SoC architects to employ a broad systemlevel design strategy that will allow: Explore and evaluate system level
architectural choices Concurrent hardware-software design Easily evaluate and integrate a number of
different technologies Adequate verification at every level of the
design cycle
Verification of Complex Systems (4/15)
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Carry out an architecture level poweranalysis
Drive requirements for executablespecifications
Provide visibility into designs Easily handle regression testing
How do we achieve all thiswith such complexity?
Verification of Complex Systems (5/15)
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The answer to all above is to employ aUnified System Model without committingto any pre-conceived hardware / software
partitioning.This will be a type of electronic systemslevel (ESL) prototypeThe form of these models can be anywherefrom a cycle-accurate RTL model and to atime-efficient ISS model, or a hybrid
Verification of Complex Systems (6/15)
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Source: Mixed-Abstraction Virtual System Prototypes
Close SOC Design Gaps, Carbon Design Systems, Inc.
Verification of Complex Systems (7/15)
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Verification of Complex Systems (8/15)
Running Speed
10Hz
100Hz1KHz
10KHz
100KHz
1MHz
10MHz
100MHz
SW Simulator
Investment
HW Emulator
Rapid Prototype
Real Silicon
HW Accelerator
Ideal VerificationIdeal Verification
SolutionSolution
Make it fasterMake it faster
Make it cheaperMake it cheaper
Ideal VerificationIdeal Verification
SolutionSolution
Make it fasterMake it faster
Make it cheaperMake it cheaper
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The basis for a unified system model isTransaction Level Modeling (TLM).
TransactionsBasic representation for exchange of information betweentwo blocksImprove efficiency and performance of verification by
raising the level of abstractions from the signal levelCan be as simple as a single data write operation orlinked together to form a complex IP packet transfer
Verification of Complex Systems (9/15)
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Transactions :
Source: Cadence white paper, The Unified Verification Methodology
Verification of Complex Systems (10/15)
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Stimulus Generation: Transactions
Transactor provides a level of abstraction between the pins ofthe model and the test code
Encapsulation : Test code does not need knowledge about the busprotocols
Abstraction : Allows test to be written in an abstract fashion that
specifies the required transactions, instead of the operationexecution details Re-use : Transactor provides a standard set of routines that the
test can call Modularity : Verification environment can be built from a set of
parts
DESIGNUNDER
VERIFICATION
Processor Bus
Test Code
Write (Addr, data)
Data = Read (Addr)
WriteOperation
ReadOperation
OthersOperations
TestInterface
BusDriver
Transactor
Verification of Complex Systems (11/15)
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C
Transactor
HDLC to HDL
EDIFSynthesis
Transactor
C ISSProcessor
Cross-compiler
Transactor
Transactor
Transactor
SW partmodel
W partmodel
Support functional design and verification at variousabstraction levelsAdvantages
Enhance reusability in the test-benches Improve debugging and coverage analysis
Transaction Level Models (TLM)Source: Chong- Min Kyung, Current Status and Challenges of SoC Verification for Embedded Systems Market, IEEE International
SOC Conference, 2003
Verification of Complex Systems (12/15)
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Unified System Model: Functional PrototypeUnambiguous executable specificationGolden top-level verification environment and integration vehicleReference for defining transaction coverage requirementsModel for performing architectural trade-offs
Early handoff vehicle to system development teamsFast executable model for early embedded software development
Source: Cadence white paper, The Unified Verification Methodology
Verification of Complex Systems (13/15)
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Functional Level to Implementation Level Prototype
Source: Cadence white paper, The Unified Verification Methodology
Verification of Complex Systems (14/15)
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Unified System Model with the highest desirable abstractionis created early in the design process by the SoC verificationteam working closely with the architectsA test suite is included with the Functional PrototypeEach subsystem has its own TLM (Transaction Level Model)defined at the SoC partitionIndividual subsystem teams proceed to develop theimplementation level of the subsystemThe test suite is run on the FVP as each subsystemimplementation is integrated into the FVP
The process of integration is facilitated by transactors, whichtranslate information between the transaction and signal levelOnce all the transaction-level models are replaced, theimplementation level prototype is complete
Verification of Complex Systems (15/15)
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Outline
Embedded SystemsHigh Performance Embedded SystemsVerification and ValidationConventional Verification of EmbeddedSystemsVerification of Complex Systems
ConclusionQuestions and Answers
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Conclusion
Embedded systems tend to contain tensof processor cores with multi-layeredbusses and bus-bridges.Hardware and software development amandatory design methodology.Existing embedded system verification
strategies do not offer enoughsophistication for today's complexsystems.
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TLM based Unified System Modelsprovide a means to carry out design andverification hand in hand whilepromoting hardware / software co-development.
Conclusion
Source: DSP Design Line54 of
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances , home automation ,
consumer electronics , ATMs , networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances, home automation
consumer electronics , ATMs , networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances, home automation,
consumer electronics , ATMs , networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances, home automation,
consumer electronics , ATMs , networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances, home automation,
consumer electronics, ATMs, networkrouters , automobiles , aircrafts , etc.
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Introduction to Embedded Systems (1/4)
An application specific electronic sub-system which is completely encapsulatedby the main system it belongs to.
The main systems can range fromhousehold appliances, home automation,
consumer electronics, ATMs, networkrouters , automobiles , aircrafts , etc.
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Conventional Verification of Embedded Systems
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RTL-based simulation as verificationmechanism
Conventional Verification of Embedded Systems(7/13)
a = 1;
#20 b = 1;
$display ( status is = %d ,c);
...
estbench UV
Source: Chong- Min Kyung, Current Status and Challenges of SoC Verification for EmbeddedSystems Market, IEEE International SOC Conference, 2003
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Hardware acceleration and emulation as verification mechanism These typically involve arrays of field-
programmable gate arrays (FPGAs) orprocessors.
Conventional Verification of Embedded Systems(5/13)
Simulation environment
estbench
Module0
Module1
Module 2
Hardware Accelerator
Module 2 issynthesized &compiled into
FPGAs
Source: Chong-Min Kyung, Current Status andChallenges of SoCVerification for EmbeddedSystems Market, IEEEInternational SOCConference, 2003
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Hardware acceleration and emulation as verification mechanism
Conventional Verification of Embedded Systems(5/13)
&
&
>
+
Logic designEmulation hardware with multiple FPGAs
Designmapping
External pins
Source: Chong-Min Kyung, Current Status andChallenges of SoCVerification for EmbeddedSystems Market, IEEEInternational SOCConference, 2003
FPGA 0 FPGA 1
FPGA 2 FPGA 3
Crossbar(Switch)
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SoC architects to employ a broad systemlevel design strategy that will allow: Explore and evaluate system level
architectural choices Concurrent hardware-software design Easily evaluate and integrate a number of
different technologies Adequate verification at every level of thedesign cycle
Verification of Complex Systems (4/15)Specification
Behavioral Model
RTL Model
Gate-Level Model
Transistor-Level Model
D E S I G N
V E RI F I C AT I ON
Meet
Specifications?
Implement Behavior?
Equivalent?
Equivalent?
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Brief Introduction
Graduated with First Class Honors in Electronic andTelecommunication Eng (1986)Won the Presidential Scholarship (Sri Lanka) and aFulbright Fellowship (USEF), and undertookgraduate studies leading to M.Sc. (MicroprocessorEng and Digital Electronics) (1989), Ph.D.(Information Systems Engineering) (1992), at U.of Manchester Inst of Sc and Tech, UK.
Employed as a faculty member (InformationEngineering) at Nanyang Technological University,Singapore (1992-1999)Served the industry in USA at senior technical and
management positions (1999 To date) 69 of
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Center for High Performance EmbeddedSystems CHiPES), NTU, Singapore
CHiPES was established by the NanyangTechnological University in April 1998 topromote research and development inembedded systems engineering usingstate-of-the-art VLSI CAD tools and
technology.
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Selected Research Projects
FPGA Based High PerformanceArchitecture for Move Generation inComputer Chess
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Selected Research Projects
Multiple Sequence Families withEfficient Hardware Architecture foruse in Spread Spectrum
Watermarking for MultimediaGame Tree Search on a MassivelyParallel SIMD Machine
Massively Parallel Implementation ofa Pattern Based Evaluation Functionfor Computer Chess
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ApplicationS ecific
Slide - 73
Technology Comparison
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ApplicationS ecific
Slide - 74
Time to Market: Design Cycle
ASIC design cycle is longer compared to FPGA becausemore time has to be spent on verification, timing closureand prototyping.
Development Costs: Process Geometry
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ApplicationS ecific
Slide - 75
Development Costs: Process Geometry
ASIC NRE cost is rapidly increasing with process improvementswhile NRE is almost non-existent in FPGAs.However, ASIC remains the preferred option only for very highvolume productions.
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ApplicationS ecific
Slide - 76
Time to Market: A Hybrid Approach
FPGAs can be used for a quick entry into the market(FPGA-to-ASIC conversion can be done later)
The convergence of the ASIC and FPGA design methodologymakes it easy to adopt an FPGA first ASIC later approach.
RTL coding should be done with future FPGA-to-ASICtransition in mind.
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ApplicationS ecific
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ApplicationS ecific
Slide - 79
TypicalASICFlow
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ApplicationS ecific
Slide - 80
Convergence of ASIC & FPGA Design Flows
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D i C l Ti
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Design Cycle Time