verilog chapter3 module+and+hierarchical+structure

8/8/2019 Verilog Chapter3 Module+and+Hierarchical+Structure

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NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

LECTURE

Lecturer: Lam Duc Khai

VERILOG

Hardware Description Language

Chapter3: Modules and

Hierarchical structure

Subject:


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Agenda

1. Chapter 1: Introduction ( Week1)

2. Chapter 2: Fundamental concepts (Week1)

3. Chapter 3: Modules and hierarchical structure (Week2)

4. Chapter 4: Primitive Gates Switches User defined

primitives (Week2)5. Chapter 5: Structural model (Week3)

6. Chapter 6: Behavioral model Combination circuit (Week4)

7. Chapter 7: Behavioral model Sequential circuit (Week5)8. Chapter 8: Tasks and Functions (Week6)

9. Chapter 9: State machines (Week6)

10. Chaper 10: Testbench and verification (Week7)


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Agenda

Hierarchical structure

Modules

Instances

3. Chapter 3: Module and Hierarchical structure


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Hierarchical structure The Verilog HDL supports a hierarchical hardware description

structure by allowing modules to be embedded within other

modules. Higher level modules create instances of lower levelmodules and communicate with them through input, output,and bidirectional ports. These module input/output (I/O) portscan be scalar or vector.


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Top-down design methodology

Top-level block

identifyenoughto build

Cannot further be divided

Hierarchical structure (Contd)


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Bottom-up design methodology

Top-level block, thefinal block in design

Building blocks that are

available is identified

build



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Design Methodologies

A combination of top-down and bottom-up flows is typicallyused

Design architects define the specifications of the top-level

block Logic designers break up the functionality into blocks and

sub-blocks.

At the same time, circuit designers are designing optimized

circuits for leaf-level cells. They build higher-level cells by

using these leaf cells.

The flow meets at an intermediate point



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Example: 4-bit Ripple Carry Counter

Ripple Carry Counter T-flipflop

Design Hierarchy



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Modules A module is the basic building block in Verilog

Can be an element or a collection of lower-level design

blocks

Provide functionality for higher-level block through its

port interface

Hide internal implementation

Is used at many places in the design

Allows designers modify module internals without

effecting the rest of design


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Typical Module Components Diagram

Module name, Port list (optional, if there are ports)

Port declarations

Parameter list

Declaration of variables (wires, reg, integer etc.)

Instantiation of inner (lower-level) modules

Structural statements (i.e., assign and gates)

Procedural blocks (i.e., always and initial blocks)

Tasks and functions

endmodule declaration

Modules (Contd)


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Module description

module module name (port name,port name,);

module_port declaration

data type declaration

logic description part

endmodule

A module definition

A part of a chip, or

whole the chip

module

The file name for RTL source must be

module name.v

Modules (Contd)


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reg or wire

Port Rules Diagram

input output

wirereg or wire wire

inoutwire

wire

EXTERNAL

MODULE

Internal ports

INTERNAL

MODULE

Outside connectors

to internal ports, i.e.,

variables corresponding

to ports in instantiation

of internal moduleExample:

module external

reg a;

wire b;

internal in(a, b);//instantiation

endmodule

module internal(x, y)

input x;

output y;

wire x;

reg y;

endmodule

port-connector

General rule (with few exceptions) Ports in all modules except for the

stimulus module should be wire. Stimulus module has registers to set datafor internal modules and wire ports only to read data from internal modules.

Modules (Contd)


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Data type declaration Declare characteristics of variables

wire variable name, variable name, ;

wire variable name, variable name, ;

module

4

8

1

116

4

4wire [3:0] a;

wire [7:0] b;wire c, d;

wire [3:0] f;

wire [7:0] q1, q2, q3, q4;

wire sel3, ;.

ab

c

dg

fe

for net data type

SEL

q2

q1

sel3

q3

Modules (Contd) Data type declaration


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Data type declaration

Define signals which are output of FF, registers, andother memory elements as register type variable.

reg variable name, variable name, ;

reg variable name, variable name, ;

wire [3:0] e;

wire [15:0] g;

wire q2;

.

for register data type

module

4

8

11

16

4

4a

b

c

dg

f

eq2

Output does not have to be declared as register data typeInput (inout) must not be declared as register data type

Note:

Modules (Contd) Data type declaration (Contd)


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Example: Mistakes and correct on register and net data type

module1 module2

reg

reg

reg

reg

wire

wire

wire

reg

wire

reg

wire wire

reg

module2_1

wire reg

reg

wire wire

The output of memory element

must be defined as reg

They must be defined as wire at

these points.

: memory element

Modules (Contd)


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module2

reg wire

regmodule2_1

wire reg reg reg

wire

module1

reg

reg

wire

reg

wire

wire

reg

wire

reg

wirewire

wire

wire

reg

wire

wire

wire

wire

reg

wire

Suppose this part is programmed byusing always statement.

Assume gates are not defined by using

always nor function statements

Modules (Contd)Example: Mistakes and correct on register and net data type (Contd)


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module2

reg wire

regmodule2_1

wire reg reg reg

wire

module1

reg

reg

wire

reg

wire

wire

reg

wire

reg

wirewire

wire

wire

reg

wire

wire

wire

wire

reg

wire

Suppose this part is programmed byusing always statement.

Note: reg data type cannot be declared as an input !!!

wire wire

reg

wire wire

wire

wirewire

reg

reg

regExplain later

Example: Mistakes and correct on register and net data type (Contd)Modules (Contd)


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Example: 4-bit Ripple Carry Counter

Ripple Carry Counter

module

T-flipflop module

Instances

Module

Instance1

T_FF

Module

Instance2

T_FF

Instance3

T_FF

Instance4

T_FF

Instance1

D_FF

Instance1

Inverter


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Instances (Contd)

Connecting module instance ports by ordered list

module topmod;

wire [4:0] v;

wire a,b,c,w;

modB b1 (v[0], v[3], w, v[4]);endmodule

module modB (wa, wb, c, d);

inout wa, wb;

input c, d;

tranif1 g1 (wa, wb, cinvert);

not #(2, 6) n1 (cinvert, int);

and #(6, 5) g2 (int, c, d);

endmodule

The port expressions listed for the module instance shall be in the same order as the

ports listed in the module declaration.


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Connecting module instance ports by name

Connections are made by name, the order in which they appear is irrelevant.

module topmod;

wire [4:0] v;

wire a,b,c,w;

modB b1 (.wb(v[3]),.wa(v[0]),.d(v[4]),.c(w));endmodule

module modB(wa, wb, c, d);

inout wa, wb;

input c, d;tranif1 g1(wa, wb, cinvert);

not #(6, 2) n1(cinvert, int);

and #(5, 6) g2(int, c, d);

endmodule

Instances (Contd)


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END

verilog chapter3 module+and+hierarchical+structure

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