verilog simulator - silvaco...• ieee-1364-2001 compliant verilog simulator with programming...
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• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions
• Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor
• Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more
• Ensures comprehensive verifi cation with integrated code coverage
• Supports compliance testing for RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,” Appendix B
• Silvaco’s strong encryption is available to protect valuable customer and third party intellectual property
Silos is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs.
Silos
Verilog Simulator
• Easy-to-usegraphicuserinterfaceprovidesproductiveenvironmentfornovicesandexperts–SilosselectedbysevenpopularVerilogtextbooksandusedinthemajorityofuniversityVLSIdesigncourses
• HierarchyExploreroffersafamiliarviewofahierarchicaldesignwith“drag&drop”forrapidcaptureanddisplayofanyvariablesinthedesign
• SilosInteractiveEnvironmentenablesreal-timeaccessandanalysisofallexpressions,variables,modules, signals, vectors, and registers
• Consistentinteractivemethodsforsignalselection,settingtime-scale,busradix,statuswindow,timingmarker,bookmark,andbusdefinition
• InteractiveSourceCodeEditordisplayslinenumbersforstop,start,andbreakpoints,DataTipstoviewthevaluesofvariablesandexpressions,andcodecoverageinformation
Ease of Use
Functionality• IEEE1364CompliantVerilogwith2001Extensionsincludingthegeneratestatement
and wildcards
• Multi-levelHDLsimulatoratswitch,gate,andbehaviorallevels
• ComprehensiveProjectManagersavespreferences,settings,directories,andoptionsinafileforefficientmulti-projectsetup
• SaveAllenablesdesignerstoviewthecompletesimulationhistory
• SaveandRestoresavesthecompletestateofthesimulatortoafilethatcanbeusedtorestartsimulationatthepointofthesave
• IEEE1364ProgrammingLanguageInterface(PLI)enablesdesignersandFPGAvendorstocreateVerilogextensionsasdynamicallylinkedlibraries
AnyVerilogexpressioncanbeviewedasawaveformbydragginganddroppingtheexpressionintotheDataAnalyzer.
Data Analyzer uses the Trace Signal Window and the Source CodeWindowtotracethecauseofanunknownvalue.
Lint Capability
Productivity – Interactive Simulation Environment
• HighPerformancesimulationengineachievesfastsimulationresultsrivalingcompiledVerilogforinteractivedebuggingofdesignsuptoseveralhundredthousandgates(withnocompiletimes)
• Interactive,interpretedVerilogenvironmentprovidesasetofmulti-taskingutilitiestoeditHDLsource,setincrementalbreakpoints,steppingortimedsimulation,real-timeviewing,anderrordetection
• Multi-windowcustomizableDataAnalyzercontrolspanandzoom,timingmarkers,usinginteractive“drag&drop”capture,anddisplayforsignalsandexpressionsforanaloganddigitalwaveforms
• TraceModegraphicallytracesallfan-inconnectionstoanysignalthroughalllevelsofcircuithierarchyinstantly
• Watcheswindowdisplaysorforcesstatevaluesofspecifiedsignalsandvariableswhilesingle-stepping–allsetupthrough“drag&drop”fordesignerconvenience
• Checksformorethan500designrules
• Checksraceconditionsandclockdomainsynchronization
• Checksforsynthesizability,andreportspotentialsynthesisandsimulationmismatches
• Optimizesgateusagewithdetailedreportsofinferredregisters,latches,state-machinesandothersequentialelementsthatwillbesynthesizedintosynchronoushardware
• ExtractsFiniteStateMachines(FSM)andanalysesforredundantorunreachablestates
• Offersdesign-for-testabilitychecksforup-frontidentificationofun-testablecircuits
• Comprehensivereportfilteringsystemdeliverspreciseinformationtoisolateandfixproblem
DataTipsintheSourceWindowdisplayvalue,scope,andtimeofthehighlightedexpressionattheT1markerintheDataAnalyzer.
Analogwaveformscanbedisplayedineitherpiecewiselinearformator stepping format.
Silos Inputs/Outputs
Silos
Verilog Source
SDF Back Annotation
Code Coverage Reports
Waveforms
Log and Trace Files
IEEE 1364 PLIProgramming
Language Interface
Command Files
Verilog Libraries Lint Report
Support for FAA Standard DO254 Testing
• RTCA/DO-254,DESIGNASSURANCEGUIDANCEFORAIRBORNEELECTRONICHARDWAREisastandardrecognizedbytheFederalAviationAdministration(FAA)asameanstoensurethesafetyofelectronicairbornesystemsbyverifyingthedesignofcomplexelectronichardwareinairbornesystems
• TheSiloscodecoveragereportingfeaturesupportscompliancetestingforRTCA/DO-254“DesignAssuranceGuidanceforAirborneElectronicHardware,”forlevelsAandBasspecifiedtomeet“ElementalAnalysis”inAppendixB
• Silosgeneratescodecoveragereportsincluding“Line/StatementCoverage,”“Operator/ExpressionCoverage”and“BranchCoverage.”ReportscanbeexportedastextfilesandcanalsobeexaminedinteractivelyusingtheSilosgraphicaluserinterface(GUI).CodeCoveragedatafrommultipleindependent simulation runs can be merged into a single report
• Theusercanenableanddisablecoveragereportingforspecificlinesandblocksofbehavioralsourcecode.Spurioustime0eventsareautomaticallyeliminatedfromthecoverageresults
HEADQUARTERS
4701 Patrick Henry Drive, Bldg. 2
Santa Clara, CA 95054 USA
Phone: 408-567-1000
Fax: 408-496-6080
JAPAN [email protected]
EUROPE [email protected]
KOREA [email protected]
TAIWAN [email protected]
SINGAPORE [email protected]
CALIFORNIA [email protected]
408-567-1000
MASSACHUSETTS [email protected]
978-323-7901
TEXAS [email protected]
512-418-2929
WWW.SILVACO.COMRev.042513_23