vga controller - altium: next generation electronics design

VGA Controller

Summary Core Reference CR0113 (v1.3) May 27, 2005

This document provides detailed reference information with respect to the VGA Controller peripheral devices.

The VGA Controller provides a simple interface to any VGA-compatible monitor. Taking a processor-generated picture (pixilated) from memory space, the Controller provides digital RGB values for each pixel, as well as horizontal and vertical synchronization signals, in order to correctly display the picture on a connected monitor.

Available devices The following two variants of the Controller are available:

VGA - Standard version of the VGA Controller, providing an 8-bit host interface

VGA32 - Wishbone-compliant version of the VGA Controller, providing a 32-bit host interface

Both devices can be found in the FPGA Peripherals integrated library (\Program Files\Altium2004\Library\Fpga\FPGA Peripherals.IntLib)

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VGA32 – 32-bit Wishbone-compliant version The VGA32 provides a simple, 32-bit interface between a host processor and any VGA-compatible monitor. This variant of the Controller has been designed for exclusive use with 32-bit processors, such as the TSK3000A and PPC405A 32-bit RISC Processors.

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Compatible with any standard VGA- or SVGA-compatible monitor

Independent Wishbone Master and Pixel clock inputs

Two resolutions supported

− 640x480 – standard VGA

− 800x600 – standard SVGA

Black & White, 8 bits per pixel mode (256 grey scale mode)

Four non-indexed color modes:

− 8 bits per pixel mode



− 1 bit per pixel mode

Indexed color mode

− 2 color look-up tables

Configurable output synchronization levels

Composite output

Horizontal and vertical interrupts.

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Functional Description

Symbol

Figure 1. VGA Controller Symbol – 32-bit Wishbone variant (VGA32)

Pin description Table 1. VGA32 Pin description

Name Type Polarity/ Bus size Description

Global Control Signals

CLK_I I Rise Global Wishbone clock input. This clock is used to drive both Master and Slave interfaces

RST_I I High Global Wishbone reset

PixelClock I Rise Video subsystem clock

PixelReset I High Video subsystem reset

Host Processor Interface Signals

WBS_STB_I I High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle

WBS_CYC_I I High Cycle signal. When asserted, indicates the start of a valid Wishbone cycle

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WBS_ACK_O O High Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated

WBS_ADR_I I 12 Address bus, used to select an internal register of the device for writing to/reading from

WBS_DAT_O O 32 Data to be sent to host processor

WBS_DAT_I I 32 Data received from host processor

WBS_SEL_I I 4/High Select input, used to determine where data is placed on the WBS_DAT_O line during a Read cycle and from where on the WBS_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24)

WBS_WE_I I Level Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle:

0 = Read

1 = Write

INT_O O 3/High Interrupt output lines. Three interrupts are sent to the connected processor on this 3-bit bus.

bit 0 = VSYNC

bit 1 = HSYNC

bit 2 = BLANK

Video Memory Interface Signals

WBM_STB_O O High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle

WBM_CYC_O O High Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers

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WBM_ACK_I I High Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated

WBM_ADR_O O 32 Standard Wishbone address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from

WBM_DAT_I I 32 Data received from the connected Wishbone slave device

WBM_SEL_O O 4/High Select output, used to determine where data is placed on the WBM_DAT_O line during a Write cycle and from where on the WBM_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24)

WBM_WE_O O Level Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read

1 = Write

Note: This signal is always Low as the Controller does not write to Video memory, it only reads data from memory.

VGA Monitor Control Signals

HSYNC O High/Low Horizontal synchronization signal. This signal is used to control the horizontal deflection circuit in the VGA monitor, so that the start and end of a line of pixels is correctly displayed across the visible display area of the screen. The polarity of this signal is controlled by the hop bit in the Control register (CTRL.8)

VSYNC O High/Low Vertical synchronization signal. This signal is used to control the vertical deflection circuit in the VGA monitor, so that the start and end of a frame (of lines) is correctly displayed between the top and bottom edges of the visible display area of the screen. The polarity of this signal is controlled by the vop bit in the Control register (CTRL.9)

CSYNC O High/Low Composite synchronization signal. The polarity of this signal is controlled by the cop bit in the Control register (CTRL.10)

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BLANK O High/Low Blank synchronization signal. The polarity of this signal is controlled by the bop bit in the Control register (CTRL.11)

R O 8 Provides the 8-bit digital signal for the intensity of red used in composing a pixel's displayed color

G O 8 Provides the 8-bit digital signal for the intensity of green used in composing a pixel's displayed color

B O 8 Provides the 8-bit digital signal for the intensity of blue used in composing a pixel's displayed color

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Hardware Description

Block Diagram

I

Data FIFO Line FIFO RGB Output Color Processor

RGB Buffer

Wishbone Interfaces & Configuration

Module CLK_I RST_I

CTRL

WBM_STB_O STATUS WBM_CYC_O

WBM_ACK_I R[7..0] WBM_ADR_O

HTIM G[7..0] WBM_DAT_I B[7..0] WBM_SEL_O

WBM_WE_O VTIM

CLUT Memory nterface

RGB Line Synchronizer

HVLEN

PixelReset WBS_STB_I VMBA PixelClock WBS_CYC_I

WBS_ACK_O WBS_ADR_I

CDIV WBS_DAT_O WBS_DAT_I

Pixel Generator – Synchronization and Control Unit WBS_SEL_I CLUTOFFWBS_WE_I

WAREG INT_O[2..0]

WDOUT

Horizontal & Vertical Timing Generator

HSYNC VSYNC CSYNC BLANK

PixelClock PixelReset

Figure 2. VGA32 block diagram

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Internal Registers The following sections detail the internal registers for the VGA32 Controller (part of the Wishbone Interfaces & Configuration Module), as well as the two color look-up tables.

Control register (CTRL) Address: 0000000000b

Access: Read/Write

Value after Reset: 0000_0000h

This 32-bit register is used to configure and control operation of the Controller.

Table 2. The CTRL register

MSB LSB

31 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- ckde bop cop vop hop cme bm1 bm0 ltb - - - vse

Table 3. CTRL register bit functions

Bit Symbol Function

CTRL.31..CTRL.13 - Not used

CTRL.12 ckde Clock Division Enable bit

CTRL.11 bop Blanking Synchronization Output Polarity bit.

0 = Blanking sync pulse is active High

1 = Blanking sync pulse is active Low

CTRL.10 cop Composite Synchronization Output Polarity bit.

0 = Composite sync pulse is active High

1 = Composite sync pulse is active Low

CTRL.9 vop Vertical Synchronization Output Polarity bit.

0 = Vertical sync pulse is active High

1 = Vertical sync pulse is active Low

CTRL.8 hop Horizontal Synchronization Output Polarity bit.

0 = Horizontal sync pulse is active High

1 = Horizontal sync pulse is active Low

CTRL.7 cme Color Mode Enable bit.

0 = Controller operating in Black & White mode

1 = Controller operating in Indexed Color mode

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CTRL.6 bm1

CTRL.5 bm0

Bitmode control bits (bm1 bm0). Determines how many bits are used to represent a single pixel:

00 = 8 bits per pixel



11 = 1 bit per pixel

CTRL.4 ltb Color Look-up Table Select bit.

0 = color look-up table 0 is active

1 = color look-up table 1 is active

CTRL.3 - Not used

CTRL.2 - Not used

CTRL.1 - Not used

CTRL.0 vse Video System Enable bit.

0 = Controller is stopped

1 = Controller is started

Status register (STATUS) Address: 0000000001b

Access: Read


This 32-bit register is used to provide status information concerning which color look-up table is currently active.

Table 4. The STATUS register

MSB LSB

31 5 4 3 2 1 0

- acp - - - -

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Table 5. STATUS register bit functions

Bit Symbol Function

STATUS.31..STATUS.5 - Not used. Returns 0 when read

STATUS.4 acp Active Color Look-up Table flag. Reflects which look-up table is currently being used:

0 = Color Look-up Table 0 in use

1 = Color Look-up Table 1 in use

STATUS.3 - Not used. Returns 0 when read




Horizontal Timing register (HTIM) Address: 0000000010b

Access: Read/Write


This 32-bit register is used to configure the horizontal timing.

Table 6. The HTIM register

MSB LSB

31 23 15 0

hsync hbporch hvisible

Table 7. HTIM register bit functions

Bit Symbol Function

HTIM.31..HTIM.24 hsync Horizontal Synchronization Pulse length (in pixels – 1)

HTIM.23..HTIM.16 hbporch Horizontal Back Porch length (in pixels – 1)

HTIM.15..HTIM.0 hvisible Horizontal Visible Area (in pixels – 1)

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Vertical Timing register (VTIM) Address: 0000000011b

Access: Read/Write


This 32-bit register is used to configure the vertical timing.

Table 8. The VTIM register

MSB LSB

31 23 15 0

vsync vbporch vvisible

Table 9. VTIM register bit functions

Bit Symbol Function

VTIM.31..VTIM.24 vsync Vertical Synchronization Pulse length (in lines – 1)

VTIM.23..VTIM.16 vbporch Vertical Back Porch length (in lines – 1)

VTIM.15..VTIM.0 vvisible Vertical Visible Area (in lines – 1)

Horizontal and Vertical Length register (HVLEN) Address: 0000000100b

Access: Read/Write


This 32-bit register is used to store horizontal and vertical length values that together determine the actual extents of the image display area on the screen.

Table 10. The HVLEN register

MSB LSB

31 15 0

hlen vlen

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Table 11. HVLEN register bit functions

Bit Symbol Function

HVLEN.31..HVLEN.16 hlen This value determines the number of viewable pixels to be displayed in each line of a frame and is therefore used to control the horizontal extents of the visible display area

HVLEN.15..HVLEN.0 vlen This value determines the number of lines to be displayed in a frame and is therefore used to control the vertical extents of the visible display area

Video Memory Base Address register (VMBA) Address: 0000000101b

Access: Read/Write


This 30-bit register is used to store the address in memory at which the video page starts. The width of the memory used to store the graphics to be displayed is actually 32 bits. When addressing locations in this memory, the 30-bit video base address value is sent on the WBM_ADR_O line as bits 31..2, with bits 1..0 always zeros.

System Clock Division register (CDIV) Address: 0000000110b

Access: Read/Write

Value after Reset: 00h

This 8-bit register is used to store a divisor reload value, allowing you to effectively control the frequency of the clock used to drive the timing generation unit (and horizontal and vertical timing sub-units therein).

If you wish to divide CLK_I by 2, load 01h into CDIV. If you wish to divide by 3, load 02h into CDIV, and so on.

If no internal clock division is required, either load 00h into CDIV, or expressly prohibit clock division by clearing the ckde bit in the Control register (CTRL.12).

Color Look-up Table Offset register (CLUTOFF) Address: 0000000111b

Access: Read/Write

Value after Reset: 00h

This 8-bit register is used to store an offset value used to determine the 8-bit address of a color contained within the active color look-up table. The use of this offset value depends on the bitmode setting in the Control register, as determined by the bm1 and bm0 bits (CTRL.6 and CTRL.5 respectively). The following table summarizes how the effective CLUT address is determined for each of the four possible pixel modes:

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Table 12. Use of CLUTOFF register for CLUT addressing

bm1 (CTRL.6)

bm0 (CTRL.5)

Mode Use of value in CLUTOFF register

0 0 8 bits per pixel not used

0 1 4 bits per pixel bits 7..4 are used as the upper bits of the 8-bit CLUT address, with bits 3..0 taken from the Video Memory

1 0 2 bits per pixel bits 7..2 are used as the upper bits of the 8-bit CLUT address, with bits 1..0 taken from the Video Memory

1 1 1 bit per pixel bits 7..1 are used as the upper bits of the 8-bit CLUT address, with bit 0 taken from the Video Memory

Color Look-up Tables (CLUT0 and CLUT1) Two color look-up tables are available, each of which contain 256 addresses. The two tables form a single contiguous 512 x 32-bit address space:

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CLUT0 – with address range 100h to 17Fh

CLUT1 – with address range 180h to 1FFh

The color look-up tables can be accessed directly through the Controller’s Wishbone Slave interface. Direct access is controlled using bit 11 of the WBS_ADR_I line. When this bit is High, Wishbone communications are configured to be direct with the active color look-up table.

Each 32-bit data entry in the table is comprised as follows:

bits 31..24 – unused

bits 23..16 – Red

bits 15..8 – Green

bits 7..0 – Blue

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Placing a VGA32 Controller in a Design Figure 3 shows an example of how a VGA32 Controller can be wired into a design that uses a TSK3000A processor. A configurable Wishbone Interconnect device (WB_INTERCON) is used to simplify connection and also handle addressing – taking the 24-bit address line from the processor and mapping it to the 12-bit address line used to drive the Controller.

Figure 3. Example interfacing between a 32-bit processor (TSK3000A) and a VGA32 Controller

For further information on the Wishbone Interconnect peripheral, refer to the WB_INTERCON Configurable Wishbone Interconnect core reference in the FPGA Core Reference book.

For further information on the TSK3000A processor, refer to the TSK3000A 32-bit RISC Processor core reference in the TSK3000 Reference Manual.

Color Output using the NanoBoard The R, G and B outputs from the Controller are 8 bits in length, supporting 8-bits per pixel (B&W or color). Together, these outputs form the 24-bit RGB value (True Color) required for driving the red, green and blue color guns of the target monitor.

On a custom/production board, you can take full advantage of this support and the subsequent full range of colors that can be achieved. When using the NanoBoard, on-board 2-bit digital to analog converter circuitry ( ) provides a limitation to the number of colors that can be used/achieved. Figure 9

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Figure 4. Digital to Analog RGB conversion

The 8-bit R, G and B outputs must, in the case of using the NanoBoard, be reduced to 2-bit signals through the use of relevant bus joiners, as illustrated in Figure 5. The least significant 2 bits are used in each case.

Figure 5. Color output bit reduction

For each color, the 2-bit digital signal can be converted into 4 distinct analog levels. These levels specify the intensity of each of the three primary colors to use when displaying the pixel on the monitor’s screen. The levels range from 0V (total darkness) to 0.7V (maximum brightness).

With each analog input being one of four possible levels, the monitor can display each pixel on the screen with one of 64 different color permutations.

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Host to Controller Communications Communications between the 32-bit host processor and the VGA32 Controller are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved between host and Controller for writing to/reading from either the internal registers or the active color look-up table.

Writing to an Internal Register Data is written from the host processor to an internal register in the VGA32 Controller, in accordance with the standard Wishbone data transfer handshaking protocol.

Bit 11 of the WBS_ADR_I line is used to control direct access between either an internal register or the active color look-up table. This bit must be ‘0’ in order to address and write to, an internal register.

The actual 24-bit address sent out from the processor on its IO_ADR_O line is constructed as follows:

VGA32 Base Address + (Internal Register Address & “00”)

The base address for the VGA32 Controller is specified as part of the peripheral’s definition when adding it as a slave to the Wishbone Interconnect. For example, if the base address entered for the device is 100000h (mapping it to address FF10_0000h in the processor’s address space), and you want to write to the Horizontal Timing Register (HTIM) with address 0000000010b, the value entered on the processor’s IO_ADR_O line would be:

100000h + 008h = 100008h

The following sections detail the write operation which, in each case, occurs on the rising edge of the CLK_I input.

All Writable Registers (except CTRL) When writing to an internal register, bits 11..2 of the WBS_ADR_I line are used to address the register. The write operation can be summarized as follows:

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The host presents the required 24-bit address based on the register to be written on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle

The VGA32 receives the 12-bit address on its WBS_ADR_I input and, identifying the addressed register using bits 11..2, prepares to receive data into that register

The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by latching the data appearing at its WBS_DAT_I input into the target register and asserting its WBS_ACK_O signal – to indicate to the host that the data has been received

The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated.

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Writing to the CTRL Register The procedure for writing to the VGA32’s Control register (CTRL) is similar to that detailed in the previous section. There are basically two main differences that apply when the VGA32 receives the 12-bit address on its WBS_ADR_I line:

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The address for the register is stored in the 10-bit non-accessible Wishbone Address Register (WAREG), which is loaded as follows:

WAREG <= "0000" & WBS_ADR_I(7 downto 2)

The value loaded into this register is then interrogated to determine if the internal register being addressed is indeed the CTRL register

An internal flag signal is interrogated, to ascertain whether or not the Controller’s Wishbone Master interface is currently in use – i.e. Video Memory is currently being accessed. If the Wishbone Master interface is NOT in use, then data from the host processor is latched into the Control register.

Remember that some of the internal registers are not 32-bit. The actual value stored in a register depends on the specific internal register being addressed/written. Table 13 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.

Table 13. Values loaded into internal registers during a write

Internal Register Value loaded into register

CTRL Entire 32-bit value arriving on WBS_DAT_I

HTIM Entire 32-bit value arriving on WBS_DAT_I

VTIM Entire 32-bit value arriving on WBS_DAT_I

HVLEN Entire 32-bit value arriving on WBS_DAT_I

VMBA WBS_DAT_I(31..2)

CDIV WBS_DAT_I(7..0)

CLUTOFF WBS_DAT_I(7..0)

Reading from an Internal Register Data is read from one of the VGA32’s internal registers in accordance with the standard Wishbone data transfer handshaking protocol.

Bit 11 of the WBS_ADR_I line is used to control direct access between either an internal register or the active color look-up table. This bit must be ‘0’ in order to address and read from, an internal register.

The 10-bit Wishbone Address Register is again used to store the address of the register to be read (“0000” & WBS_ADR_I(7..2)). The actual data to be sent to the host processor is stored in an additional non-accessible internal register – the 32-bit Wishbone Data Output register (WDOUT).

The read operation occurs on the rising edge of the CLK_I input and can be summarized as follows:

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The host presents the required 24-bit address based on the register to be read on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle

The VGA32 receives the 12-bit address on its WBS_ADR_I input and loads the WAREG register accordingly

Having identified the addressed register, the Controller uses that register’s contents to load the WDOUT register

The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by presenting the valid data stored in the WDOUT register on its WBS_DAT_O output and asserting its WBS_ACK_O signal – to indicate to the host that valid data is present

The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated.

The actual value stored in the WDOUT register and subsequently sent to the host processor depends on the specific internal register being addressed/read. Table 14 summarizes the ‘make-up’ of the 32-bit data word that is read back from each register.

Table 14. Values read from internal registers during a read

Internal Register Value loaded into WDOUT register (and presented to host processor)

CTRL 32-bit value currently in the CTRL register

STATUS “000000000000000000000000000” & STATUS.4 & “0000”

HTIM 32-bit value currently in the HTIM register

VTIM 32-bit value currently in the VTIM register

HVLEN 32-bit value currently in the HVLEN register

VMBA 30-bit value in the VMBA register & “00”

CDIV “000000000000000000000000” & 8-bit value currently in the CDIV register

CLUTOFF “000000000000000000000000” & 8-bit value currently in the CLUTOFF register

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Writing to the Active Color Look-up Table Data is written from the host processor to a location in the VGA32 Controller’s active color look-up table, in accordance with the standard Wishbone data transfer handshaking protocol.

Bit 11 of the WBS_ADR_I line is used to control direct access between either an internal register or the active color look-up table. This bit must be ‘1’ in order to address and write to, the active color look-up table.

When writing to the active color look-up table, bits 10..2 of the WBS_ADR_I line are used to address the required entry in the table. The two look-up tables are actually part of the same contiguous address space. This 9-bit address provides access to each of the 512 32-bit entries in this address space.

The actual 256 addresses available at any one time depend on the state of the ltb bit in the Control register (CTRL.4). When ‘0’, the lower 256 addresses are addressable (CLUT0), when ‘1’, the upper 256 addresses are addressable (CLUT 1).

The actual 24-bit address sent out from the processor on its IO_ADR_O line is constructed as follows:

VGA32 Base Address + (“1” & CLUT Address & “00”)

For example, if the base address entered for the device is 100000h (mapping it to address FF10_0000h in the processor’s address space), and you want to write to address 17Fh in CLUT0 (let’s assume this is currently the active look-up table), the value entered on the processor’s IO_ADR_O line would be:

100000h + DFCh = 100DFCh

The write operation can be summarized as follows:

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The host presents the required 24-bit address, based on the address in the look-up table to be written, on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle

The VGA32 receives the 12-bit address on its WBS_ADR_I input and, identifying the addressed location in the active look-up table using bits 10..2, prepares to receive data into that location

The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by latching the lower 24 bits of data appearing at its WBS_DAT_I input into the target location and asserting its WBS_ACK_O signal – to indicate to the host that the data has been received

The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated.

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Reading from the Active Color Look-up Table Data is read from a location in the VGA32’s active color look-up table in accordance with the standard Wishbone data transfer handshaking protocol.

Bit 11 of the WBS_ADR_I line is used to control direct access between either an internal register or the active color look-up table. This bit must be ‘1’ in order to address and read from, the active color look-up table.

The read operation occurs on the rising edge of the CLK_I input and can be summarized as follows:

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The host presents the required 24-bit address, based on the address in the look-up table to be read, on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle

The VGA32 receives the 12-bit address on its WBS_ADR_I input and, identifying the addressed location in the active look-up table using bits 10..2, prepares to transmit data from that location

The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32, which monitors its WBS_STB_I and WBS_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by presenting a valid data word (“00000000” & CLUT Data at addressed location) on its WBS_DAT_O output and asserting its WBS_ACK_O signal – to indicate to the host that valid data is present

The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 negates the WBS_ACK_O signal and the data transfer cycle is naturally terminated.

Timing Information The following tables provide information for setting the Controller’s internal timing registers (HTIM and VTIM), based on a variety of different monitor resolutions and refresh rates.

Table 15. Horizontal timing information

Resolution Refresh Rate (Hz)

Pixel Clock (MHz)

Number of pixels per line

Sync pulse length (pixels)

Horizontal back porch

(pixels)

Number of visible

pixels

640x480 60 25.175 800 96 51 640

640x480 72 31.5 832 40 131 640

720x400 70 28.322 900 108 57 720

720x350 70 28.322 900 108 57 720

800x600 56 36 1024 72 131 800

800x600 60 40 1056 128 91 800

800x600 72 50 1040 120 67 800

640x480 75 31.5 800 96 51 640

640x480 66 30.24 864 64 99 640

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Table 16. Vertical timing information

Resolution Refresh Rate (Hz)

Number of lines per

frame

Sync pulse length (lines)

Vertical back porch

(lines)

Number of visible lines

640x480 60 525 2 34 480

640x480 72 520 3 30 480

720x400 70 449 2 36 400

720x350 70 449 2 61 350

800x600 56 625 1 24 600

800x600 60 628 4 25 600

800x600 72 666 6 25 600

640x480 75 525 2 34 480

640x480 66 525 3 41 480

Device Driver Code Various C-header files are available with respect to the VGA32 Controller, providing definitions and built-in functions that enable you to write source code for working with the Controller quickly and efficiently – a one-stop shop of predefined code building blocks if you like. The following files are available from the \Examples\FPGA Processors 32-bit\Device Driver Code folder of the installation:

io_wb_vga.h (and corresponding .C file) – providing various text-based routines •

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wb_vga.h (and corresponding .C file) – providing various drawing and display functions

wb_vga_defs.h – providing definitions for various horizontal and vertical timing modes.

For an example of the use of these device driver code files, refer to the following example project, found in the \Examples\FPGA Processors 32-bit\TSK3000 vga folder of the installation: TSK3000_VGA.PrjFpg

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VGA Controller

VGA – 8-bit non-Wishbone version The standard VGA Controller provides a simple, 8-bit interface, between a host microcontroller and any VGA-compatible monitor. This variant of the Controller provides six modes of display, depending on the resolution chosen (640x480 (VGA) or 800x600 (SVGA)) and the color palette (either Black & White, 16 Colors, or 64 Colors).

Features •

•

•

•

Compatible with any standard VGA- or SVGA-compatible monitor

Two resolutions supported

− 640x480 – standard VGA

− 800x600 – standard SVGA

Black & White, 16 Color and 64 Color display modes

Processor-controlled horizontal and vertical display sizing.

Functional Description

Symbol

Figure 6. VGA Controller Symbol – 8-bit non-Wishbone variant (VGA)

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VGA Controller

Pin description Table 17. VGA Pin description


Global Control Signals

CLK I Rising Global system clock. This clock determines the maximum rate at which pixels can be sent to the monitor. The frequency of the clock signal determines the refresh rate as follows:

640x480

CLK = 25MHz, Refresh = 60Hz


800x600


CLK = 50MHz, Refresh = 72Hz.

RST I High Global system reset

VGA Input Settings Signals

RESOLUTION I High / Low This input selects the screen resolution to be used.

1 = 640x400 (VGA)

0 = 800x600 (SVGA).

CMOD I 2 This input selects the color palette to be used:

00 = Black & White

01 = 16 Colors

10 = 64 Colors.

DISPSIZE_H I 10 This input determines the number of viewable pixels to be displayed in each line of a frame and is therefore used to control the horizontal extents of the visible display area.

DISPSIZE_V I 10 This input determines the number of lines to be displayed in a frame and is therefore used to control the vertical extents of the visible display area.

Data Memory Control Signals

RD O High This is the enable signal when data is required to be read from the memory space. This signal is controlled by, and follows, the internal line enable signal, en, generated by the Synchronization Unit of the Controller.

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VGA Controller


DATA I 8 Data input from picture memory space. Data is stored in memory in bytes, the content of which depends on the chosen color palette as follows:

Black & White mode : 8, 1-bit pixels

16 Colors mode : 2, 4-bit pixels

64 Colors mode : 1, 6-bit pixel (DATA[5..0])

Note : In 64 Colors mode, bits 7 and 6 of each byte are not used.

ADDR_PIXEL O 19 Specifies the address of the next pixel in picture memory. Addresses are consecutive – once the end of the current line has been reached, the next address is that of the pixel at the start of the next line down in the frame.

VGA Monitor Control Signals

HSYNC O Falling Horizontal synchronization signal. This signal is used to control the horizontal deflection circuit in the VGA monitor, so that the start and end of a line of pixels is correctly displayed across the visible display area of the screen. The horizontal size of the display area is controlled by the DISPSIZE_H input to the Controller.

VSYNC O Falling Vertical synchronization signal. This signal is used to control the vertical deflection circuit in the VGA monitor, so that the start and end of a frame (of lines) is correctly displayed between the top and bottom edges of the visible display area of the screen. The vertical size of the display area is controlled by the DISPSIZE_V input to the Controller.

R1

R0

O High / Low Provides the 2-bit digital signal for the intensity of red used in composing a pixel's displayed color. These two signals are inputs to a simple 2-bit DAC (external to the Controller) that provides the analog signal required by the VGA monitor.

G1

G0

O High / Low Provides the 2-bit digital signal for the intensity of green used in composing a pixel's displayed color. These two signals are inputs to a simple 2-bit DAC (external to the Controller) that provides the analog signal required by the VGA monitor.

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VGA Controller


B1

B0

O High / Low Provides the 2-bit digital signal for the intensity of blue used in composing a pixel's displayed color. These two signals are inputs to a simple 2-bit DAC (external to the Controller) that provides the analog signal required by the VGA monitor.

Hardware Description

Block Diagram

Synchronization Unit RESOLUTION

HSYNC DISPSIZE_H[9..0]HCOUNT

VSYNC DISPSIZE_V[9..0] MEMADDR CLK VCOUNT RST

en enex hvcnt[18..0]

R1 Pixel Unit R0

G1 CMOD[1..0] RGBREGG0

DATA[7..0] PIXREGB1 RDB0 ADDR_PIXEL[18..0]

Figure 7. VGA Controller block diagram

VGA Synchronization Unit The Synchronization Unit provides the horizontal and vertical synchronization signals – HSYNC and VSYNC – that are required to correctly display a picture frame within the confines of a monitor’s display area.

These synchronization signals are used as control inputs by the monitor’s horizontal and vertical deflection circuits. These circuits deflect the electrons emitted by the three primary color electron guns (Red, Green, Blue) left to right and from top to bottom, respectively. HSYNC provides the start and stop times for the horizontal deflection circuit, so that a line of pixels is correctly drawn across the screen display. VSYNC provides the start and stop times for the vertical deflection circuit, so that the lines of a frame are correctly drawn from the top to the bottom of the screen display. The resolution for the display is defined by the level on the RESOLUTION input. If High, the 640x480 resolution is used (VGA). If Low, the 800x600 resolution (SVGA) is used.

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VGA Controller

Although the resolution determines the area of a monitor’s screen within which an image can be displayed, the full extents of the chosen resolution do not have to be used. The actual extents of the image display area on the screen can be controlled by the use of the DISPSIZE_H and DISPSIZE_V inputs. These inputs determine the total number of pixels to be used in a line and the total number of lines in a frame, respectively.

Horizontal (Line) Period The Horizontal Line Period – the length of time (expressed in cycles of the CLK signal) between starting to send one complete line of pixels and the next – is defined as:

TLSync + PixTotal + BlankingLeft + BlankingRight

TLSync - the synchronization time for a line. For 640x480 resolution, this value is 95 clock cycles. For 800x600 resolution, this value is 120 clock cycles.

PixTotal - the integer value of the DISPSIZE_H input. This is the total viewable pixels that will be sent per line to the monitor.

BlankingLeft - the number of blank pixels that are inserted to the left of the viewable pixel area of the screen display. The number of blank pixels depends on the resolution used:

640x480 : No. of blank pixels = 23 + ((640 – PixTotal) / 2)


BlankingRight - the number of blank pixels that are inserted to the right of the viewable pixel area of the screen display. The number of blank pixels depends on the resolution used:



Note: As a pixel is sent on each rising edge of CLK, the values for PixTotal, BlankingLeft and BlankingRight equate to the total number of clock cycles involved for each.

To express the line period in units of time, the result of the above equation must be multiplied by 1/frequency of CLK.

Horizontal Counter (HCOUNT) The horizontal counter (or pixel counter) stores the current horizontal position within a line of pixels. The counter is reset to zero when the VGA Controller receives an external reset signal (RST). The size of the counter depends on the value chosen for DISPSIZE_H, as the range is simply:

0 to Horizontal Line Period - 1

Substituting the relevant values into the expression for the Horizontal Line Period and taking the maximum number of pixels in a line for each of the supported display resolutions, the maximum ranges for the counter are:

•

•

640x480: 0 to 804

800x600: 0 to 1038.

The counter has 10-bit resolution.

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VGA Controller

While the value in the counter is less than the Horizontal Line Period, the counter is incremented on the rising edge of the external clock signal (CLK). The counter is cyclic in its operation; on reaching the upper limit of its range, it is rolled over to zero again on the rising edge of the next clock cycle.

The value in the horizontal counter is tested to determine whether or not the address counter (MEMADDR) is incremented. It is also used to determine the activation of the HSYNC signal.

Generation of the horizontal synchronization signal – HSYNC The HSYNC signal is High (inactive) after an external reset signal (RST) is received by the VGA Controller. The signal is updated on each rising edge of the external clock signal (CLK).

The state of the HSYNC signal depends on the value stored in the horizontal counter and is driven low when:

HCOUNT ≥ (PixTotal + BlankingLeft)

and remains low while:

HCOUNT < (PixTotal + BlankingLeft + TLSync)

Vertical (Frame) Period The Vertical Frame Period – the length of time (expressed in cycles of the HSYNC signal) between starting to send one complete frame and the next – is defined as:

TFSync + LinTotal + BlankingLeft + BlankingRight

TFSync - the synchronization time for a frame. For 640x480 resolution, this value is 2 HSYNC cycles. For 800x600 resolution, this value is 6 HSYNC cycles.

LinTotal - the integer value of the DISPSIZE_V input. This is the total number of viewable lines that will be sent per frame to the monitor.

BlankingLeft - the number of blank lines that are inserted above the viewable pixel area of the screen display. The number of blank lines depends on the resolution used:

640x480 : No. of blank lines = 14 + ((480 – LinTotal) / 2)


BlankingRight - the number of blank lines that are inserted below the viewable pixel area of the screen display. The number of blank lines depends on the resolution used:



Note: As a line is sent on each rising edge of HSYNC, the values for LinTotal, BlankingLeft and BlankingRight equate to the total number of HSYNC cycles involved for each.

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VGA Controller

Vertical Counter (VCOUNT) The vertical counter (or line counter) stores the current vertical position within a frame of lines. The counter is reset to zero when the VGA Controller receives an external reset signal (RST). The size of the counter depends on the value chosen for DISPSIZE_V, as the range is simply:

0 to Vertical Frame Period - 1

Substituting the relevant values into the expression for the Vertical Frame Period and taking the maximum number of lines in a frame for each of the supported display resolutions, the maximum ranges for the counter are:

•

•

•

•

640x480: 0 to 527

800x600: 0 to 665.


While the value in the counter is less than the Vertical Frame Period, the counter is incremented on the rising edge of the horizontal synchronization signal (HSYNC). The counter is cyclic in its operation; on reaching the upper limit of its range, it is rolled over to zero again on the next rising edge of HSYNC.

The value in the vertical counter is tested to determine whether the address counter (MEMADDR) is rolled over to zero or not. It is also used to determine the activation of the VSYNC signal.

Generation of the vertical synchronization signal - VSYNC The VSYNC signal is High (inactive) after an external reset signal (RST) is received by the VGA Controller. The signal is updated after every line of pixels is completed (i.e. on each rising edge of the HSYNC signal).

The state of the VSYNC signal depends on the value stored in the vertical counter and is driven low when:

VCOUNT ≥ (LinTotal + BlankingLeft)

and remains low while:

VCOUNT < (LinTotal + BlankingLeft + TFSync)

Address Counter (MEMADDR) The address counter is used to store the position of the next consecutive pixel in the frame. Its value is passed to the Pixel Unit on the internal bus signal hvcnt, which is then used to provide the ADDR_PIXEL signal, to obtain the next pixel from picture memory.

The counter is reset to zero when the VGA Controller receives an external reset signal (RST). The size of the counter depends on the values chosen for DISPSIZE_H and DISPSIZE_V, as the range is simply:

0 to (PixTotal x LinTotal) - 1

Taking the maximum number of pixels in a line and lines in a frame, for each of the supported display resolutions, the maximum ranges for the counter are:

640x480: 0 to 307199

800x600: 0 to 479999.


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VGA Controller

While the value in the horizontal counter (HCOUNT) is less than the total number of viewable pixels in a line (PixTotal, the integer value of DISPSIZE_H), the counter is incremented on the rising edge of the external clock signal (CLK). Pixel addressing within the frame is consecutive. When the counter reaches the last pixel in a line, its incremented value is the first pixel in the next line down.

The address counter will continue to be incremented until the value in the vertical counter (VCOUNT) is greater than or equal to the total number of viewable lines in a frame (LinTotal, the integer value of DISPSIZE_V). At this point, it will be rolled over to zero.

Blank pixel generation The total number of viewable pixels in a line and viewable lines in a frame is determined by the display resolution chosen through the RESOLUTION input (1= 640x480; 0 = 800x600) and the values received on the DISPSIZE_H and DISPSIZE_V buses. Whether the full extent of the chosen display resolution is used or not, the areas of the monitor screen to the top, bottom, left and right of the viewable frame area are blanked, by putting black pixels at the required line-pixel positions. This has the effect of centering the image on the screen.

The color generated for a pixel in the Pixel Unit depends on whether the particular pixel requires to be blanked or not. The Synchronization Unit provides a signal to the Pixel Unit for this very reason. This is the line display enable signal - en. The signal is checked on each rising edge of the external clock signal (CLK) and is set as follows:

If (HCOUNT ≥ PixTotal) or (VCOUNT ≥ LinTotal) then en = 0 (pixel requires to be blanked – set color to be black)

Else en = 1 (pixel is a viewable pixel – generate RGB color accordingly).

VGA Signal Timing Figure 8 summarizes the signal timing involved in sending a line of pixels and a frame of lines. The actual time values differ according to the resolution selected (640x480 or 800x600), the processor-defined values for DISPSIZE_H and DISPSIZE_V and the frequency of the external clock signal (CLK).

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VGA Controller

Line

Horizontal Blanking Interval

Horizontal Blanking Interval

HSYNC

PixTotal

BlankingLeft

TLSync

BlankingRight Horizontal Line Period

Frame

Vertical Blanking Interval

Vertical Blanking Interval

VSYNC

LinTotal

BlankingLeft

TFSync

VerticalFrame Period BlankingRight

Figure 8. Horizontal (line) and vertical (frame) timing signals

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VGA Controller

VGA Pixel Unit The Pixel Unit provides access to the pixilated image stored in external picture memory, reading in data a byte at a time and formatting each pixel to be displayed. For each pixel, the 6-bit RGB value required for the control of the monitor’s three, primary color electron guns is generated, so that the pixel is displayed on the screen with the correct color.

Accessing the stored image The image to be displayed on the monitor screen is written, by the host microcontroller, into external memory space (RAM). This memory space can be located anywhere (e.g. using a block of RAM within the FPGA design, or using the SRAM on the NanoBoard itself).

Pixel data is stored in the memory space in bytes. The number of pixels in a byte depends on which color palette is being used for the image (selected by the CMOD input):

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•

•

in Black & White mode – one byte of data in RAM contains 8, 1-bit pixels

in 16 Colors mode – one byte of data in RAM contains 2, 4-bit pixels

in 64 Colors mode – one byte of data in RAM contains 1, 6-bit pixel (DATA[7..6] are not used)

The size of memory required to store a picture is determined by the total number of viewable pixels in a line (determined by DISPSIZE_H), the total number of viewable lines in a frame (determined by DISPSIZE_V) and the number of pixels stored in each byte in memory space:

Memory required for picture = (PixTotal x LinTotal) / number of pixels per byte

The address in RAM where the next pixel is stored is determined using an internal signal provided by the Synchronization Unit – hvcnt – which reflects the current contents of the MEMADDR register. The exact addressing is described below.

Black & White mode The picture memory address – the byte of data containing the next 8 pixels – is determined by using bits 18..3 of hvcnt and right shifting the contents by three:

ADDR_PIXEL = "00" & hvcnt[18..3]

16 Colors mode The picture memory address – the byte of data containing the next 2 pixels – is determined by using bits 18..1 of hvcnt and right shifting the contents by one:

ADDR_PIXEL = '0' & hvcnt[18..1]

64 Colors mode The picture memory address – the byte of data containing the next pixel – is determined by using the full value of hvcnt:

ADDR_PIXEL = hvcnt[18..0]

The Pixel register (PIXREG) The Pixel register is used to receive the byte of pixel data read from the current address in memory space. The register, PIXREG, is reset to zero when the VGA Controller receives an external reset signal (RST).

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VGA Controller

The register is updated on each rising edge of the CLK signal. Data can be read from the memory space as long as the RD signal is active (High). The RD signal is itself controlled by the external line display enable signal, enex. This internally generated signal is defined as follows:

If ((HCOUNT > (PixTotal+1)) and (HCOUNT < Line Period)) or ((VCOUNT > (LinTotal+1)) and (VCOUNT < Frame Period)) then

enex = 0

Else

enex = 1

When enex is Low, read access from memory is disabled (RD = 0).

The point at which data is loaded from memory into PIXREG depends on the particular color palette that is chosen – Black & White, 16 Colors, or 64 Colors.

Black & White mode The next byte of data will be loaded into the register whenever the lowest three bits of the hvcnt signal – received from the Synchronization Unit - are “000”.

For the currently loaded byte, the active pixel is always in the lowest bit position of the Pixel register. Each pixel in the data byte is moved into this active pixel position by shifting the contents of the register right by one bit, on each rising edge of CLK.

16 Colors mode The next byte of data will be loaded into the register whenever the lowest bit of the hvcnt signal – received from the Synchronization Unit - is a '0'.

For the currently loaded byte, the active pixel is always in the low order nibble of the Pixel register. Remember that in this mode, each byte of data contains two pixels. The second pixel is moved into this active pixel position by shifting the contents of the register right by four bits, on the rising edge of CLK.

64 Colors mode The next byte of data will be loaded into the register on the rising edge of the external system clock signal (CLK). In this mode, the read of pixel data does not depend on the status of the hvcnt signal received from the Synchronization Unit.

The RGB register (RGBREG) The RGB register is used to store the six bits that are required for driving the red, green and blue color guns of the target monitor. When the chosen color palette is either Black & White or 16 Colors, these six bits are obtained by mapping the value of the active pixel to a predefined RGB code. When the chosen color palette is 64 Colors, the actual pixel value is used directly.

The register, RGBREG, is reset to zero (000000) when the VGA Controller receives an external reset signal (RST). This RGB code represents black.

The register is updated on each rising edge of the CLK signal and the value loaded is dependent on the state of the line display enable signal, en. When en is Low, blanking is required and RGBREG is loaded with the code for black (000000).

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VGA Controller

Table 18

Table 18. Mapping of pixel data to RGB color

illustrates the mapping of a 1-bit pixel (Black & White mode) and a 4-bit pixel (16 Colors mode) into the required RGB color code.

Color Palette Mode

State of line display enable

signal (en)

Active pixel value RGB Color Code (loaded into RGBREG)

B & W 1 0 000000 Black

1 111111 White

0 0 000000 Black

1 000000 Black

16 Colors 1 0000 000000 Black

0001 100000

0010 001000

0011 101000

0100 000010

0101 100010

0110 001010

0111 010101

1000 101010

1001 110000 Red

1010 001100 Green

1011 111100 Yellow

1100 000011 Blue

1101 110011 Magenta

1110 001111 Cyan

1111 111111 White

0 0000 000000 Black

0001 000000 Black

0010 000000 Black

0011 000000 Black

0100 000000 Black

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VGA Controller

Color Palette Mode

State of line display enable

signal (en)

Active pixel value RGB Color Code (loaded into RGBREG)

0101 000000 Black

0110 000000 Black

0111 000000 Black

1000 000000 Black

1001 000000 Black

1010 000000 Black

1011 000000 Black

1100 000000 Black

1101 000000 Black

1110 000000 Black

1111 000000 Black

The RGB color code stored in the RGB register is output from the VGA Controller as separate 2-bit R, G and B values (outputs R0, R1, G0, G1, B0 and B1).

The monitor itself expects analog signals as inputs to its electron gun control circuits. This is achieved by using 2-bit digital to analog converter circuitry, located on the NanoBoard itself, as shown in . Figure 9

Figure 9. Digital to Analog RGB conversion

For each color, the 2-bit digital signal from the VGA Controller can be converted into 4 distinct analog levels. These levels specify the intensity of each of the three primary colors to use when displaying the pixel on the monitor’s screen. The levels range from 0V (total darkness) to 0.7V (maximum brightness).

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VGA Controller

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With each analog input being one of four possible levels, the monitor can display each pixel on the screen with one of 64 different color permutations.

Revision History

Date Version No. Revision

30-Dec-2003 1.0 New product release

01-Dec-2004 1.1 Schematic symbol update

04-Mar-2005 1.2 Addition of 32-bit Wishbone variant of the Controller – VGA32.

27-May-2005 1.3 Updated for Altium Designer SP4

Software, hardware, documentation and related materials:

Copyright © 2005 Altium Limited.

All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, CAMtastic, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, CircuitStudio, P-CAD, Protel, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed.

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