VHDL

Prepared by:Gaurav

Outline…..

Brief Overview of VHDL Structural elements of VHDL

Entity Architecture Signals

Data Types & Operator VHDL Design Methodology

Behavioral Structural Dataflow

Brief Overview of VHDL

• VHDL... stands for Very High Speed Integrated Circuit

Hardware Description Language

can be translated into an actual hardware implementation

allows complex digital circuits to be easily created In VHDL, strong understanding of your code is more

important than syntax & style.

Structural Elements

• Entity• Interface

• Example: Ports, I/O

• Architecture• Implementation• Behavior•Function

Vhdl model

ENTITY

provides a name to the component contains the port definitions in the interface

list can contain some generic definitions which

can be used to override default valuesentity identifier is generic interface_list; port interface_list; declarationsbegin statementsend [entity] [identifier];

Example

And

a

bc

1. entity and is port (a, b: in bit; c : out bit);

end and;

2. ENTITY and IS PORT( a, b : IN std_logic; c: OUT

std_logic );END and;

2 input And gate

Architecture

encapsulates the behavior and timing information contains a number of concurrent statements there can be multiple architecture bodies for a given entity

architecture identifier of entity_name is declarations

begin statementsend [architecture] [identifier];

Example

And

a

bc

architecture and_arch of and is;begin;c<= a and b;end and_arch;

2 input And gate

Signals Signals are intermediary ‘ports’ within the architecture represents wires and storage elements

Xor

And

And

Or

ABC

And

sum

Carry

D

E

F

Circuit diagram of full adder

Data Types

Data type

Scalar Type Composite Type Access Type

File Type

IntegerFloat

Physical

Enumeration

Record

Array

Typical Operators

Logical Operators

AND

NOR NOT

OR NAND

XOR XNOR

Mathematical Operators

+ Addition- Subtraction

* Multiplication

/ Division

Relational Operators

= Equal/= Not Equal< Less than> Greater

than

Operators

Design Methodology

Design Methodology

Dataflow Behavioral Structural

Dataflow Concurrent/ Continuously or

Combinational Logic To give a signal a concurrent assignment

SignalName <= expression;

Full adder

Inputs

Outputs Sum (s)

Carry out (c)

AB

Carry( in)

Dataflow(cont.)

Xor

And And

Or

AB

Carry in (c _in) An

d

Sum (s)

Carry out (c_out)

D

E

F

Circuit diagram of full adder

Dataflow(cont.)library ieee;use ieee.std_logic_1164.all;ENTITY fulladder ISPORT ( a, b, c_in : IN BIT; s, c_out : OUT BIT);END fulladder;architecture fulladder_arch of fulladder isbegins<=a xor b xor c;c_out<= (a and b) or (b and c ) or (c and a);end fulladder_arch;

Behavioral The circuit is described by means of Boolean

equations and a set of sequential instructions.

4 x 1

a

d

b

c

s0 s1

x

Multiplexer 4 x 1

Behavioral (cont.)ENTITY mux ISPORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT;x, : OUT BIT);END mux;

ARCHITECTURE sequential OF mux ISProcess (a, b, c, d, s0, s1 )VARIABLE sel : INTEGER;BEGINIF s0 = ‘0’ and s1 = ‘0’ THENsel := 0;ELSIF s0 = ‘1’ and s1 = ‘0’ THENsel := 1;ELSIF s0 = ‘0’ and s1 = ‘0’ THENsel := 2;ELSEsel := 3;END IF;

CASE sel ISWHEN 0 =>x <= a;WHEN 1 =>x <= b;WHEN 2 =>x <= c;WHEN OTHERS =>x <= d;END CASE;END PROCESS;END sequential;

Structural The circuit is described as an interconnection of

known components.

xor

and

AB

sum

carry

Half Adder 1 Half Adder 2

Or

sum

Carryout

A

B

Carry in

Half adder

Full adder using half adder

Structural (cont.)HALF ADDER (USED FOR FULL ADDER)library ieee;use ieee.std_logic_1164.all;entity HA isport(a,b:in std_logic;s,c:out std_logic);end HA;architecture dataflow of HA isbegins<= a xor b;c<= a and b;end dataflow;library ieee;use ieee.std_logic_1164.all;entity OR2 isport(i1,i2:in std_logic; o:out std_logic);end OR2;architecture dataflow of OR2 isbegino<= i1 or i2;end dataflow;

Structural (cont.)--STRURAL DESCRIPTION OF FULL ADDERlibrary ieee;use ieee.std_logic_1164.all;entity FA isport(x, y, ci :in std_logic;sum,co:out std_logic);end FA;

architecture struct of FA iscomponent HA port(a, b: in std_logic;s, c:out std_logic);end component;component OR2 port(i1,i2:in std_logic;o:out std_logic);end component;signal s1,c1,c2:std_logic;begin

HA1:HA port map(x ,y ,s1 ,c1);HA2:HA port map(s1,ci,sum ,c2);ORG:OR2 port map(c1,c2,co);

end struct;

Advantages of VHDL

1. Standard language2. Concurrent & sequential statement processing3. No standard methodology4. Man machine readable documentation5. Versatile design support

References [1] Douglas L. Perry, VHDL: “programming by example”,

McGraw-Hill, New York, 2002, Fourth Edition. [2] Wai-Kai Chen,” The VLSI Handbook “, CRC Press,

USA, Second Edition. [3] Dr. Cecil alford tsai chi huang, “Digital design vhdl

laboratory notes”, 1996, version 1.01, [4] http://en.wikipedia.org/wiki/Very-large-

scale_integration [5] 1076 IEEE Standard VHDL Language Reference

Manual

Questions?