AIM

Apparatus Required

Code implementation

To display our name on the LCD screen of .

Software Xilinx ISE Project Navigator (M.63c) 12.2Xilinx ISE iMPACT (M.63c) 12.2Xilinx ISim Simulator (M.63c) 12.2

Hardware MTE Universal VTU trainer MXS3FK-VTU protoboard.

Universal VTU trainer protoboard

--libraries to be used are specified herelibrary use .ALLuse .ALLuse .ALL

entity is Port out downto out out

in ;

out in

end architecture of is

type is

IEEEIEEE STD_LOGIC_1164IEEE STD_LOGIC_ARITHIEEE STD_LOGIC_UNSIGNED

( LCD_DB: std_logic_vectorstd_logicstd_logic

std_logic

std_logicstd_logic

;. ;. ;. ;

lcd(7 0);

RS: ;RW: ;

CLK:

OE: ;rst: );

lcd;Behavioral lcd

mstate ( stFunctionSet,stDisplayCtrlSet,stDisplayClear,stPowerOn_Delay, stFunctionSet_Delay,stDisplayCtrlSet_Delay,

--DB( 7 through 0)--WE--ADR(0)

--GCLK2--ADR1:out std_logic; --ADR(1)

--ADR2:out std_logic; --ADR(2) --CS:out std_logic; --CSC

--OE--BTN

--rdone: out std_logic); --WriteDone output to work with DI05 test

-------------------------------------------------------------------- Component Declarations-------------------------------------------------------------------------------------------------------------------------------------- Local Type Declarations------------------------------------------------------------------- Symbolic names for all possible states of the state machines.

--LCD control state machine--Initialization states

--Delay states

Experiment No. 17

type is

signal downto signal signal downto signal std_logicsignal signal signal signal signal signal type is array integer range of

downto constant

stDisplayClear_Delay,stInitDne,stActWr,stCharDelay

);

wstate (stRW,stEnable,stIdle

);

clkCount: (5 0);activateW: := '0';count: (16 0):= "00000000000000000"; delayOK: := '0';OneUSClk: ;stCur:mstate:= stPowerOn_Delay; stNext:mstate;stCurW:wstate:= stIdle;stNextW:wstate;writeDone: := '0';

LCD_CMDS_T ( ) (90);

LCD_CMDS : LCD_CMDS_T := ( 0 => "00"&X"3C",1 => "00"&X"0C",2 => "00"&X"01",3 => "00"&X"02", 4 => "10"&X"50", 5 => "10"&X"72", 6 => "10"&X"61", 7 => "10"&X"76", 8 => "10"&X"65", 9 => "10"&X"65",

--Display charachters and perform standard operations

--Write delay for operations--stWait --Idle state

--Write control state machine--set up RS and RW--set up E--Write data on DB(0)-DB(7)

-------------------------------------------------------------------- Signal Declarations and Constants------------------------------------------------------------------

--These constants are used to initialize the LCD pannel.--FunctionSet:

--Bit 0 and 1 are arbitrary--Bit 2: Displays font type(0=5x8, 1=5x11)--Bit 3: Numbers of display lines (0=1, 1=2)--Bit 4: Data length (0=4 bit, 1=8 bit)--Bit 5-7 are set

--DisplayCtrlSet:--Bit 0: Blinking cursor control (0=off, 1=on)--Bit 1: Cursor (0=off, 1=on)--Bit 2: Display (0=off, 1=on)--Bit 3-7 are set

--DisplayClear:--Bit 1-7 are set

--15 bit count variable for timing delays--High when count has reached the--right delay time

--Signal is treated as a 1 MHz clock--LCD control state machine

--Write control state machine--Command set finish

--Function Set--Display ON, Cursor OFF, Blink OFF--Clear Display--return home--P --r--a--v--e--e

std_logic_vectorstd_logic --Activate Write sequence

std_logic_vector

std_logic

std_logicstd_logic_vector

10 => "10"&X"6E", 11 => "10"&X"48", 12 => "10"&X"56", 13 => "10"&X"61", 14 => "10"&X"69",15 => "10"&X"73", 16 => "10"&X"68", 17 => "10"&X"6E", 18 => "10"&X"61", 19 => "10"&X"76", 20 => "10"&X"20", 21 => "10"&X"20", 22 => "10"&X"20",23 => "00"&X"18");

lcd_cmd_ptr : 0 LCD_CMDS'HIGH + 1 := 0;

(CLK, oneUSClk)(CLK = '1' CLK'event)

clkCount

end ifend if

end process

when and or

and or

and or

and or

and

else '0'

process begin

if and thenif thenelseend if

end ifend process

process begin

case is

when if thenelseend if

downto

when

downto

;;;

delayOK

stNext RS

when

downto

when

downto

when

downto if thenelseend if

end caseend process;

process

beginif and then

if thenelseend if

end ifend process

process begin

case is

when

stInitDne =>RS

when

when

if thenelseend if

end caseend process

end

stEnable =>OE