vhdl lab final

8/6/2019 VHDL Lab Final

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ROGRAM NO: 1

AIM: Write HDL code to realize all the logic gates

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity gates is

Port ( Ain : in std_logic; ---- First Input

Bin : in std_logic; ---- Second Input

Op_not : out std_logic;

Op_or : out std_logic;

Op_and : out std_logic;

Op_nor : out std_logic;

Op_nand : out std_logic;

Op_xor : out std_logic;

Op_xnor : out std_logic);

end gates;

architecture Behavioral of gates is

begin

Op_not


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Verilog Program

module all_gates(Ain,Bin, Op_not, Op_or, Op_and, Op_nor, Op_nand, Op_xor, Op_xnor);

input Ain,Bin;

output Op_not, Op_or, Op_and, Op_nor, Op_nand, Op_xor, Op_xnor;

assing Op_not = ~Ain;

assing Op_or = Ain | Bin;

assing Op_and = Ain & Bin;

assing Op_nor = ~(Ain | Bin);

assing Op_nand = ~(Ain & Bin);

assing Op_xor = Ain ^ Bin;

assing Op_xnor = ~(Ain ^ Bin);

endmodule


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PROGRAM NO: 2

AIM: Write HDL programme for the following combinational designs

a) 2 to 4 decoder in Dataflow modelling.

VHDL Program

library ieee;




entity d2_4mx is

port ( a,b: in std_logic;

s0,s1 : in std_logic;

y0,y1,y2,y3 : out std_logic);

end d2_4mx;

architecture behave of d2_4mx is

begin

y0


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assign y2 = (a & ~b) & (s1 & ~s0);

assign y3 = (a & b) & (s1 & s0);

endmodule

b) Multiplexer, de-multiplexer, comparator

1) Multiplexer 8to1in dataflow modeling.

VHDL Program

library ieee;




entity mux8_1 is

port (I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2: in std_logic;

y:out std_logic);

end mux8_1;

architecture Behavioral of mux8_1 is

begin

y


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( not s2 and s1 and s0 and I3 ) or

( s2 and not s1 and not s0 and I4 ) or

( s2 and not s1 and s0 and I5 ) or

( s2 and s1 and not s0 and I6 ) or

( s2 and s1 and s0 and I7 );

end Behavioral;

2) Multiplexer 8to1behavioral modeling .

VHDL Program

library ieee;




entity eight_onemux is

port(a,b,c,d,e,f,g,h:in std_logic_vector(7 downto 0);

sel:in std_logic_vector(2 downto 0);

output:out std_logic_vector(7 downto 0));

end eight_onemux;

Architecture behave of eight_onemux is

begin


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process(a,b,c,d,e,f,g,h,sel)

variable y:std_logic_vector(7 downto 0);

begin

if(sel="000") then

y:=a;

elsif

(sel="001") then

y:=b;

elsif

(sel="010") then

y:=c;

elsif

(sel="011") then

y:=d;

elsif

(sel="100") then

y:=e;

elsif

(sel="101") then

y:=f; elsif

(sel="110") then

y:=g; else

y:=h;

end if;

output


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Multiplexer 8to1dataflow modeling using Verilog.

Verilog Program

module mux8to1(I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2,y);

input I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2;

output y;

assign y = (~ s2 & ~ s1 & ~ s0 &I0 ) |

(~ s2 & ~ s1 & s0 & I1 ) |

(~ s2 & s1 & ~ s0 & I2 ) |

(~ s2 & s1 & s0 & I3 ) |

( s2 & ~ s1 & ~ s0 & I4 ) |

( s2 & ~ s1 & s0 & I5 ) |


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( s2 & s1 & ~ s0 & I6 ) |

( s2 & s1 & s0 & I7 );

endmodule

4) 8 to 1 multiplexer in behavioural modeling.

Verilog Program

module mux8to1(I,sel,y);

input [7:0]I;

input [2:0]sel;

output reg y;

always@(I,sel)

begin

if(sel=="000") y=I[0];

else if (sel=="001") y=I[1];

else if (sel=="010") y=I[2];


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else if (sel=="011") y=I[3];

else if (sel=="100") y=I[4];

else if (sel=="101") y=I[5];

else if (sel=="110") y=I[6];

else

y=I[7];

end

endmodule

c) 4 bit binary to grey converter

VHDL Program

library ieee;




entity bin2_gray is

port(a:in std_logic_vector(3 downto 0);

o:out std_logic_vector(3 downto 0));

end bin2_gray;

architecture behave of bin2_gray is

begin


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process(a)

begin

o(3)


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end

endmodule

d) 4 bit comparator in dataflow modeling

VHDL Program

entity com_pr is

Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);

aeqb : out STD_LOGIC;

agtb : out STD_LOGIC;

altb : out STD_LOGIC);

end com_pr;

architecture Behavioral of com_pr is

begin


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aeqb


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library ieee;




entity comparator is

port(a,b:in std_logic_vector(3 downto 0);

altb,aeqb,agtb:out std_logic);

end comparator;

architecture behave of comparator is

begin

process(a,b)

begin

if(a > b)then

altb


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agtb


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VHDL Program

a) Dataflow modeling

library ieee;




entity fa_ader is

port(a,b,c:in std_logic;

sum,carry:out std_logic);

end fa_ader;

architecture behave of fa_ader is

signal q,l,n,p: bit;

begin

q


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b) Behavioral modeling

library ieee;




entity full_adder is

port(a,b,cin:in bit;

sum,carry:out bit);

end full_adder;

architecture behave of full_adder is

begin

process(a,b,cin)

variable s,c:bit;

begin

if(cin='0' and a='0' and b='0') then

s:='0'; c:='0';

elsif(cin='0' and a='0' and b='1') then


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s:='1'; c:='0';


s:='1'; c:='0';


s:='0'; c:='1';


s:='1'; c:='0';

elsif (cin='1' and a='0' and b='1') then

s:='0'; c:='1';

elsif (cin='1' and a='1' and b='0') then

s:='0'; c:='1';

else

s:='1'; c:='1';

end if;

sum


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c) Structural modeling.

I. entity xrgate is

Port ( j,k : in STD_LOGIC;

l : out STD_LOGIC);

end xrgate;

architecture Behavioral of xrgate is

begin

l


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architecture Behavioral of angate is

begin

r


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use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ader_struct is

Port ( a,b,cin : in STD_LOGIC;

sum, carry : out STD_LOGIC);

end ader_struct;

architecture Behavioral of ader_struct is

component angate is

Port ( p,q : in STD_LOGIC;

r : out STD_LOGIC);

end component;

component org is

Port ( p,q : in STD_LOGIC;

r : out STD_LOGIC);

end component;

component xrgate is

Port ( j,k : in STD_LOGIC;

l : out STD_LOGIC);

end component;

signal m,n,o:STD_LOGIC;


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begin

STR1 : xrgate port map(a,b,m);

STR2 : xrgate port map(m,cin,sum);

STR3 : angate port map(a,b,n);

STR4 : angate port map(m,cin,o);

STR5 : org port map(o,n,carry);

end Behavioral;

4. Write a model for 32 bit ALU to perform according to given table below

en Sel Arithmetic function Logic function

0 000 Ain

00 001 Ain 1

0 010 1 Ain + 1

0 011 Bin

0 100 Bin 1

0 101 Bin + 1


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0 110 Ain - Bin

0 111 Ain + Bin

1 000 Not Ain

1 001 Not Bin

1 010 Ain or Bin

1 011 Ain and Bin

1 100 Ain nor Bin

1 101 Ain nand Bin

1 110 Ain xor Bin

1 111 Ain xnor Bin

Arithmetic function program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;


entity ari_thop is

port ( a,b : in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);


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arith_out : out STD_LOGIC_VECTOR (31 downto 0));

end ari_thop;

architecture Behavioral of ari_thop is

begin

arith_out


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logic_out : out STD_LOGIC_VECTOR (31 downto 0));

end logic_op;

architecture Behavioral of logic_op is

begin

logic_out


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z : out STD_LOGIC_VECTOR (31 downto 0));

end mx2_1pro;

architecture Behavioral of mx2_1pro is

begin

z


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Alu_output : out STD_LOGIC_VECTOR (31 downto 0));

end ALU_MAIN;

architecture Behavioral of ALU_MAIN is

component ari_thop is

Port ( a,b : in STD_LOGIC_VECTOR (31 downto 0);


arith_out : out STD_LOGIC_VECTOR (31 downto 0));

end component;

component logic_op is

Port ( p,q: in STD_LOGIC_VECTOR (31 downto 0);


logic_out : out STD_LOGIC_VECTOR (31 downto 0));

end component;

component mx2_1pro is

Port (x,y : in STD_LOGIC_VECTOR (31 downto 0);

s : in STD_LOGIC;

z : out STD_LOGIC_VECTOR (31 downto 0));

end component;

signal ar_1,log_2:STD_LOGIC_VECTOR (31 downto 0);

begin

ALU1 : ari_thop port map(Ain,bin,sel,ar_1);

ALU2 : logic_op port map(Ain,bin,sel,log_2);


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ALU3 : mx2_1pro port map(ar_1,log_2,en,Alu_output);

end Behavioral;

5. develop the HDL code for the following flip-flops, SR, JK, D, T

SR flip-flop

library IEEE;




entity rs_ff is


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port(r,s,clk : in std_logic;

q : inout std_logic:='0';

qbar : inout std_logic:='1');

end rs_ff;

architecture flip of rs_ff is

signal m:std_logic:='0';

signal n:std_logic:='1';

begin

m


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qbar:out bit:='1'); --compliment of the output

end jkff;

architecture behave of jkff is

begin

process(rst,clk,j,k)

variable a:bit:='0';

begin

if (rst='1') then

a :='0';

elsif(clk='1' and clk'event) then

if (j='0' and k='0') then

a := a;

elsif

(j='0' and k='1') then

a := '0';

elsif (j='1' and k='0') then

a := '1';

else

a := not a;

end if;

end if;

q


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end process;

end behave;

D-Flip-flop

library IEEE;




entity DFF is

port (

clk: in STD_LOGIC; --Global Clock as Input


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end TFF;

architecture t_ff_arch of TFF is

begin

process(clk)

begin

if(clk'event and clk='1')then

q


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end sync_counter;

architecture counter_arch of sync_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);

begin

process (CLK)

begin

if CLK='1' and CLK'event then

if RESET='1' then --Synchronous reset

TEMP '0');

ELSE

TEMP


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architecture counter_arch of async_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);

begin

process (CLK,RESET)

begin

if RESET='1' then --asynchronous reset

TEMP '0');

elsif CLK='1' and CLK'event then

TEMP

vhdl lab final

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