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VHDL Key IdeaVHDL Key Idea

A key idea in VHDL is to define the interface of a A key idea in VHDL is to define the interface of a hardware module while hiding its internal details.hardware module while hiding its internal details.

A VHDL A VHDL entityentity is simply a declaration of a module’s inputs is simply a declaration of a module’s inputs and outputs, i.e., its external interface signals or ports.and outputs, i.e., its external interface signals or ports.

A VHDL A VHDL architecturearchitecture is a detailed description of the is a detailed description of the module’s internal structure or behavior.module’s internal structure or behavior.

entity

architectureinterface interface

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VHDL Interface - PortsVHDL Interface - Ports

You can think of the entity as a “wrapper” for the You can think of the entity as a “wrapper” for the architecturearchitecture

hiding the details of what’s inside hiding the details of what’s inside

providing “ports” to other modulesproviding “ports” to other modules

input port

entity

architecture output port...

...

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VHDL Conceptual ModelVHDL Conceptual Model

VHDL actually allows you VHDL actually allows you to define multiple to define multiple architectures for a single architectures for a single entity entity

it also provides a it also provides a configuration management configuration management facility that allows you to facility that allows you to specify which architecture specify which architecture to use during a particular to use during a particular synthesis runsynthesis run

entity

architecture 1

architecture 2

configuration

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VHDL Program FileVHDL Program File

In the text file of a VHDL program:

the entity, architecture, and configuration declarations are all separated

not nested as the previous diagram may have implied

We will use white space to set them apart

mydesign.vhd

entity

architecture

configuration

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VHDL Program FileVHDL Program File

In large projects the entities and architectures are sometimes defined in separate files, which the compiler matches according to their declared names

VHDL ignores spaces and line breaks

Comments begin with two hyphens (--) and end at the end of a line

VHDL defines many special character strings, called reserved words or keywords

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VHDL reserved words or keywordsVHDL reserved words or keywords

Some reserved words or keywordsSome reserved words or keywordsentity, port, is, in, out, end, entity, port, is, in, out, end, architecture, begin, when, else, architecture, begin, when, else, not,not, etc.etc.

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Elements of VHDLElements of VHDL

Syntax (the rules)Syntax (the rules)

Five design units (or elements)Five design units (or elements)

Identifiers (naming constraints)Identifiers (naming constraints)

Data objects (what you name)Data objects (what you name)

Data types (enumerated, integer, arrays, etc.)Data types (enumerated, integer, arrays, etc.)

ExamplesExamples

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VHDL Provides Five Design UnitsVHDL Provides Five Design UnitsEntity DeclarationEntity Declaration

Specifies the Specifies the NAMENAME and lists the interface and lists the interface PORTSPORTS

Architecture BodyArchitecture BodyModels the actual circuit “guts” within an entityModels the actual circuit “guts” within an entity

Configuration DeclarationConfiguration DeclarationIdentifies which arch. should be used with an entityIdentifies which arch. should be used with an entitySpecifies location of components used within arch.Specifies location of components used within arch.

Package Declaration – Package Declaration – like a header file in Clike a header file in C

Package Body – Package Body – like an implementation file in Clike an implementation file in C

PackagesPackages are libraries containing type definitions, overloaded are libraries containing type definitions, overloaded operators, components, functions, and procedures. They have a operators, components, functions, and procedures. They have a “declarative” section and a BODY section. Elements of a Package “declarative” section and a BODY section. Elements of a Package can be used by many entities in a design, or many designs.can be used by many entities in a design, or many designs.

Our initial examples will focus on the first three design units.

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VHDL Identifiers (Names)VHDL Identifiers (Names)Basic identifierBasic identifier

starts with a letterstarts with a lettermade up of letters, numbers, and underscore “_” charactermade up of letters, numbers, and underscore “_” charactercannot end with an underscorecannot end with an underscorean underscore cannot follow an underscorean underscore cannot follow an underscorecase-insensitive: case-insensitive: MY_Signal_NameMY_Signal_Name = = my_signal_namemy_signal_name

Extended IdentifierExtended Identifierany text within 2 backslashesany text within 2 backslashese.g., e.g., \2FOR$\ \-23signal\\2FOR$\ \-23signal\ etc. etc.case is significant: case is significant: \COUNT\\COUNT\ not equal to not equal to \count\\count\, and, and\FRAMUS\\FRAMUS\ not equal to basic identifier not equal to basic identifier FRAMUSFRAMUSNot often used – Not often used – not necessarily supported in synthesis !!not necessarily supported in synthesis !!

not recommended

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VHDL Identifiers (Names)VHDL Identifiers (Names)

Identifiers in the exampleIdentifiers in the examplehalf_adder, A, B, half_adder, A, B, BITBIT, SUM , SUM andand CARRYCARRY

BITBIT is a built-in identifier for a predefined is a built-in identifier for a predefined type; and not considered as a reserved word type; and not considered as a reserved word because it can be redefinedbecause it can be redefined

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Four Classes of Data ObjectsFour Classes of Data ObjectsConstantConstant

Holds a single value of a given type – cannot change.Holds a single value of a given type – cannot change.

VariableVariableHolds a single value of a given type.Holds a single value of a given type.New value of same type can be “assigned” – (instantly)New value of same type can be “assigned” – (instantly)

SignalSignalHolds a LIST of values of a given type.Holds a LIST of values of a given type.Present value + a set of possible future valuesPresent value + a set of possible future valuesNew values can be assigned New values can be assigned at some future time – not now!at some future time – not now!Signals have ATTRIBUTES: [signal’attribute]Signals have ATTRIBUTES: [signal’attribute]

FileFileContains a sequence of values of one or more types.Contains a sequence of values of one or more types.Usually read or written to using proceduresUsually read or written to using proceduresFor simulation – not synthesisFor simulation – not synthesis

analogous to a “wire”analogous to a “wire”

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Data TypesData TypesScalar TypesScalar Types

Enumerated : a list of valuesEnumerated : a list of valuesIntegerIntegerFloating PointFloating PointPhysical : with units, for physical quantitiesPhysical : with units, for physical quantities

Composite TypesComposite TypesArray (all of same type)Array (all of same type)Record (can be different types)Record (can be different types)

Access TypeAccess TypeFile TypeFile Type

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Entity DeclarationEntity Declaration

Specifies the name of the entitySpecifies the name of the entity

Lists the set of interface PORTSLists the set of interface PORTS

PORTSPORTS are SIGNALS are SIGNALS that enter or leave the entity that enter or leave the entity

This is the “black box,” or block diagram view This is the “black box,” or block diagram view

Half-AdderA

B

SUM

CARRY

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Syntax of a VHDL entity declarationSyntax of a VHDL entity declaration

entity entity-name is port( signal-names : mode signal-type;

signal-names : mode signal-type; … signal-names : mode signal-type);

end entity-name;

entity-name A user selected identifiersignal-names A comma separated list of 1 or more user selected

identifiersmode One of the four reserved wordssignal-type A built in or user defined signal type

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Entity DeclarationEntity Declaration

entity half_adder is port( A, B : in BIT; SUM, CARRY : out BIT);end half_adder;

entity half_adder is port( A, B : in BIT; SUM : out BIT; CARRY : out BIT );end entity half_adder;

no “;” after last signal

end of port statement

NAME

MODE

TYPE

optional words, but recommended

White space is ignored

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VHDL Signal ModesVHDL Signal Modes

inin – means means input-ONLY, input-ONLY, you cannot use a you cannot use a mode mode inin signal on the signal on the LEFTLEFT side of an equation (that is, you can’t side of an equation (that is, you can’t assign a new value to inputs)assign a new value to inputs)outout – means means output-ONLY, output-ONLY, you cannot use a you cannot use a mode mode outout signal on the signal on the RIGHTRIGHT side of an equation (that is, you side of an equation (that is, you can’t “use” the outputs)can’t “use” the outputs)inoutinout – means means bi-directional, bi-directional, like a three-state bus, for like a three-state bus, for example. This mode is typically used for three-state example. This mode is typically used for three-state input/output pins on PLDsinput/output pins on PLDsbufferbuffer – means the signal is an output of the entity, and – means the signal is an output of the entity, and its value can also be read inside the entity’s architectureits value can also be read inside the entity’s architecture

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Entity DeclarationEntity Declaration

entity half_adder is port( A, B : in BIT; SUM, CARRY : out std_logic);end half_adder;

entity half_adder is port( A, B : in std_logic; SUM : out std_logic; CARRY : out std_logic );end entity half_adder;

Using IEEE 1164 standard signals and data types:

TYPE

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Example: LogicFcnExample: LogicFcn

entity architecture

A

B

C Y

ports

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Entity Declaration for LogicFcnEntity Declaration for LogicFcnlibrary IEEE;

use IEEE.std_logic_1164.all;

 entity LogicFcn is

port (

A: in std_logic;

B: in std_logic;

C: in std_logic;

Y: out std_logic

);

end entity LogicFcn; 

ABC

Y

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An entity’s ports and their modes and types are all that is An entity’s ports and their modes and types are all that is seen by other modules that use it seen by other modules that use it The entity’s internal operation is specified in it’s The entity’s internal operation is specified in it’s architecture definitionarchitecture definition whose general syntax is whose general syntax is as shown nextas shown nextThe The entity-nameentity-name in this definition must be the same as in this definition must be the same as the one given previously in the entity declarationthe one given previously in the entity declarationThe The architecture-namearchitecture-name is a user selected identifier, is a user selected identifier, usually related to the usually related to the entity-nameentity-name; it can be the same ; it can be the same as the entity name if desiredas the entity name if desired

Architecture definitionArchitecture definition

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An architecture’s external interface signals (ports) are An architecture’s external interface signals (ports) are inherited from the port-declaration part of its inherited from the port-declaration part of its corresponding entity declarationcorresponding entity declarationAn architecture may include signals and other declarations An architecture may include signals and other declarations that are local to that architecturethat are local to that architectureDeclaration common to multiple entities can be made in a Declaration common to multiple entities can be made in a separate “package” used by all entitiesseparate “package” used by all entitiesDeclarations can appear in any orderDeclarations can appear in any order

Architecture definitionArchitecture definition

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Syntax:VHDL architectureSyntax:VHDL architecture

architecture arch-name of entity-name is type declarations signal declarations constant declarations function definitions procedure definitions component declarationsbegin

concurrent-statements

end arch-name;

named wires

later

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It gives the same information about a signal as in a port It gives the same information about a signal as in a port declaration, except that no mode is specified:declaration, except that no mode is specified:

signal signal signal-names : signal-type;Zero or more signals can be defined within an architecture, Zero or more signals can be defined within an architecture, and they roughly correspond to named wires in a logic and they roughly correspond to named wires in a logic diagramdiagramThey can be read or written within the architecture They can be read or written within the architecture definition and, like other local objects, can be referenced definition and, like other local objects, can be referenced only within the encompassing architecture definitiononly within the encompassing architecture definition

Signal declarationSignal declaration

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VHDL variables are similar to signals, except that they VHDL variables are similar to signals, except that they usually don’t have physical significance in a circuitusually don’t have physical significance in a circuitVariables are used in VHDL functions, procedures and Variables are used in VHDL functions, procedures and processesprocessesWithin these program elements, the syntax of a variable Within these program elements, the syntax of a variable declaration is just like that of a signal declaration, except declaration is just like that of a signal declaration, except that the variable keyword is usedthat the variable keyword is used

variable variable variable-names : variable-type;

Variable declarationVariable declaration

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All signals, variables and constants in aVHDL program All signals, variables and constants in aVHDL program must have an associated “type”must have an associated “type”The type specifies the set of range of values that the object The type specifies the set of range of values that the object can take on, and there is also typically a set of operators can take on, and there is also typically a set of operators (such as add, AND, and so on ) associated with a given (such as add, AND, and so on ) associated with a given typetypeVHDL has just a few predefined typesVHDL has just a few predefined typesbit, character, severity_level, bit, character, severity_level, bit_vector, integer, string, boolean, bit_vector, integer, string, boolean, real, timereal, time

Types and ConstantsTypes and Constants

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The only ones we’ll see here are integer, character, The only ones we’ll see here are integer, character, and booleanand booleanThe built-in types bit and bit_vector may seem to The built-in types bit and bit_vector may seem to be essential in digital design, but the be essential in digital design, but the “user-“user-defined”defined” types std_logic and std_logic_vector are types std_logic and std_logic_vector are more useful (IEEE 1164 std)more useful (IEEE 1164 std)

Types and ConstantsTypes and Constants

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Type integersType integersAll implementations support 32-bit integers, All implementations support 32-bit integers, with a range of values from –(2with a range of values from –(23131 – 1) to – 1) to +(2+(23131 – 1) – 1)Integer data types with a smaller range can be Integer data types with a smaller range can be defined to save hardware (no sense forcing a defined to save hardware (no sense forcing a 32-bit counter when you need a 4-bit counter)32-bit counter when you need a 4-bit counter)Examples of legal integersExamples of legal integers

56349 6E2 0 98_71_2856349 6E2 0 98_71_28(Underscores can be thrown in anywhere, and (Underscores can be thrown in anywhere, and don’t change the value of the number.)don’t change the value of the number.)

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Integer OperatorsInteger Operators

VHDL provides the following predefined basic VHDL provides the following predefined basic integer operators:integer operators:

Keyword+-*/modremabs**

DefinitionadditionsubtractionmultiplicationdivisionModulo divisionModulo remainderAbsolute valueexponentiation

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Enumerated TypesEnumerated Types

The most commonly used types in typical VHDL The most commonly used types in typical VHDL programs are user-defined types and the most programs are user-defined types and the most common of these are enumerated types, which common of these are enumerated types, which are defined by listing their valuesare defined by listing their values

Predefined types character and boolean are Predefined types character and boolean are enumerated typesenumerated types

CHARACTER – CHARACTER – one of the ASCII setone of the ASCII set

BOOLEANBOOLEAN – can be FALSE or TRUE – can be FALSE or TRUE

Built-in operators for boolean type are listed nextBuilt-in operators for boolean type are listed next

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Boolean OperatorsBoolean Operators

VHDL provides the following predefined basic VHDL provides the following predefined basic boolean operators:boolean operators:

Keywordandorxorxnor*

nandnornot

Definitionconjunctioninclusive orexclusive orcomplement exclusive orcomplement conjunctioncomplement inclusive orcomplement

* only predefined in VHDL-93

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Enumerated TypesEnumerated Types

A type declaration for an enumerated type has the format A type declaration for an enumerated type has the format shown belowshown belowThe value list is a comma-separated list (enumeration) of The value list is a comma-separated list (enumeration) of all possible values of the typeall possible values of the typeThe values may be user-defined identifiers or charactersThe values may be user-defined identifiers or charactersSyntaxSyntax

type type-name is (value-list);type type-name is (value-list);subtype subtype-name is type-name start subtype subtype-name is type-name start to end;to end;

subtype subtype-name is type-name start subtype subtype-name is type-name start downto end;downto end;