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Basic VHDl problem

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------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 11:17:38 10/28/2014 -- Design Name: -- Module Name: assign_4_prob_1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity D_ff is Port ( D ,Clk: in STD_LOGIC; Q : out STD_LOGIC; Qbar : out STD_LOGIC);end D_ff;architecture Behavioral of D_ff isbeginprocess(Clk,D)beginif(Clk'event and Clk='1')thenQ

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