vector.weebly.comvector.weebly.com/uploads/1/3/1/0/1310781/final_report.docx · web viewchapter 1....

Chapter 1

INTRODUCTION TO VLSI SYSTEMS

Historical Perspective:

The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of VLSI. The number of applications of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field.

The current leading-edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability. This trend is expected to continue, with very important implications on VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth (in order to handle real-time video, for example). The other important characteristic is that the information services tend to become more and more personalized (as opposed to collective services such as broadcasting), which means that the devices must be more intelligent to answer individual demands, and at the same time they must be portable to allow more flexibility/mobility.

As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these functions in a small system/package is also increasing. The level of integration as measured by the number of logic gates in a monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Table 1.1 shows the evolution of logic complexity in integrated circuits over the last three decades.

ERA DATE COMPLEXITY (number of logic blocks per chip)

Single transistor 1959 less than 1Unit logic (one gate) 1960 1Multi-function 1962 2 - 4Complex function 1964 5 - 20Medium Scale Integration 1967 20 - 200 (MSI)Large Scale Integration 1972 200 - 2000 (LSI)Very Large Scale Integration 1978 2000 – 20000 (VLSI)Ultra Large Scale Integration 1989 20000 - ? (ULSI)

Table-1.1: Evolution of logic complexity in integrated circuits.

The most important message here is that the logic complexity per chip has been (and still is) increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides:

Less area/volume and therefore, compactness Less power consumption Less testing requirements at system level Higher reliability, mainly due to improved on-chip interconnects Higher speed, due to significantly reduced interconnection length Significant cost savings

Figure-1.2: Evolution of integration density and minimum feature size, as seen in the early 1980s.

Figure 1.2 shows the history and forecast of chip complexity - and minimum feature size - over time, as seen in the early 1980s. At that time, a minimum feature size of 0.3 microns was expected around the year 2000. The actual development of the technology, however, has far exceeded these expectations. A minimum size of 0.25 microns was readily achievable by the year 1995. As a direct result of this, the integration density has also exceeded previous expectations - the first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994, pushing the envelope of integration density.

VLSI design Flow:

Figure-1.5: A more simplified view of VLSI design flow.

Figure 1.5 provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market.Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer defined architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom up) as early as possible.

Systematic design methods (called design methodologies) are necessary for successfully designing complex digital hardware. Such design methods can be classified into following three broad categories :

# Top-down Design.# Bottom-up Design.# Mixed Top-down and Bottom-up Design.

Top-down Design

This method relies on realizing the desired complex behaviour of a hardware by partitioning it into intercommunicating simpler sub-behaviours.

The designer controls the partitioning and specifies the sub-behaviour of each partition. There are no priority given parts or components.

This methodology is applied recursively to break down the original complex behaviour into an interconnection of simple enough behaviours whose implementation is known.

Bottom-up Design

This method aims at realizing the desired complex behaviour by suitable selection and interconnection of parts / components from an available set of parts /components with known behaviours (builiding-block approach). Such an available set of parts/components is often a standard cell library or a library of TTL gates.

This method is adequate whenever the complexity of desired behaviour is not too high as compared to the complexity of behaviours of available parts. An example is the designing of the logic circuit of an ALU-bit or a counter using TTL gates.

However, this method does not work when the complexity of desired behaviour is much too high as compared to the complexities of behaviours of available parts. An example is the designing of the logic circuit of a Microprocessor using TTL gates.

Mixed Top-down and Bottom-up Design

This is the most commonly used and practical method of designing complex VLSI circuits.It aims at realizing the desired complex behaviour by first following the topdown design method (recursively a few times, if necessary) and partitioning the desired complex behaviour into a set of intercommunicating simpler sub-behaviours, and then realizing the resulting simpler sub-behaviours by following the bottom-up design method e.g. by selection and interconnection of parts from an available library/set of parts with known behaviours.

VLSI Design Styles:

Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the functionality at low cost.

Field Programmable Gate Array (FPGA)

Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality. This design style provides a means for fast prototyping and also for

cost-effective chip design, especially for low-volume applications. A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures. The programming of interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. A general architecture of FPGA from XILINX is shown in Fig. 1.12. A more detailed view showing the locations of switch matrices used for interconnect routing is given in Fig. 1.13. A simple CLB (model XC2000 from XILINX) is shown in Fig. 1.14. It consists of four signal input terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an SR-latch, and a look-up table (LUT). The LUT is a digital memory that stores the truth table of the Boolean function. Thus, it can generate any function of up to four variables or any two functions of three variables. The control terminals of multiplexers are not shown explicitly in Fig. 1.14. The CLB is configured such that many different logic functions can be realized by programming its array. The typical design flow of an FPGA chip starts with the behavioral description of its functionality, using a hardware description language such as VHDL. The synthesized architecture is then technology-mapped (or partitioned) into circuits or logic cells. At this stage, the chip design is completely described in terms of available logic cells. Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs) and determines the routing patterns among the cells in accordance with the netlist.

Figure-1.12: General architecture of Xilinx FPGAs.

performance of the design can be simulated and verified before downloading the design for programming of the FPGA chip. The programming of the chip remains valid as long as the chip is powered-on, or until new programming is done. In most cases, full utilization of the FPGA chip area is not possible - many cell sites may remain unused.

The largest advantage of FPGA-based design is the very short turn-around time, i.e., the time required from the start of the design process until a functional chip is available. Since no physical manufacturing step is necessary for customizing the FPGA chip, a functional sample can be obtained almost as soon as the design is mapped into a specific technology. The typical price of FPGA chips are usually higher than other realization alternatives (such as gate array or standard cells) of the same design, but for small-volume production of ASIC chips and for fast prototyping, FPGA offers a very valuable option.

Full Custom Design

Although the standard-cells based design is often called full custom design, in a strict sense, it is somewhat less than fully custom since the cells are pre-designed for general use and the same cells are utilized in many different chip designs. In a fuller custom design, the entire mask design is done anew without use of any library. However, the development cost of such a design style is becoming prohibitively high. Thus, the concept of design reuse is becoming popular in order to reduce design cycle time and development cost. The most rigorous full custom design can be the design of a memory cell, be it static or dynamic. Since the same layout design is replicated, there would not be any alternative to high density memory chip design. For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip, such as standard cells, data-path cells and PLAs. In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer, design productivity is usually very low - typically 10 to 20 transistors per day, per designer.In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high- performance microprocessors and FPGA masters.

Fig: Impact of different VLSI design styles on design cycle time & achievable chip performance.

Chapter 2

CMOS TECHNOLOGY

Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS also allows a high density of logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI chips.

Technical details:

"CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power when static, and is denser than other implementations having the same functionality. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters. These devices are commonly called "chips", although within the industry they are also referred to as "die" (singular) or "dice", "dies", or "die" (plural).

Composition:

The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal–oxide–semiconductor field-effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.

Output is inversion of input:

CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.

The image above shows what happens when an input is connected to both a PMOS transistor and an NMOS transistor. When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an off (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an on (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current

drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this opposite behavior of input and output, the CMOS circuits' output is the inversion of the input.

Working of NAND gate:

Shown below is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

Working of NOR gate:

In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.

Chapter 3

Hardware Description Language

Aspects of Hardware Description:

There are two fundamental aspects of any piece of hardware:

# Behavioral.# Structural.

The behavioral aspect deals with the behavior of hardware: what is its functionality and speed (without worrying about the constructional details).

The structural aspect tells us about the hardware construction: which parts have been selected for construction and how they have been interconnected.

Of course, complete information on the hardware requires a combination of both the behavioral and structural aspects. However, in many practical situations, we may need to focus only on a single aspect.Besides the behavioral (functionality and timing) and structural (net list) aspects, there is also a third aspect to a hardware. This is the physical aspect (e.g. the layout of the IC or the PCB).In fact the information on each of these aspects is itself represented at different levels of detail, using different abstraction levels. Each abstraction level is used to represent information on an aspect of the design at a certain convenient level of detail.For example, the structural aspect (the net list) of a VLSI design can be described at several different abstraction levels e.g. the system structure level, the processor-buses level, the ALU-register level, the gate ip/op level, and the transistor level. Simultaneously, the behavioral and physical aspects of a VLSI chip/system can also be described at different levels of abstraction. Very often the three aspects of a design are called the three design domains. And for each domain (aspect) there are several different levels of abstraction at which the design information in that domain is represented.Therefore, a complete system of maintaining, providing, and exchanging information on a VLSI design must address all the three domains (aspects) individually or in combination. However, a single design description language that permits design description in all the three design domains at each of the abstraction levels does not exist.

Hardware description languages (HDLs) have been developed to provide a means of describing, validating, maintaining and exchanging design information on complex digital VLSI chips across multiple levels of design abstractions used during the design process in behavioral and structural domains.

Front-End Design Steps Using HDL:

Behavioral Design:

To capture the behavior of the chip in a formal form using a hardware description language (HDL) following steps are followed-

# This step involves coding of the behavior of the chip (usually specified in a natural language description or other informal means e.g. tables, diagrams etc.) in a formal hardware description language (HDL).# The HDL description formally captures the functional behavior (input to output transformations done by the chip) and timing behavior at the pins of the chip. The description has no regard as to how the behavior would be realized in a hardware form.

Back-End Design Steps:

Floor Planning and Physical Partitioning:

# This step partitions the chip-area into area segments and allocates logic gates/logic blocks to be placed in each area segment.# Floor planning provides a useful level of hierarchy in the optimization of the physical design (layout generation) by taking advantage of the designer's knowledge of functional and logical hierarchies of the design.

Expectations from a HDL:

# It should serve as an integral documentation of the design process.

# It must support multiple abstraction levels in both behavioural and structural domains, and offer constructs that naturally map the designer's view and understanding of the circuit at different abstraction levels into HDL descriptions.

# The language should not dictate or put restrictions on the choice of a particular design methodology by the designer. It should have a rich enough set of constructs to support any design methodology.

# The language should not be tied to a particular technology (such as CMOS,TTL, ECL) and/or feature size. It should work across the spectrum of technologies and feature sizes.

# It should be flexible and easily extendable by the user.

# It should have a good support in terms of the availability of CAD tools and design libraries.

# It should be a medium for design exchange and design re-use.

# It should have formal unambiguous semantics.

Advantages of HDL-Based Design Approach:

# Specifications captured using HDLs are easier to understand, less error prone, and can be modified easily.# HDL descriptions are faster to simulate.# Design of complex systems is easier.# It results in a shorter design cycle.

Disadvantages of HDL-Based Design Approach:

# only a subset of the HDL constructs can be synthesized.# the resulting hardware is generally greater than the optimum.

Specifying Logic:

How do we specify logic?

1. through Boolean Expressions.Y = (A.B' + B.C.D). (C' + A')

2. through Truth Tables.

3. through Natural Language Statements.

4. through Programming Language Statements.(C, C++, Pascal, Basic, FORTRAN)

5. Through Behavioral Description Constructs of Hardware Description Languages(VHDL, Verilog) e.g. process statement in VHDL.

Implementing Logic:

How do you efficiently implement logic given the constraints on-

# Speed of Operation.# Power Consumption.# Area.# Design Time.# Design Cost.# Product Cost.# Upgradability.

The strategic planning and selection of an optimal approach for implementationof logic is typically called architecting or architecture design.

Specifying and Implementing Logic:

Example Logic Specification: Z = A + B + C + D + E

Architecture #1 (Combinational) for Logic Implementation

Architecture #2 (Combinational) for Logic Implementation

Architecture #3 (Sequential) for Logic Implementation

Sequential Architectures:

Characteristics of Sequential Architectures:

# They need storage elements besides combinational logic.# They need a sequence of steps to implement the full logic specification.#Next step should be taken only when the logic function of the previous step has been completed and its result saved.# the stepping can be asynchronous/self-timed/synchronous (with timing signal called clock).# depending upon the selection of method of stepping, sequential architectures can be asynchronous/self-timed/synchronous.

HDL-Based RTL Design:

In the hierarchy of design abstractions RTL represents that level of design detail where the designer has already decided upon the detailed architecture of his design.By detailed architecture we mean that the designer has already fixed the following:

# All the registers he is going to use in his design.# All the functional blocks he is going to use in his design# How under the controls issued by a Finite State Machine (FSM) data stored in specific registers will be supplied to functional blocks to form Boolean expressions that will then be stored in specified registers on a clock-cycle by clock-cycle basis.

In fact, the transfer of data from one or more source registers to a destination register after processing by a functional unit that lies in the transfer path is called a register transfer step.

A RTL design description, therefore, captures all the architectural blocks of the design e.g. registers, functional units (ALUs, Barrel shifters, Multipliers, etc.) and multiplexers and/or buses interconnecting them. It enumerates all the interface points of each architectural block (data inputs, data outputs, control inputs, and clock . where applicable) and describes the functioning of the blocks behaviorally. Also included in the design is the control generation block, the FSM that generates controls for all the blocks in the architecture.

RTL and Logic Synthesis:

Currently RTL VHDL designs are created and validated by designers. A logic synthesis tool (such as Design Compiler from Synopsys) is then used to automatically generate the gate level design and output the net-list for a specific technology library.Besides the RTL design, a priority of design objectives (whether to design for maximum speed or minimum area), the level of effort permitted for design optimization (low, medium, high) and a set of constraints are also input to the logic synthesizer.

The constraints may take the simple form of specification of an overall clocking rate for the design or the designer may constrain delays along specified paths running across one or more blocks of the RTL design. Additional constraints like maximum permissible fan-ins and fan-outs for gates to be used, maximum permissible rise and fall times for nodes in the circuit, preclusion of / preference for certain cells in the target technology library etc. can also be provided to theLogic synthesis tool.While constraints can be supplied interactively to the synthesis tool, usually they are included in a separate constraint file which is read in by the synthesis tool or they are part of a synthesis script.

The synthesis tool then translates the RTL design into a gate level net-list while trying to satisfy all the constraints supplied by the designer. Detailed timing reports on the generated net-lists are provided by the synthesis tool along-with a list of constraints that could not be satisfied (if that is the case).If some constraints are not met, then the designer should either relax the constraints, or try `high' effort of optimization, or alter his architecture and rewrite the RTL code or part thereof.

The synthesis tools typically work in two phases:1. In the first phase a design using generic gates is synthesized.2. In the second or technology mapping phase the generic gates are replaced by cells in the specified technology library. After the placement-and-routing of the generated net-list, delays from the layout are extracted and back-annotated into the net-list. Timing checks are once again carried out on the back annotated net-list to see if the timing constraints are still satisfied post-layout.If some timing constraints are not satisfied post-layout, then either a place-and-route iteration or a synthesis iteration followed by a fresh place-and-route are carried out until timing closure is achieved.

Chapter 4

VHDL

Introduction:

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description.

The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language +concurrent language +

net-list language +timing specifications +

waveform generation language => VHDL

Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also be generated using the same constructs. All the above constructs may be combined to provide a comprehensive description of the system in a single model. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore, models written in this language can be verified using a VHDL simulator.

History:

The requirements for the language were first generated in 1981 under the VHSIC program. In this program, a number of U.S. companies were involved in designing VHSIC chips for the Department of Defense (DoD). At that time, most of the companies were using different hardware description languages to describe and develop their integrated circuits. As a result, different vendors could not effectively exchange designs with one another. Also, different vendors provided DoD with descriptions of their chips in different hardware description languages. Reuse was also a big issue. Thus, a need for a standardized hardware description language for design, documentation, and verification of digital systems was generated. A team of three companies, IBM, Texas Instruments, and Intermetrics, were first awarded the contract by the DoD to develop a version of the language in 1983. Version 7.2 of VHDL was developed and released to the public in 1985. There was strong industry participation throughout the VHDL language development process, especially from the companies that were developing

VHSIC chips. After the release of version 7.2, there was an increasing need to make the language an industry-wide standard. Consequently, the language was transferred to the IEEE for standardization in 1986. After a substantial enhancement to the language, made by a team of industry, university, and DoD representatives, the language was standardized by the IEEE in December 1987; this version of the language is now known as the IEEE Std 1076-1987.

Capabilities:

The following are the major capabilities that the language provides along with the features that differentiate it from other hardware description languages.

The language supports flexible design methodologies: top-down, bottom-up, or mixed. It supports both synchronous and asynchronous timing models. The language supports three basic different description styles: structural, dataflow, and

behavioral. A design may also be expressed in any combination of these three descriptive styles.

The language has elements that make large scale design modeling easier, for example, components, functions, procedures, and packages.

Models written in this language can be verified by simulation since precise simulation semantics are defined for each language construct.

Basic Terminologies:

VHDL is a hardware description language that can be used to model a digital system. The digital system can be as simple as a logic gate or as complex as a complete electronic system. A hardware abstraction of this digital system is called an entity in this text. An entity X, when used in another entity Y, becomes a component for the entity Y. Therefore, a component is also an entity, depending on the level at which you are trying to model. To describe an entity, VHDL provides five different types of primary constructs, called" design units. They are-

1. Entity declaration2. Architecture body

3. Configuration declaration4. Package declaration

5. Package body

1. Entity Declaration

The entity' declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment.

Here is an example of an entity declaration for the half-adder circuit shown in Fig. 2.3. entity HALF_ADDER is port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER;

2. Architecture Body

The internal details of an entity are specified by an architecture body using any of the following modeling styles:

a. Structural style of modeling- As a set of interconnected components b. Dataflow style of modeling- As a set of concurrent assignment statements c. Behavioral style of modeling- As a set of sequential assignment statements d. Mixed style of modeling- Any combination of the above three.

a. Structural Style of Modeling

In the structural style of modeling, an entity is described as a set of interconnected components. Such a model for the HALF_ADDER entity, shown in Fig. 2.3, is described in an architecture body as shown below-

architecture HA_STRUCTURE of HALF_ADDER is component XOR2 port (X, Y: in BIT; Z: out BIT); end component; component AND2 port (L, M: in BIT; N: out BIT); end component; begin X1: XOR2 port map (A, B, SUM); A1: AND2 port map (A, B, CARRY); end HA_STRUCTURE;

The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ADDER (presented in the previous section) specifies the interface ports for this architecture body. The architecture body is composed of two parts: the declarative part (before the keyword begin) and the statement part (after the keyword begin). Two component declarations are present in the declarative part of the architecture body. These declarations

specify the interface of components that are used in the architecture body. The components XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they may later be bound to other components in a library.

b. Dataflow Style of Modeling

In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this modeling style, but it can be implicitly deduced. Consider the following alternate architecture body for the HALF..ADDER entity that uses this style.

architecture HA_CONCURRENTof HALF_ADDER is begin SUM <= A xor B after 8 ns; CARRY <= A and B after 4 ns; end HA_CONCURRENT;

The dataflow model for the HALF_ADDER is described using two concurrent signal assignment statements (sequential signal assignment statements are described in the next section). In a signal assignment statement, the symbol <= implies an assignment of a value to a signal.

c. Behavioral Style of Modeling

In contrast to the styles of modeling described earlier, the behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality. A process statement is a concurrent statement that can appear within an architecture body. For example, consider the following behavioral model for the D-flip flop entity.

entity LS_DFF is port (Q: out BIT; D, CLK: in BIT): end LS_DFF; architecture LS_DFF_BEH of LS_DFF is begin process (D, CLK) begin if (CLK = '1') then Q <= D; end if; end process; end LS_DFF_BEH;

A process statement, too, has a declarative part (between the keywords process and begin), and a statement part (between the keywords begin and end process). The statements appearing within the statement part are sequential statements and are executed sequentially. The list of signals specified within the parenthesis after the keyword process constitutes a sensitivity list and the process statement is invoked whenever there is an event on any signal in this list.

d. Mixed Style of Modeling

It is possible to mix the three modeling styles that we have seen so far in a single architecture body. That is, within an architecture body, we could use component instantiation statements (that represent structure), concurrent signal assignment statements (that represent dataflow), and process statements (that represent behavior). Here is an example of a mixed style model for a one-bit full-adder shown in Fig. 2.7.

entity FULL_ADDER is port (A, B, CIN: in BIT; SUM, COUT: out BIT); end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is component XOR2 port (A, B: in BIT; Z: out BIT); end component; signal S1: BIT; begin X1: XOR2 port map (A, B, S1 ); - structure. process (A, B, CIN) - behavior. variable T1, T2, T3: BIT; begin T1 :=A and B; T2 := B and CIN; T3:=A and CIN; COUT <= T1 or T2 or T3;

end process; SUM <= S1 xor CIN; - dataflow. end FA_M!XED;

The full-adder is represented using one component instantiation statement, one process statement and one concurrent signal assignment statement. All of these statements are concurrent statements, and therefore, their order of appearance within the architecture body is not important. Note that a process statement itself is a concurrent statement; however, statements within a process statement are always executed sequentially. SI is a signal locally declared within the architecture body and is used to pass the value from the output of the component XI to the expression for signal SUM.

3. Model analysis:

Once an entity is described in VHDL, it can be validated using an analyzer and a simulator that are part of a VHDL system. The first step in the validation process is analysis. The analyzer takes a file that contains one or more design units (remember that a design unit is an entity declaration, an architecture body, a configuration declaration, a package declaration or a package body) and compiles them into an intermediate form. The format of this compiled intermediate representation is not defined by the language. During compilation, the analyzer validates the syntax and performs static semantic checks. The generated intermediate form is stored in a specific design library, that has been designated as the working library.

4. Simulation:

Once the model description is successfully compiled into one or more design libraries, the next step in the validation process is simulation. For a hierarchical entity to be simulated, all of its lowest level components must be described at the behavioral level.

Simulation commences by advancing time to that of the next event. Values that are scheduled to be assigned to signals at this time are assigned. Each process that has a signal in its sensitivity list whose value just changed, is executed until it suspends. Simulation stops when a user-specified time limit is reached.

Basic Language Elements:

Identifiers:

An identifier in VHDL is composed of a sequence of one or more characters. A legal character is an upper-case letter (A... Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) or the underscore (_ ) character. The first character in an identifier must be a letter and the last character may not be an underscore. Lower-case and upper-case letters are considered to be identical when used in

an identifier; as an example. Count, COUNT, and CouNT, all refer to the same identifier. Also,-two underscore characters cannot appear consecutively.

Data objects

A data object holds a value of a specified type. It is created by means of an object declaration. An example is

Variable COUNT: INTEGER;This result in the creation of a data object called COUNT which can hold integer values.

Every data object belongs to one of the following three classes:

1. Constant: An object of constant cla^s can hold a single value of a given type. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation. 2. Variable: An object of variable class can also hold a single value of a given type. However in this case, different values can be assigned to the object at different times using a variable assignment statement. 3. Signal: An object belonging to the signal class has a past history of values, a current value, and a set of future values. Future values can be assigned to a signal object using a signal assignment statement.

Data Types

All the possible types that can exist in the language can be categorized into the following four major categories:

1.Scalar types: Values belonging to these types appear in a sequential order. E.g. Integer, floating point.2. Composite types: These are composed of elements of a single type (an array type) or elements of different types (a record type). 3. Access types: These provide access to objects of a given type (via pointers). 4. File types: These provides access to objects that contain a sequence of values of a given type

Operators

The predefined operators in the language are classified into the following five categories:a. Logical operators b. Relational operators c. Adding operators d. Multiplying oper ators e. Miscellaneous operators

a. Logical operators

The six logical operators are AND, OR, NAND, NOR, XOR, NOT

These operators are defined for the predefined types BIT and BOOLEAN. They are also defined for one-dimensional arrays of BIT and BOOLEAN. During evaluation, bit values '0' and 1' are treated as FALSE and TRUE values of the BOOLEAN type, respectively. The result of a logical operation has the same type as its operands.

b. Relational operators

These are =, /=, <, <=, >, >=

The result types for all relational operations is always BOOLEAN. The = (equality) and the /= (inequality) operators are permitted on any type except file types. The remaining four relational operators are permitted on any scalar type (e.g., integer or enumerated types) or discrete array type (i.e., arrays in which element values belong to a discrete type).

c. Adding operators

These are +, -, &

The operands for the + (addition) and - (subtraction) operators must be of the same numeric type with the result being of the same numeric type. The addition and subtraction operators may also be used as unary operators, in which case, the operand and the result type must be the same.

c. Multiplying Operators

These are *, /, mod, rem

The * (multiplication) and / (division) operators are predefined for both operands being of the same integer or floating point type. The result is also of the same type. The multiplication operator is also defined for the case when one of the operands is of a physical type and the second operand is of integer or real type. The result is of physical type. For the division operator, division of an object of a physical type by either an integer or a real type object is allowed and the result type is of the physical type. Division of an object of a physical type by another object of the same physical type is also defined and it yields an integer value as a result. The rem (remainder) and mod (modulus) operators operate on operands of integer types and the result is also of the same type. The result of a rem operation has the sign of its first operand and is defined as A rem B = A - ( A / B ) * B The result of a mod operator has the sign of the second operand and is defined as A mod B = A – B * N -For some integer N.

d. Miscellaneous Operators

The miscellaneous operators are abs, ** The abs (absolute) operator is defined for any numeric type. The ** (exponentiation) operator is defined for the left operand to be of integer or floating point type and the right operand (i.e., the exponent) to be of integer type only. The not logical operator has the same precedence as the above two operators.

Various statements used in VHDL:

Behavioral Modeling:

Process statement:

A process statement contains sequential statements that describe the functionality of a portion of an entity in sequential terms. The syntax of a process statement is [ process-label: ] process [ ( sensitivity-list ) ] [process-item-declarations] begin sequential-statements;

end process [ process-label];

A set of signals that the process is sensitive to is defined by the sensitivity list. In other words, each time an event occurs on any of the signals in the sensitivity list, the sequential statements within the process are executed in a sequential order, that is, in the order in which they appear. The process then suspends after executing the last sequential statement and waits for another event to occur on a signal in the sensitivity list. Items declared in the item declarations part are available for use only within the process.

Variable Assignment Statement:

Variables can be declared and used inside a process statement. A variable is assigned a value using the variable assignment statement that typically has the form variable-object := expression; The expression is evaluated when the statement is executed and the computed value is assigned to the variable object instantaneously, that is, at the current simulation time.

Signal Assignment Statement:

Signals are assigned values using a signal assignment statement The simplest form of a signal assignment statement is signal-object <= expression [ after delay-value ];

A signal assignment statement can appear within a process or outside of a process. If it occurs outside of a process, it is considered to be a concurrent signal assignment statement. When a signal assignment statement appears within a process, it is considered to be a sequential signal assignment statement and is executed in sequence with respect to the other sequential statements that appear within that process.

Sequential statements

Wait Statement:

As we saw earlier, a process may be suspended by means of a sensitivity list. That is, when a process has a sensitivity list, it always suspends after executing the last sequential statement in the process. The wait statement provides an alternate way to suspend the execution of a process.

Some examples of wait statements are wait on A, B, C; -- statement 1 wait until (A = B); -- statement 2 wait for 10ns; -- statement 3 wait on CLOCK for 20ns; -- statement 4 wait until (SUM > 100) for 50 ms; -- statement 5

If Statement:

An if statement selects a sequence of statements for execution based on the value of a condition. The general form of an if statement is

if boolean-expressionthen sequential-statements [ elsif boolean-expression then -- elsif clause; if stmt can have 0 or sequential-statements ] -- more elsif clauses. [ else -- else clause. sequential-statements ] end if;

The if statement is executed by checking each condition sequentially until the first true condition is found; then, the set of sequential statements associated with this condition is executed.

Case Statement:

The format of a case statement is case expression is when choices => sequential-statements -- branch #1 when choices => sequential-statements -- branch #2 -- Can have any number of branches. [when others => sequential-statements] -- last branch end case; The case statement selects one of the branches for execution based on the value of the expression.

Null Statement:

The statement null; is a sequential statement that does not cause any action to take place and execution continues with the next statement. One example of this statement's use is in an if statement or in a case statement where for certain conditions, it may be useful or necessary to explicitly specify that no action needs to be performed.Loop Statement:

A loop statement is used to iterate through a set of sequential statements. The syntax of a loop statement is [ loop-label : ] iteration-scheme loop sequential-statements end loop [ loop-label ] ;

Exit Statement:

The exit statement is a sequential statement that can be used only inside a loop. It causes execution to jump out of the innermost loop or the loop whose label is specified. The syntax for an exit statement is exit [ loop-label] [ when condition ]: If no loop label is specified, the innermost loop is exited. If the when clause is used, the specified loop is exited only if the given condition is true, otherwise, execution continues with the next statement.

Delays:

Delta Delay

A delta delay is a very small delay (infinitesimally small). It does not correspond to any real delay and actual simulation time does not advance. This delay models hardware where a minimal amount of time is needed for a change to occur, for example, in performing zero delay simulation. Delta delay allows for ordering of events that occur at the same simulation time during a simulation. Each unit of simulation time can be considered to be composed of an infinite number of delta delays. Therefore, an event always occurs at a real simulation time plus an integral multiple of delta delays. For example, events can occur at 15 ns, 15 ns+IA, 15 ns+2A, 15 ns+3A, 22 ns, 22 ns+A, 27 ns, 27 ns+A, and so on.

Inertial Delay

Inertial delay models the delays often found in switching circuits. It represents the time for which an input value must be stable before the value is allowed to propagate to the output. In addition, the value appears at the output after the specified delay. If the input is not stable for the specified time, no output change occurs. When used with signal assignments, the input value is represented by the value of the expression on the right-hand-side and the output is represented by the target signal.

Transport Delay

Transport delay models the delays in hardware that do not exhibit any inertial delay. This delay represents pure propagation delay, that is, any changes on an input is transported to the output, no matter how small, after the specified delay. To use a transport delay model, the keyword transport must be used in a signal assignment statement. Figure 4.4 shows an example of a noninverting buffer using a transport delay of 10 ns.

Dataflow Modeling

Concurrent Signal Assignment Statement

One of the primary mechanisms for modeling the dataflow behavior of an entity is by using the concurrent signal assignment statement. An example of a dataflow model for a 2-input or gate, shown in Fig. 5.1, follows.

entity OR2 is port (signal A, B: in BIT; signal Z: out BIT); end OR2; architecture OR2 of OR2 is begin Z <= A or B after 9 ns; end OR2;

The architecture body contains a single concurrent signal assignment statement that represents the dataflow of the or gate. The semantic interpretation of this statement is that whenever there is an event (a change of value) on either signal A or B (A and B are signals in the expression for Z), the expression on the right is evaluated and its value is scheduled to appear on signal Z after a delay of 9 ns. The signals in the expression, A and B, form the "sensitivity list" for the signal assignment statement.

Concurrent versus Sequential Signal Assignment

Earlier, we saw that signal assignment statements can also appear within the body of a process statement. Such statements are called sequential signal assignment statements, while signal assignment statements that appear outside of a process are called concurrent signal assignment statements. Concurrent signal assignment statements are event triggered, that is, they are executed whenever there is an event on a signal that appears in its expression, while sequential signal assignment statements are not event triggered and are executed in sequence in relation to the other sequential statements that appear within the process. To further understand the

difference between these two kinds of signal assignment statements, consider the following two architecture bodies.

architecture SEQ_SIG_ASG of FRAGMENT1 is - A, B and Z are signals. begin process (B) begin -- Following are sequential signal assignment statements: A<=B; Z<=A; end process; end; architecture CON_SIG_ASG of FRAGMENT2 is begin -- Following are concurrent signal assignment statements: A<=B; Z<=A; end;

In architecture SEQ_SIG_ASG, the two signal assignments are sequential signal assignments. Therefore, whenever signal B has an event, say at time T, the first signal assignment statement is executed and then the second signal assignment statement is executed, both in zero time. However, signal A is scheduled to get its new value of B only at time T+Δ (the delta delay is implicit), and Z is scheduled to be assigned the old value of A (not the value of B) at time T+Δ also. In architecture CON_SIG_ASG, the two statements are concurrent signal assignment statements. When an event occurs on signal B, say at time T, signal A gets the value of B after delta delay, that is, at time T+Δ. When simulation time advances to T+Δ, signal A will get its new value and this event on A (assuming there is a change of value on signal A) will trigger the second signal assignment statement that will cause the new value of A to be assigned to Z after another delta delay, that is, at time T+2Δ. The delta delay model is explored in more detail in the next section.

Conditional Signal Assignment Statement

The conditional signal assignment statement selects different values for the target signal based on the specified, possibly different, conditions (it is like an if statement). A typical syntax for this statement is

Target - signal <= [ waveform-elements when condition else ] [ waveform-elements when condition else ] . . . waveform-elements; The semantics of this concurrent statement are as follows. Whenever an event occurs on a signal used either in any of the waveform expressions (recall that a waveform expression is the value expression in a waveform element) or in any of the conditions, the conditional signal assignment

statement is executed by evaluating the conditions one at a time. For the first true condition found, the corresponding value (or values) of the waveform is scheduled to be assigned to the target signal. For example,

process begin if S0 = '0' and S1 = '0' then Z<= IN0 after 10 ns; elsif S0='1'and S1='0' then Z<= IN1 after 10ns; elsif S0='0' and S1 = '1' then

Z<= IN2 after 10 ns; else Z<= INS after 10 ns; end if; wait on IN0, IN1, IN2, IN3, S0, S1; end process;

Selected Signal Assignment Statement The selected signal assignment statement selects different values for a target signal based on the,value of a select expression (it is like a case statement). A typical syntax for this statement is with expression select —This is the select expression.

target-signal <= waveform-elements when choices, waveform-elements when choices, … waveform-elements when choices ;

Here is an example of a selected signal assignment statement. type OP is (ADD, SUB, MUL, DIV); signal OP_CODE: OP; . . . with OP_CODE select Z <= A+B after ADD_PROP_DLY when ADD, A - B after SUB_PROP_DLY when SUB, A * B after MUL_PROP_DLY when MUL, A / B after DIV_PROP_DLY when DIV;

In this example, whenever an event occurs on signals, OP_CODE, A, or B, the statement is executed. Assuming the value of the select expression, OP_CODE, is SUB, the expression "A - B" is computed and its value is scheduled to be assigned to signal Z after SUB_PROP_DLY time.

Structural Modeling

Component Declaration

A component instantiated in a structural description must first be declared using a component declaration. A component declaration declares the name and the interface of a component. The interface specifies the mode and the type of ports. The syntax of a simple form of component declaration is

component component-name port ( list-of-interface-ports ) ; end component;

The component-name may or may not refer to the name of an already ex-isfing entity in a library. If it does not, it must be explicitly bound to an entity; otherwise, the model cannot be simulated. This is done using a configuration.

Component Instantiation

A component instantiation statement defines a subcomponent of the entity in which it appears. It associates the signals in the entity with the ports of that subcomponent. A format of a component instantiation statement is

component-label: component-name port map ( association-list) ',

The component-label can be any legal identifier and can be considered as the name of the instance. The component-name must be the name of a component declared earlier using a component declaration. The association-list associates signals in the entity, called actuals, with the ports of a component, called locals.

VHDL codes for some digital circuits:

1) DATA FLOW CODING STYLE

FULL ADDER

entity fulladder1 is

port(a,b,cin : in std_logic; sum,carry : out std_logic);

end fulladder1;

architecture beh of fulladder1 is

component halfadder is

port(a,b : in std_logic;

sum,carry : out std_logic);

end component;

component orgate is

port(a,b : in std_logic; c : out std_logic);

end component;

signal temp, temp1, temp2 : std_logic;

begin

u1 : halfadder port map

(a=>a,

b=>b,

sum=>temp,

carry=>temp1);

u2 : halfadder port map

(a=>temp,

b=>cin,

sum=>sum,

carry=>temp2);

u3 : orgate port map

(a=>temp2,

b=>temp1,

c=>carry);

end beh;

2) BEHAVIORAL CODING STYLE

HALF ADDER

entity halfadder is

port(a,b : in std_logic; sum,carry : out std_logic);

end halfadder;

architecture beh of halfadder is

begin

process(a,b)

begin

if a='0' and b='0'then

sum<='0';

carry<='0';

elsif a='0' and b='1'then

sum<='1';

carry<='0';

else

sum<='0';

carry<='1';

end if;

end process;

end beh;

3) STRUCTURAL CODING STYLE

FULLADDER

entity fladder is

port(a,b,cin : in std_logic; sum,carry : out std_logic);

end fladder;

architecture beh of fladder is

component hfadder is

port(a,b : in std_logic; sum,carry : out std_logic);

end component;

component orgate is

port(a,b : in std_logic; q : out std_logic);

end component;

signal temp,temp1,temp2 : std_logic;

begin

u1: hfadder port map(a=>b,b=>b,sum=>temp,carry=>temp1);

u2: hfadder port map(a=>temp,b=>cin,sum=>sum,carry=>temp2);

u3: orgate port map(a=>temp2,b=>temp1,q=>carry);

end beh;

Chapter 4

Tool description: TANNER EDA

Tanner is an EDA (Electronic design automation) tool, which is used to design and produce electronic systems ranging from printed circuit boards (PCBs) to integrated circuits.

User Interface:S-Edit’s user interface consists of the Title Bar, Menu Bar, Work Area, Status Bar, & 5 toolbars.

Getting Started:

Launch S-Edit; double-click on the S-Edit icon.

Browsing symbols

Designing the circuit using the components browsed

Enter the T-spice mode

Inserting the commands

Run simulation

Generation of waveform in W-Edit

References

Books:

VHDL programming by examples- Douglas L. Perry

Introduction to HDL based VLSI design- Chandra Shekhar

Principles of CMOS VLSI Design,- Neil H. E. Weste and David Harris

Websites:

http://www.wikipedia.org/ http://www.tannereda.com/

http://www.aw-bc.com/weste/

http://www.aw-bc.com/weste/

vector.weebly.comvector.weebly.com/uploads/1/3/1/0/1310781/final_report.docx · web viewchapter 1....

Documents