Design of Low Voltage, Low Power, Wide Input Range Fully CMOS Analog

Multiplier

Ali Rezaeia,b Mehdi JafariPanaha,c

a Department of Electrical Eng., Tafresh University, Tehran Ave., Tafresh, IRAN

b Corresponding author, Email: En.Rezaei1364@gmail.com

c Email: Mj@tafreshu.ac.ir

Abstract ̶ In this paper, a four quadrant voltage mode analog multiplier, which is an important component in many applications, using CMOS transistors biased in the triode and saturation region is presented. The major improvements of the proposed multiplier are reducing the power consumption, increasing the input range and increasing the frequency bandwidth. The fully CMOS design of the multiplier makes it compatible with digital technology. Simulation results with Hspice for 0.18μm CMOS process show that this new multiplier structure has very low power consumption, low THD and wide frequency range, which make it suitable for varieties of analog applications.

Keywords: CMOS Multiplier, Low voltage circuits, Low power design, Analog IC design

Introduction

Analog multipliers are the major building blocks in the signal processing circuits. Multipliers are used in the modulators, PLL’s, AGC’s, detectors, frequency multipliers, neural networks, adaptive filters, fuzzy systems and other applications.

The function of analog multiplier is that two signals x and y is applied to the inputs, and the output is a linear product of these signals, Z=A0 XY . A0 is a constant value and it is called the multiplier gain and the maximum value of A0 is equal to 1/ Xmax or 1/Y max[1].

The first solid state multiplier was presented by Gilbert [1] and then a variety of multipliers with different characteristics have been presented [2-7]. Due to advances in digital technology in modern electronics, analog circuits are required to be implemented in the same standard CMOS process for low-cost fabrication.

The multipliers can be implemented in two modes, the voltage mode and the current mode. Each one of these modes can be realized with CMOS transistors which are biased in the saturation, triode or sub-threshold region. In [4] multipliers are divided into eight categories, depending on the signals application methods, CMOS transistor operation region and the nonlinear cancelation method. In this division, according to the transistor operation region, the input signals can be applied to drain, source, gate and substrate. Some of categories presented in this reference are not practical and also some of them have poor linearity, high power consumption and low bandwidth, which make them unsuitable for some applications. In [3] a current mode multiplier is obtained for high speed applications. This structure needs a circuit to produce 2x which should be very precise and increases the number of transistors and power consumption. So it is not suitable for low voltage and low power applications. In [5] a voltage mode

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multiplier is offered for low voltage applications, in which a common voltage is required for biasing the transistors for the input y. Furthermore, to convert the output current to the voltage, resistor is used which is not suitable for fully CMOS implementation. In [6] a current mode multiplier is presented in which the transistors operate in weak inversion region. It is proposed for low voltage and low power applications. This structure has very low bandwidth about a few tens of KHz, which is not suitable for high frequency applications.

Achieving a lower level of nonlinear error in CMOS technology is difficult compared to BJT counterpart because of the different (I-V) relationship of them. Hence, traditional BJT structures cannot be used easily for CMOS multipliers. Therefore, various linearization techniques have been used to compensate for the nonlinearity of the square-law device, such as floating gate[10], signal attenuator[11], variable Transconductance[12], using differential pair[5] and using bipolar characteristic of the CMOS transistors[6]. Differential structure, because of common signals cancellation property, is frequently used to cancel the nonlinear term in the multiplier circuits [1-7].

Multiplier Circuit Analysis

Fig. 1 shows the block diagram of the proposed four-quadrant multiplier, consisting of single-quadrant multiplier blocks and square-law blocks. In [4], for multiplier implementation, only single-quadrant multiplier or square law multiplier have been used, whereas Fig. 1 that consist of single-quadrant blocks and square law blocks simultaneously.

According to the block diagram shown in Fig. 1, one can write the following relationships:

(1) (2) Where K is a constant, X and Y are the input signals and V1, V2 are the offset terms which

have the same values. The differential output signal Zd=Z1−Z2 becomes:

(3)

Fig. 1 Block diagram of the multiplier

A. Basic circuit

Fig. 2 illustrates the basic structure of the purposed multiplier shown schematically in Fig. 1. For implementation of a multiplier using CMOS transistors, it is possible to use V GS

2 in the saturation region and V GS ×V DS or V DS2 in

the triode region [4]. In the basic structure of Fig. 2, since CMOS transistors operate in both saturation and triode regions, for multiplier implementation, the combination of V GS

2 and V GS ×V DS terms have been used.

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Fig.2 Multiplier basic sub-circuit

In this paper, capital letters with capital subscripts are used for DC bias values, and lower case letters with lower subscripts for ac signals and capital letters with lower case subscripts for instantaneous values are used, respectively.

Having neglected the short channel effect and channel length modulation, the drain current of CMOS transistor in the triode and saturation region are given with equations (4) and (5), respectively [9].

I d=12

K N /P(V gs−V TN /P)2 (4a)

V gs>V TN ,V ds>V gs−V TN∨V dg>−V TN (NMOS) (4b)V gs<V TP ,V gd>V TP∨V dg<¿V TP∨¿ (PMOS) (4c)I d=

12

KN /P

[2 (V gs−V TN /P ) V ds−V ds2 ] (5a)

V gs>V TN ,V ds<V gs−V TN∨V dg←V TN (NMOS) (5b)V gs<V TP ,V dg<V TP∨V dg>¿V TP∨¿ (PMOS) (5c) Where, K N /P=μN /PCox W /L is the transconductance parameter, W is transistor width, L is transistor length, μn /p is carrier mobility, Cox is the gate capacitance per unit area, and V TN / P is the threshold voltage of the NMOS and PMOS transistors, respectively.

In this circuit, when the input signals are zero, all transistors are in the triode region and when the non-zero inputs are applied, transistors M1 and M4 are in the saturation region and transistor M2 and M3 are in the triode region or wise versa. Assuming that transistors M1 and M4 are in the saturation region and transistor M2 and M3 are in the triode region we have:

I d1=12

K P1 [ ( y+x+V GS−V TP)2 ] (6a)I d2=

12

K P2 [2 ( y−x+V GS−V TP) ( y−V 2 )−( y−V 2 )2 ] (6b)3

I d3=12

K P 3 [2 (− y−x+V GS−V TP ) (− y−V 1 )−(− y−V 1 )2 ] (6c)I d 4=

12

KP 4 [ (− y+x+V GS−V TP )2 ] (6d)Where V GS is the bias voltage due to the flow of the bias current I B/2 in each transistor, V TP is threshold voltage, x and y are input signals and V 1, V 2 are constant DC voltages. In the Fig. 2, the output currents I o 1 and I o 2 can be written as:

I o 1=I d 1+ I d 3 (7)I o2=I d 2+ I d 4 (8)Currents I o 1 and I o 2 have the signal components, io, and DC components, I B, i.e. (I o=io+ I B). The output current is defined as the difference between I o 1 and I o 2. Using equations (6), (7), (8) and assume equal KP, yields:

I o1−I o 2=12

KP [8 xy+2 V TP (V 1−V 2)+2 (V 22−V 1

2 )+2 x (V 1−V 2)] (9)V 1, V 2 will be obtained in equations (10) and (11), respectively.

B. Analysis of the proposed multiplier circuit

The proposed multiplier circuit is shown in Fig. 3. In this circuit, the transistor M 1 to M4 form the basic circuit of Fig. 2, transistors M5 to M9 are current mirror source which provide the bias current IB, and M8, M9 are in the triode region and transistors M10 to M13 are used as linear resistors which convert the output currents to the output voltages.

Considering equations (6) to (8) for the circuit of Fig. 3, the differential output current is the same as equation (9).

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Fig. 3 Proposed multiplier circuit

According to the circuit of Fig. 3, we have:

V 1=V GS 12=V DD−V GS 10 (10)V 2=V GS13=V DD−V GS 11 (11)Since the circuit is perfectly symmetrical and assuming transistor matching, then V GS 10=V GS 11 and according to equations (10) and (11), V 1=V 2 . By substituting in equation (9), the DC values are removed and we have only the signal values:

io=I o 1−I o2=4 K P . x . y (12)C. Differential active linear resistance

Using active resistors instead of passive resistors causes fully CMOS implementation of the circuit with lower area occupation on the chip. In the circuit of Fig. 3, transistors M10 to M13 are used as linear resistors for converting the output current to the voltage. For convenience, this part of the circuit is shown in Fig. 4.

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Fig. 4 Differential active linear resistor Circuit

In the circuit shown in Fig. 4, all four transistors are in the saturation region. By writing KCL at the output node, V o1, we have:

I o 1+ I D10−I D 12=0 (13)Where:

I D10=12

K N(V DD−V o1−V TN 10)2

(14)I D12=

12

KN(V o1−V TN 12)

2 (15)By combining equations (13), (14) and (15), the output voltage, V o 1, can be found in terms of the output current I o 1 (I o 1=io 1+ I B), as follows:

V o 1=io 1+ IB

K N (V DD−V TN 12−V TN 10 )+

V DD+V TN 12−V TN10

2(16)

Similarly:

V o2=io 2+ I B

K N (V DD−V TN 13−V TN11 )+

V DD+V TN 13−V TN11

2(17)

Considering equations (16) and (17) and since V TN 10=V TN11 and V TN 12=V TN 13, we have:

V o 1−V o2=I o 1−I o 2

K N (V DD−V TN 11−V TN 13 )(18)

From equation (18), the differential output resistor can be obtained as follows:

Rdiff =V o 1−V o 2

I o 1−I o2= 1

KN (V DD−V TN11−V TN 13)(19)

By substituting equation (12) into equation (18), the differential output voltage is:

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vo=V o1−V o 2=4.K P . x . y

K N (V DD−V TN11−V TN13 )(20)

D. Inspection of operation region of transistors

Since in the proposed multiplier, the wide input range with comparable linearity is obtained by using CMOS transistors biased in the triode and saturation region complementary, careful inspection of operation region of transistors are presented in detail.

a) Transistors M11-M13, M10 - M12

Operation of transistors M11-M13 is completely similar to transistors M10 - M12. For proper circuit functionality, all four transistors, which are used as active load, must be in the saturation region. Equation (4b) gives the conditions for NMOS transistors to be in the saturation regions.

According to Fig. 3, the gate-drain voltage of the active load transistors are zero and noticing that the threshold voltage of an NMOS is positive, so equation V DG>−V TN is always established and if equation V GS>V TN is achieved the transistors will be in the saturated region.

Equations (21) to (24) can be written, by assumption that transistors M11-M13, M10- M12 operate in the saturation region.

I D10+ I o1−I D 12=0 (21) I D10=

12

KN(V GS 10−V TN 10)

2 (22) I D12=

12

K N(V GS12−V TN 12)2 (23)

V GS 12=V DD−V GS 10 (24)Considering the DC values, I o 1 will be equal to I B and by combining equations (21) to (24) the gate-source voltages, V GS 10 and V GS 12, are obtained as follows:

V GS10=V DD+V TN 10−V TN 12

2−

I B

K N (V DD−V TN 12−V TN 10 )(25)

V GS12=V DD+V TN 12−V TN 10

2+

IB

KN (V DD−V TN 12−V TN 10 )(26)

According to equations (25), (26), regarding to the values of the technology parameters and the bias current, IB, it can be concluded that:

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V GS10>V TN 10 (27)V GS 12>V TN 12 (28) Hence, transistors M11-M13, M10- M12 are in the saturation region.

b) Transistors M1, M2, M3 & M4

In circuit of Fig 3., when the input signals are zero, transistors M1, M2, M3 and M4 are in the triode region. Since the circuit is symmetrical and assuming matching between transistors, when the non-zero inputs are applied, transistors M1 and M4 are in the saturation region and M2 and M3 are in the triode region or wise versa. Hence, we just obtain the operation region of M1 and M2 for non-zero inputs.

c) Condition of operating M1 in the triode region

In order to M1 to be in the triode region, equation (5c) must be satisfied. According to Fig. 3, the body effect are not canceled in M1, M2, M3 and M4; V SB ≠ 0, and V TP can be obtained from equation (29)[8].

V TP=¿V TP0+γ (√2|ϕ f|+|V sb|−√2|ϕf|)∨¿ ,V sb=|y−V DD|(29)where V TP 0 is the threshold voltage when

V SB=0, γ is the body effect coefficient, and ϕ f is the Fermi potential.As it can be seen in equation (29), the input y signal affects V TP and hence affects equation (5c). Using equation (5c) we have:

V D−V G>¿V TP∨ ,V G=x ,V D=V GS 12(30)

By combining equations (29) and (30) we obtaine:

x<V GS12−¿V TP0+γ (√2|ϕf|+|y−V DD|−√2|ϕ f|)∨(31)

If y has its minimum value, then V TP will be maximum and if the equation (31) is satisfied, then M1 would be in the triode region. If y is has the maximum value, V TP will be minimum and if the following equation (32) is satisfied, then M1 will be in the saturation region.

x>V GS 12−¿V TP0+γ (√2|ϕf|+|y−V DD|−√2|ϕf|)∨¿ (32)It should be noted that when the gate voltage of M1 has the maximum value, the gate voltage of M2 is minimum and vice versa. Therefore, it can be concluded that when M1 operates in the saturation region, M2 is in the triode region and when M1 operates in the triode region M2 is in the saturation region. There are the same conditions for M3 and M4. Hence, according to the input signals, when M1 and M4 are in the triode region, M2 and M3 are in the saturation region and vice versa. In all cases, equation (12) represents the multiplication of two signals.

E. Input Range

If x and y have their maximum values, according to the equation (32), M1 and M4 will be in the saturation region and saturation of the transistors determines the maximum input range.

We have:

|xmax|+|ymax|+V GS<V TP (33)8

According to equation (4a) VGS of the transistors M1, M2, M3 and M4 in saturation region can be obtained as follows.

V GS=−√ IB

K P+V TP (34)

Substituting equation (34) into equation (33) and assuming that both inputs x, y have equal swings, then we have:

|V i , max|<0.5√ IB

K P(35)

As it can be seen from equation (35), the maximum input range depends on IB and the technology parameters.

F. Power Consumption

Since PMOS transistors need lower drain current in comparison with NMOS transistors, they are good choices for input stage operated in the saturation or triode regions in order to decrease the power consumption [2]. In [2, 5, 6, 7], transistors biasing requires extra circuits which causes an increase in the power consumption, but in the proposed multiplier circuit, for biasing, only the current source have been used that is one of major reasons to reduce the power consumption.

The power consumption for the circuit of Fig. 3 is:PT=V B IB+V DD I T (36)Where, V DD is supply voltage, I B is the value of the current source and V B is the voltage across this current source,I T is the total current and can be obtained as follows:

I T=I D5+ ID6+ I D7+ I D10+ I D11 (37) In the circuit of Fig. 3, we have:

I D5=I D6=I D7=I B , ID 10=I D11 (38)

I D10=12

K N( V DD+V TN 10−V TN 12

2−

I B

KN (V DD−V TN 12−V TN 10 )– V TN 10)

2

(39)

V B=V DD−V SG5=V DD−√ 2 I B

K P−¿V TP 5∨(40)

According to equations (36) to (40), the power consumption is obtained as follows:

PT=¿

It should be noted from equation (41) that increasing IB will increase the power consumption.

G. Frequency Response

Although the precise calculation of frequency responses is most often left to computer simulations, there is much insight that can be obtained by finding the dominant frequency effects in integrated circuits [9]. In the presented circuit of Fig. 3, because of the simple method of applying the input signals (the inputs are applied to the gate and source directly) and considering short channel length for the transistors, the proposed multiplier has relatively high

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cut of frequency. The active resistors used in Fig. 3 have the maximum effect on the frequency response characteristic. For each one of the outputs, the dominant pole frequency can be

considered as follows:

ω p 1,2=1

Ro 1,2 .Co 1,2(42)

For the output node, V o 1, we have:

Ro 1=1

gm10+gm12, Co1=C gs10+Cgs 12(43)

According to equations (42) and (43):

ω p 1=gm10+gm12

Cgs 10+Cgs 12(44 )

The dominant pole frequency of V o2 is actually equal to that of V o1. Since small area transistors are used, the gate-source capacitors are small and hence according to (44) it is expected that the cut-off frequency will be large.

Simulation Results

The designed multiplier circuit of Fig. 3 was simulated using Hspice for 0.18µm CMOS process with main parameters of V TN 0=0.486 v, V TP 0=−0.46 v, IB=5µA and V DD=1.2 v .Transistors sizes are shown in Tab. 1; these sizes are selected in order to optimize power consumption, input range and bandwidth.

In section 3, the analysis of the maximum input range has been done. According to (35), the maximum input range is a function of the bias current, IB, and this current has selected regarding to the trade-offs between the maximum input range, power consumption and bandwidth.

(Fig. 5a) shows simulated DC transfer characteristics of the proposed multiplier, when x was swept continuously from -0.3v to 0.3v while y was varied from -0.3v to 0.3v with 0.1v step size. It can be seen that the maximum input range is %50 of the power supply voltage and the multiplier is four quadrants. Since in the proposed multiplier circuit of Fig. 3, I B=5µA and ℘/Lp=0.3 µm /0.6 µm, simulation result validates the theoretical calculations offered in (35). The derivative of the transfer characteristic is show in (Fig. 5b) which illustrates the e rror performances of the DC transfer characteristic. In section 4, the analysis of the power consumption has been carried out which resulted to equation (41). Simulation results shows a power consumption about 33µw, which is in agreement with the theoretical calculations.

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TAB. 1 TRANSISTORS DIMENSOIN

TRANSISTOR W(µm) L(µm)

M1,M2,M3,M4 0.3 0.6

M5,M6,M7,M8,M9 15 1

M10,M11,M12,M13 0. 22 1

(a) (b)

Fig. 5 (a) DC transfer characteristic (b) Error performances of the DC characteristic

In order to demonstrate the application of the proposed multiplier in a modulator circuit, transient response simulation for the input signals y=0.3 v p− p−1GHz ,∧x=0.3 v p−p−100 MHz is shown in (Fig. 6a). To illustrate the nonlinearity characteristics of the modulator circuit, the frequency spectrum of the output waveform is shown in (Fig. 6b).

(a) (b)

Fig. 6 (a) Output transient responses (b) Frequency spectrum of the waveform in Fig. 6

Frequency response simulation result of the proposed circuit is shown in Fig. 7 with the input signal x=0.3 v. As it can be seen, the circuit has high bandwidth of 3.7 GHz which makes the circuit suitable for high frequency applications.By increasing the amplitude of the input signals, the non-linear effects of the CMOS transistors will be increased. This causes an increase in the THD and non-linear effect in the DC characteristic. There is a direct relationship between the THD and the multiplier circuit linearity, when x=0.3 sin (2π 105 t)v and y=0.3 v are applied to the inputs, the THD is equal to 0.69% and for inputs y=0.3 sin (2π 105 t)v and x=0.3 v, the THD of 0.74% is achieved. Fig. 8 shows the THD values for various DC inputs x and y.

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Fig. 7 Frequency response of the proposed multiplier

Fig. 8 THD as a function of the input signal x & y

Tab. 2, represents a performance comparison between the proposed circuit with references [2, 5,7]; which shows that the proposed multiplier has better characteristics.

Conclusion

A four quadrant analog multiplier circuit using CMOS transistors biased in the triode and saturation region is designed and simulated. The proposed multiplier offers reduced power consumption, increased input range and increased bandwidth, which makes it suitable for high frequency, low power applications. The fully CMOS design

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TAB. 2 COMPARISON OF THE PROPOSED CIRCUIT WITH [2,5,7]

This work [2] [5] [7] V DD 1.2 1.5 1.2 1.5

Power(μw) 33 32 113 290

THD (%) 0.74 --- 1.1 ---

Bandwidth(GHZ ) 3.7 1.98 1

0.1

of the multiplier is an advantage for low cost implementation using standard digital CMOS technology. The proposed circuit has been simulated with Hspice for 0.18μm CMOS process. The power supply voltage of circuit is 1.2v. The simulation results shown that the THD is less than 0.74% for input frequency of 100KHz, -3dB bandwidth is 3.7GHz and the power consumption is about 33μw.

References

[1] Gilbert, B.: ‘A precision four-quadrant multiplier with Subnanosecond response’, IEEE J. Solid-State Circuits, Dec. 1968, SC-3, pp. 353–365 [2] Chen, C. and Li, Z.: ‘A Low-power CMOS Analog multiplier’, IEEE Trans. Circuit Syst., Feb. 2006, 52, (9), pp. 100-104[3] Naderi, A., Khoei, A. and Hadidi, Kh.: ‘High Speed Low Power Four-Quadrant CMOS Current-Mode Multiplier’. 14th IEEE conf. Circuit Syst., 2007, pp. 1308-1311[4] Han, G. and Sanchez-Sinencio, E.: ‘CMOS transconductance multipliers: A tutorial’, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Dec. 1998, 45, (12), pp. 1550–1563[5] Ebrahimi, A. and Miar-Naimi, H.: ‘A 1.2V Single Supply and Low Power, CMOS Four-Quadrant Analog Multiplier’. Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, Oct. 2010, pp. 1-5 [6] Valle, M. and Diotalevi, F.: ‘A Novel Current-Mode Very Low Power Analog CMOS Four Quadrant Multiplier’. 2005 ESSCIRC Solid-State Circuits Conf., 2005, pp. 495-498 [7] Sawigun, C. and Mahattanakul, j.: ‘A 1.5V, Wide-Input Range, High-Bandwidth, CMOS Four-Quadrant Analog Multiplier’. 2008 IEEE conf. Circuit Syst., 2008, pp. 2318-2321 [8] Razavi, B.: ‘Design of Analog CMOS Integrated Circuits’ (MacGraw-Hill, New York, 2001) [9] Johns, D. A. and Martin, K.: ‘Analog Integrated Circuits Design’ (Wiley, New York, 1997)[10] Garimella, S. R. S., Ramirez-Angulo, J., Lopez-Martin, A. and Carvajal, R. G.: ‘Design of Highly Linear Multipliers using Floating Gate Transistors and/or Source Degeneration Resistor’. IEEE Int. Symp. on Circuits and Syst., 2008, pp.1492-1495[11] Qin, S. and Geiger, R.: ‘A +/-5-V CMOS Analog Multiplier’, IEEE J.of Solid-State Circuits, SC-22, (6), Dec. 1987, pp. 1143-1146[12] Song, H. and Kim, C.: ‘An MOS Four-Quadrant Analog Multiplier Using Simple Tow-Input Squaring Circuit with Source Followers’, IEEE J. of Solid-State Circuits, 25, (3), June 1990, pp. 841-845

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