virtual memory - drona.csa.iisc.ac.indeepakd/verification-workshop-2016/... · pdpt pd pt all three...
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Virtual Memory HABEEB P
Virtual Memory
Memory management technique that is implemented
using both hardware and software.
It maps memory addresses used by a program, called
virtual addresses, into physical addresses in
computer memory.
Address translation hardware in the system, often
referred to as a memory management unit or MMU,
automatically translates virtual addresses to physical
addresses
Paging provides a mechanism to implement virtual
memory.
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Address Translation: An Overview
CPU Physical Memory Paging Unit Segmentation
Unit
Lo
gic
al
Ad
dre
ss
Lin
ea
r A
dd
res
s
Ph
ysi
ca
l A
dd
res
s
Translation Logical to Linear
Translation Linear to Physical
3
Memory in Paging
Virtual
Address Space
Physical
Address Space
Page Table
LA to PA Mapping
VA
0-4095
PA
4096-8191
0
4095 4096
8191 8192
12287 12288
16383 16384
20479 20480
24575
0
4095 4096
8191 8192
12287 12288
16383
What is the physical address
for virtual address 300?
4096+300
4
Virtual Memory ..
Program Address
Space (4GB) 1GB Physical
Memory
0
…
1
2
Without Virtual Memory With Virtual Memory
0
…
1
2
Program Address
Space (4GB)
1GB Physical
Memory
Program Address = RAM Address Program Address Maps to RAM Address
MAP
Disk Crash
5
Problems with Memory
. What if we don’t have enough memory?
Let suppose a program need 4GB of memory.
Program can access any address in its 32-bit address space.
What if we don’t have 4GB of memory?
1GB Physical
Memory
Crash if try to
access more
than 1 GB
Program Address
Space (4GB) 0x00000000
0xFFFF FFFF
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2. Holes in address space
Problems with Memory ..
32 bit physical
Address Space
(4GB)
0x00000000
0xFFFF FFFF
Program1(1GB) Program2(2GB) Program3(2GB)
Program 1 and Program 2 fit in the
memory, and use 1+2 =3GB.
Quit Program 1
Can`t run program3 even though we have
enough Memory
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3. How do we keep programs secure?
Each program can access any address in RAM.
Problems with Memory ..
0x00000000
0xFFFF FFFF
32 bit physical
Address Space
(4GB)
Program1(1GB)
Program2(2GB)
1. Program 1 store
bank balance at
2048
2. Program 2 store
game score at 2048
They corrupt or crash
each other
4000 40000
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The memory management facilities of the IA-32 architecture are divided into two parts
Segmentation Segmentation provides a mechanism of isolating individual
code, data, and stack modules.
Each program divided into segments. Each segment can have different size.
Paging Paging provides a mechanism for implementing a
conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed.
Paging can be used to provide isolation between multiple tasks.
Memory Management Overview 9
When operating in protected mode, some form of
segmentation must be used.
There is no mode bit to disable segmentation.
The use of paging, however, is optional (If CR0.PG = 0,
paging is not used. The logical processor treats all linear
addresses as if they were physical addresses.)
Memory Management Overview.. 10
PAGING
Intel-64 processors support three different paging
modes
32-bit paging (CR0.PG = 1 and CR4.PAE = 0).
PAE paging (CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 0).
IA-32e paging (CR0.PG = 1, CR4.PAE =1, and
IA32_EFER.LME= 1)
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The three paging modes differ with regard to the
following details
Linear-address width.
Physical-address width
Page size
Support for execute-disable access rights.
PAGING.. 12
Properties of Different Paging Modes
PAGING.. 13
Enumeration of Paging Features by CPUID
Software can discover support for different paging
features using the CPUID instruction
PAGING.. 14
32-BIT PAGING
Although 40 bits corresponds to 1 TByte, linear
addresses are limited to 32 bits; at most 4 GBytes of
linear-address space may be accessed at any given
time.
CR3 is used to locate the first paging-structure, the
page directory.
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Linear-Address Translation to a
4-KByte Page using 32-Bit Paging 16
Src: [1]
Linear-Address Translation to a
4-KByte Page using 32-Bit Paging ..
Directory Table Offset
31 22 21 12 11 0
CR3
0 31
0 … 0 CR3 (31:12) LA (31:22) 00
39 32 31 12 11 2 1 0
0 … 0 PDE (31:12) LA (21:12) 00
39 32 31 12 11 2 1 0
PDE Address Calculation PTE Address Calculation
PDE
0 31
Linear Address
PDE Address PTE Address
17
Linear-Address Translation to a
4-KByte Page using 32-Bit Paging ..
Directory Table Offset
31 22 21 12 11 0
PTE
0 31
0 … 0 PTE (31:12) LA (11:0)
39 32 31 12 11 0
Final Physical Address Calculation
Linear Address
Physical Memory
4K
B P
ag
e
18
32-BIT PAGING
A page directory comprises
1024 32-bit entries (PDEs).
If CR4.PSE = and the PDE’s PS flag is 1, the PDE maps a 4-MByte
page
PSE: page-size extensions
If CR4.PSE = or the PDE’s PS flag is 0, a 4-KByte naturally
aligned page table
Page Directory
Page Table
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HIERARCHICAL PAGING STRUCTURES
Paging structures are used to translate linear address
to physical.
PML4
PDPT
PD
PT
All three paging modes translate linear addresses use
hierarchical paging structures.
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For 32 bit Machine with 4KB pages we need
1 Million Page Table Entries ( 32 Bit - 20 bit page offset = 20bit ; 220 = 1M)
Each Page Table entry is about 4 Byte
(20 bit for physical page + Permission bits )
Total 4MB for each program
If we have 100 programs running then, we need 400MB of page tables!!!.
We cant swap page tables out of RAM (because only one level)
Why Hierarchical Paging? 21
Two Level Paging
Why Hierarchical Paging?
0x0004
0x0006
Disk
Disk
0x00AA
----------
First Level
4KB Page (1024 PTEs)
0x0100
0x0106
Disk
Disk
0x00AA
----------
0x0204
0x0206
Disk
Disk
0x00AA
----------
Second Level
4KB Each (1024 PTEs)
0x0304
0x0306
Disk
Disk
0x03AA
----------
0x0004 0x0006
Disk Disk
0x00AA
------
0x0304 0x0306
Disk Disk
0x03AA
---------
-
Physical Memory
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With two level page table, what is the smallest amount of
data need to keep in memory for each program?
4KB+4KB
We always need first level page table so we can find second level
pages.
We need at least one second level page table to start execution of the
program.
If we have 100 programs in memory then, how much
memory needed for page tables?
800KB
Why Hierarchical Paging? 23
Virtual Memory: Solving Problem1
Not enough RAM in the system
Map some of the program`s address space to the disk
When it need, bring to memory.
3
0 1 2
Program Address
Space (4GB) 1GB Physical
Memory
MAP
Disk
Program Loads
Address 0
VM map address
0 to ram1
Program Loads
Address 1
VM map address
1 to ram0
Program Loads
Address 3
VM map address
3 to ram 2
Program Loads
Address 2
Page Fault
Replace Physical
memory frame
with new vale
Update Map
0
2
2 1
3
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Virtual Memory: Solving Problem2
Holes in address space
We can map program`s address space into RAM as we like.
Program2(2GB)
Program3(2GB)
Program Address
Space (4GB)
MAP 2
MAP
Can Map
different virtual
pages to different
physical pages
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Keep Program Secure Two programs map same virtual address to different physical address
Virtual Memory: Solving Problem3
32 bit physical
Address Space
(4GB)
Program1(1GB)
Program2(2GB)
1. Program 1 store
bank balance at
2048
2. Program 2 store
game score at 2048
MAP1
MAP2
4000
40000 Map VA 2048
To
PA Y
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Program Address Space in Linux
32 bit Program
virtual address space (4GB)
Kernel Space
0x FFFF FFFF
0x 0C00 0000
0x 0000 0000
Stack
Libraries
Heap
Data
Text
Random offset
Random offset
Random offset
Each program has its own 32-bit
address space
1GB Upper memory reserved for
kernel
Stack grows down
Heap grows up
Random offset to enhance security
Data: static variables
Text : Program Binary
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Kernel Space
Stack
Libraries
Heap
Data Text
Kernel Space
Stack
Libraries
Heap
Data Text
Program1
Virtual Address Space
Program2
Virtual Address Space
Example Physical Address Space
Kernel Space
Stack1
Stack 2
Shared Libraries
Library 1
Heap1
Program Address Space in Linux..
Each Process use
its own page
tables
28
How Linux Manages Address Space
Stack (grows down)
Libraries (Memory
Mapping Segment)
Heap (grows up)
BSS Segment
Data Segment
Text Segment
task_struct
Process
Descriptor
mm_struct
Memory
Descriptor
mm
strart_stack
mmap_base
brk
start_brk
end_data
start_data end_code
start_code
29
How Linux Manages Address Space ..
30
Src: [3]
How Linux Manages Address Space ..
Example vm_area_struct
31
Src: [3]
How Linux Manages Address Space ..
32
Src: [3]
Accesses using linear addresses may cause page-fault
exceptions.
An access to a linear address may cause a page-fault
exception for either of two reasons:
There is no translation for the linear address
There is a translation for the linear address, but its access
rights do not permit the access.
In Linux do_page_fault() function is responsible for
the handling of page fault.
PAGE-FAULT EXCEPTIONS 33
Page Fault Handling in Linux
Overall scheme for the Page Fault handler
34
Src: [2]
PAGE-FAULT EXCEPTIONS
The error code that the processor provides on delivery of a page-fault exception
35
Src: [1]
References
[1]. Intel 64-ia-32-architectures-software-developer-
manual-325462
[2].Understanding the LINUX KERNEL , Third edition,
Daniel P. Bovet and Marco Cesati
[3]. http://duartes.org/gustavo/blog
[4]. YouTube video : Virtual Memory by David Black-
Schaffer
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THANK YOU