virtual memory - pagingjohanmon/courses/id2206/lectures/paging.pdf · the paging mmu with tlb...
TRANSCRIPT
![Page 1: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/1.jpg)
Virtual memory - Paging
Johan Montelius
KTH
2020
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The process
0x00000000 0xC0000000 0xffffffff
code(.text) data heap stack kernel
Memory layout for a 32-bit Linux process
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![Page 3: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/3.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
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![Page 4: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/4.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 5: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/5.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 6: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/6.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 7: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/7.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 8: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/8.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 9: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/9.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 10: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/10.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 11: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/11.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 12: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/12.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 13: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/13.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 14: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/14.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 15: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/15.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 16: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/16.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 17: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/17.jpg)
Segments - a could be solution
Physical memory
Processes in virtual space
Address translation by MMU(base and bounds)
3 / 32
![Page 18: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/18.jpg)
one problem
Physical memory
External fragmentation: free areas of free space that is hard to utilize.
Solution: allocate larger segments ... internal fragmentation.
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![Page 19: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/19.jpg)
one problem
Physical memory
External fragmentation: free areas of free space that is hard to utilize.
Solution: allocate larger segments ... internal fragmentation.
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![Page 20: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/20.jpg)
one problem
Physical memory
External fragmentation: free areas of free space that is hard to utilize.
Solution: allocate larger segments ...
internal fragmentation.
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![Page 21: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/21.jpg)
one problem
Physical memory
External fragmentation: free areas of free space that is hard to utilize.
Solution: allocate larger segments ... internal fragmentation.
4 / 32
![Page 22: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/22.jpg)
another problem
virtual space
physical memory
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![Page 23: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/23.jpg)
another problem
virtual space code
physical memory
5 / 32
![Page 24: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/24.jpg)
another problem
virtual space code
physical memory
5 / 32
![Page 25: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/25.jpg)
another problem
virtual space code
physical memory
5 / 32
![Page 26: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/26.jpg)
another problem
virtual space code
physical memory
used
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![Page 27: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/27.jpg)
another problem
virtual space code
physical memory
used
not used?
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![Page 28: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/28.jpg)
another problem
virtual space code
physical memory
used
not used?
We’re reserving physical memory that is not used.
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![Page 29: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/29.jpg)
Let’s try again
It’s easier to handle fixed size memory blocks.
Can we map a process virtual space to a set of equal size blocks?
An address is interpreted as a virtual page number (VPN) and an offset.
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![Page 30: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/30.jpg)
Let’s try again
It’s easier to handle fixed size memory blocks.
Can we map a process virtual space to a set of equal size blocks?
An address is interpreted as a virtual page number (VPN) and an offset.
6 / 32
![Page 31: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/31.jpg)
Let’s try again
It’s easier to handle fixed size memory blocks.
Can we map a process virtual space to a set of equal size blocks?
An address is interpreted as a virtual page number (VPN) and an offset.
6 / 32
![Page 32: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/32.jpg)
Let’s try again
It’s easier to handle fixed size memory blocks.
Can we map a process virtual space to a set of equal size blocks?
An address is interpreted as a virtual page number (VPN) and an offset.
6 / 32
![Page 33: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/33.jpg)
Remember the segmented MMUMMU
virtual addr.
+physical address
<yes
within bounds
no
exception
// offset
index
segment table7 / 32
![Page 34: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/34.jpg)
The paging MMUMMU
virtual addr.
8 / 32
![Page 35: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/35.jpg)
The paging MMUMMU
virtual addr. //
8 / 32
![Page 36: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/36.jpg)
The paging MMUMMU
virtual addr. //
page table8 / 32
![Page 37: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/37.jpg)
The paging MMUMMU
virtual addr. //
page table
VPN
8 / 32
![Page 38: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/38.jpg)
The paging MMUMMU
virtual addr. //
page table
VPN
+
offset
8 / 32
![Page 39: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/39.jpg)
The paging MMUMMU
virtual addr. //
page table
VPN
+
offset
physical address
8 / 32
![Page 40: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/40.jpg)
The paging MMUMMU
virtual addr. //
page table
VPN
+
offset
physical address
?
8 / 32
![Page 41: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/41.jpg)
The paging MMUMMU
virtual addr. //
page table
VPN
+
offset
physical address
?available
exception
8 / 32
![Page 42: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/42.jpg)
the MMU
Segmentation
virtual address
9 / 32
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the MMU
Segmentation
virtual address
linear address
9 / 32
![Page 44: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/44.jpg)
the MMU
Segmentation
virtual address
linear address
within bounds
exception
9 / 32
![Page 45: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/45.jpg)
the MMU
Segmentation
virtual address
linear address
within bounds
exception
Paging
9 / 32
![Page 46: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/46.jpg)
the MMU
Segmentation
virtual address
linear address
within bounds
exception
Paging
9 / 32
![Page 47: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/47.jpg)
the MMU
Segmentation
virtual address
linear address
within bounds
exception
Paging
physical address
9 / 32
![Page 48: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/48.jpg)
the MMU
Segmentation
virtual address
linear address
within bounds
exception
Paging
physical address
exception
page available
9 / 32
![Page 49: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/49.jpg)
a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
10 / 32
![Page 50: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/50.jpg)
a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
10 / 32
![Page 51: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/51.jpg)
a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
10 / 32
![Page 52: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/52.jpg)
a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
10 / 32
![Page 53: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/53.jpg)
a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
10 / 32
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a note on the x86 architecture
The x86-32 architecture supports both segmentation and paging. A virtual address istranslated to a linear address using a segmentation table. The linear address is thentranslated to a physical address by paging.
Linux and Windows do not use use segmentation to separate code, data nor stack.
The x86-64 (the 64-bit version of the x86 architecture) has dropped many features forsegmentation.
Still used to manage thread local storage and CPU specific data.
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
11 / 32
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the process
Physical memory
Processes in virtual space
Only pages actually used need to be in memory.
11 / 32
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three pages
virtual space
physical memory
12 / 32
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three pages
virtual space
physical memory
12 / 32
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three pages
virtual space
physical memory
12 / 32
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three pages
virtual space
physical memory
available
12 / 32
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three pages
virtual space
physical memory
available not available(page fault)
12 / 32
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three pages
virtual space
physical memory
available not available(page fault)
not allocated(segmentation fault)
12 / 32
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The pagetable
The MMU page module
//
+ ?
The page tableprovides translation from pagenumbers to frame numberskernel or user spaceread and write access rightsavailable in memory or on disk
Note: the page table is to large to fit into the MMU hardware, it is in main memory.
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The pagetable
The MMU page module
//
+ ?
The page tableprovides translation from pagenumbers to frame numberskernel or user spaceread and write access rightsavailable in memory or on disk
Note: the page table is to large to fit into the MMU hardware, it is in main memory.
13 / 32
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The pagetable
The MMU page module
//
+ ?
The page tableprovides translation from pagenumbers to frame numberskernel or user spaceread and write access rightsavailable in memory or on disk
Note: the page table is to large to fit into the MMU hardware, it is in main memory.13 / 32
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The page table entry
example Linux on (32bit) x86
31
If the page index is 20 bits, does the frame number need to be 20 bits?
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The page table entry
example Linux on (32bit) x86
31
Present
1
If the page index is 20 bits, does the frame number need to be 20 bits?
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The page table entry
example Linux on (32bit) x86
31
Present
112
If the page index is 20 bits, does the frame number need to be 20 bits?
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The page table entry
example Linux on (32bit) x86
31
Present
112
20-bit frame number
R/W
If the page index is 20 bits, does the frame number need to be 20 bits?
14 / 32
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The page table entry
example Linux on (32bit) x86
31
Present
112
20-bit frame number
R/W
User/Supervisor
If the page index is 20 bits, does the frame number need to be 20 bits?
14 / 32
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The page table entry
example Linux on (32bit) x86
31
Present
112
20-bit frame number
R/W
User/SupervisorReference
If the page index is 20 bits, does the frame number need to be 20 bits?
14 / 32
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The page table entry
example Linux on (32bit) x86
31
Present
112
20-bit frame number
R/W
User/SupervisorReference
Dirty
If the page index is 20 bits, does the frame number need to be 20 bits?
14 / 32
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The page table entry
example Linux on (32bit) x86
31
Present
112
20-bit frame number
R/W
User/SupervisorReference
Dirty
Global
If the page index is 20 bits, does the frame number need to be 20 bits?
14 / 32
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
15 / 32
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
15 / 32
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
15 / 32
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Physical Address Extension (PAE)
In 1995 the x86 architecture provided 24-bit frame numbers. The CPU could thusaddress 64 Gibyte of physical address space (24-bit frame, 12-bit offset).
Each process still had a 32-bit virtual address space, (20-bit page number, 12-bitoffset) i.e. 4 Gibyte.
The x86_64 architecture supports 48-bit virtual address space and up to 52-bitphysical address space.
Linux supports 48-bit virtual address (47-bit user space) and up to 46-bit physicaladdress space (64 Tibyte). Check your address space in /proc/cpuinfo.
Physical memory is in reality limited by chipset, motherboard, memory modules etc.Check your available memory in /proc/meminfo.
15 / 32
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largest server
Largest server on the market, SGI 3000, can scale up to 256 CPUs and 64 Tibyte ofRAM (NUMA) - running Linux.
16 / 32
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBR
the virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111
read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)
extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entry
the offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
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Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222
read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
![Page 100: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/100.jpg)
Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
![Page 101: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/101.jpg)
Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
![Page 102: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/102.jpg)
Speed matters
movl 0x11111222, %eax
we need a page table base register, PTBRthe virtual page number, VPN, is 0x11111read the page table entry from PTBR + (0x11111 * 8)extract frame number PFN from the entrythe offset is 0x222read the memory location at (PFN << 12) + 0x222
An extra memory operation for each memory reference.
17 / 32
![Page 103: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/103.jpg)
TLB: hardware support
The CPU keeps a translation look-aside buffer, TLB, with the most recent page tableentries.
The buffer is implemented using a content-addressable memory keyed by the virtualpage number.
If the page table entry is found - great!
If the page table entry is not found - access the real page table in memory.
18 / 32
![Page 104: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/104.jpg)
TLB: hardware support
The CPU keeps a translation look-aside buffer, TLB, with the most recent page tableentries.
The buffer is implemented using a content-addressable memory keyed by the virtualpage number.
If the page table entry is found - great!
If the page table entry is not found - access the real page table in memory.
18 / 32
![Page 105: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/105.jpg)
TLB: hardware support
The CPU keeps a translation look-aside buffer, TLB, with the most recent page tableentries.
The buffer is implemented using a content-addressable memory keyed by the virtualpage number.
If the page table entry is found - great!
If the page table entry is not found - access the real page table in memory.
18 / 32
![Page 106: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/106.jpg)
TLB: hardware support
The CPU keeps a translation look-aside buffer, TLB, with the most recent page tableentries.
The buffer is implemented using a content-addressable memory keyed by the virtualpage number.
If the page table entry is found - great!
If the page table entry is not found - access the real page table in memory.
18 / 32
![Page 107: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/107.jpg)
TLB: hardware support
The CPU keeps a translation look-aside buffer, TLB, with the most recent page tableentries.
The buffer is implemented using a content-addressable memory keyed by the virtualpage number.
If the page table entry is found - great!
If the page table entry is not found - access the real page table in memory.
18 / 32
![Page 108: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/108.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARM
The hardware rises an interrupt.The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 109: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/109.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.
The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 110: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/110.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.The operating system jumps to a traphandler.
The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 111: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/111.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 112: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/112.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86
The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 113: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/113.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).
The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 114: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/114.jpg)
Who handles a TLB miss
RISC architectureMIPS, Sparc, ARMThe hardware rises an interrupt.The operating system jumps to a traphandler.The operating system will access theTLB and update the TLB.
CISC architecturex86The hardware “knows” where to findthe page table (CR3 register).The hardware will access the pagetable and updates the TLB.
19 / 32
![Page 115: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/115.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 116: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/116.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 117: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/117.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 118: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/118.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 119: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/119.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 120: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/120.jpg)
Process switching
What happens when we switch process?
The TLB contains the cached translations of the running process, when switchingprocess the TLB must (in general) be flushed.
Do we have to flush the whole TLB?
Is this best handled by the hardware or operating system?
Can we do pre-fetching of page table entries?
20 / 32
![Page 121: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/121.jpg)
The paging MMU with TLB
virtual addr.
21 / 32
![Page 122: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/122.jpg)
The paging MMU with TLB
virtual addr. //
21 / 32
![Page 123: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/123.jpg)
The paging MMU with TLB
virtual addr. //
21 / 32
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The paging MMU with TLB
virtual addr. //
TLB
VPN
21 / 32
![Page 125: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/125.jpg)
The paging MMU with TLB
virtual addr. //
TLB
VPN
+
offset
PFNphysical address
21 / 32
![Page 126: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/126.jpg)
The paging MMU with TLB
virtual addr. //
TLB
VPN
+
offset
PFNphysical address
PTBR
21 / 32
![Page 127: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/127.jpg)
The paging MMU with TLB
virtual addr. //
TLB
VPN
+
offset
PFNphysical address
PTBR+
VPN
21 / 32
![Page 128: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/128.jpg)
The paging MMU with TLB
virtual addr. //
TLB
VPN
+
offset
PFNphysical address
PTBR+
VPN
Page table in memory
21 / 32
![Page 129: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/129.jpg)
The paging MMU with TLB
virtual addr. //
TLB
VPN
+
offset
PFNphysical address
PTBR+
VPN
Page table in memory
PTE
21 / 32
![Page 130: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/130.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 131: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/131.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 132: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/132.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 133: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/133.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 134: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/134.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 135: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/135.jpg)
Size matters
Using 4 Kibyte pages (12 bits) for a 4 Gibyte address space (32 bits) will result in 1Mi(20 bits) page table entries.
Each page table entry is 4 bytes.
A page table has the size of 4 Mibyte.
Each process has its own page table.
For 100 processes we need room for 400 Mibyte of page tables.
Problem!
22 / 32
![Page 136: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/136.jpg)
The solution - not.
Why not use pages of size 4 Mibyte?
Use a 22 bit offset and 10 bit virtual page number.Page table 4 Kibyte (1024 entries, 4 byte each).Case closed!
4 Mibyte pages are used and do have advantages but it is not a general solution.
23 / 32
![Page 137: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/137.jpg)
The solution - not.
Why not use pages of size 4 Mibyte?Use a 22 bit offset and 10 bit virtual page number.
Page table 4 Kibyte (1024 entries, 4 byte each).Case closed!
4 Mibyte pages are used and do have advantages but it is not a general solution.
23 / 32
![Page 138: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/138.jpg)
The solution - not.
Why not use pages of size 4 Mibyte?Use a 22 bit offset and 10 bit virtual page number.Page table 4 Kibyte (1024 entries, 4 byte each).
Case closed!
4 Mibyte pages are used and do have advantages but it is not a general solution.
23 / 32
![Page 139: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/139.jpg)
The solution - not.
Why not use pages of size 4 Mibyte?Use a 22 bit offset and 10 bit virtual page number.Page table 4 Kibyte (1024 entries, 4 byte each).Case closed!
4 Mibyte pages are used and do have advantages but it is not a general solution.
23 / 32
![Page 140: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/140.jpg)
The solution - not.
Why not use pages of size 4 Mibyte?Use a 22 bit offset and 10 bit virtual page number.Page table 4 Kibyte (1024 entries, 4 byte each).Case closed!
4 Mibyte pages are used and do have advantages but it is not a general solution.
23 / 32
![Page 141: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/141.jpg)
Mostly empty space
0x00000000 0xC0000000 0xffffffff
code(.text) data heap stack kernel
Map only the areas that are actually used.
24 / 32
![Page 142: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/142.jpg)
Mostly empty space
0x00000000 0xC0000000 0xffffffff
code(.text) data heap stack kernel
Map only the areas that are actually used.
24 / 32
![Page 143: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/143.jpg)
Mostly empty space
0x00000000 0xC0000000 0xffffffff
code(.text) data heap stack kernel
Map only the areas that are actually used.
24 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.
31 0
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
29
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
base/bound
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
base/bound
bound
base
page table
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
base/bound
bound
base
page table
frame number
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
base/bound
bound
base
page table
frame number
page
25 / 32
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Hybrid approach - paged segmented memory
What if each segment was rarely larger than 1Ki pages of 4Kibyte.31 0seg
2918-bit page number
12
12-bit offset
base/bound
bound
base
page table
frame number
page
25 / 32
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Multi-level page table
31 0
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
22
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directory
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directory
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directorypage table
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directorypage table
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directorypage table
page
Used by Intel 80386
26 / 32
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Multi-level page table
31 010-bit directory index
2210-bit page index
12
12-bit offset
page directorypage table
page
Used by Intel 80386
26 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
27 / 32
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Mostly empty space
page directory
virtual address space
each page table can map 4 Mibyte
27 / 32
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More than two levels
31 0
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
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More than two levels
31 0
2-bit page global directory index
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
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More than two levels
31 0
2-bit page global directory index
9-bit page middle directory index
29 21
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
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More than two levels
31 0
2-bit page global directory index
9-bit page middle directory index
29 21
9-bit page table index
20 12
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
![Page 175: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/175.jpg)
More than two levels
31 0
2-bit page global directory index
9-bit page middle directory index
29 21
9-bit page table index
20 12
12-bit offset
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
![Page 176: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/176.jpg)
More than two levels
31 0
2-bit page global directory index
9-bit page middle directory index
29 21
9-bit page table index
20 12
12-bit offset
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
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More than two levels
31 0
2-bit page global directory index
9-bit page middle directory index
29 21
9-bit page table index
20 12
12-bit offset
Scheme used in PAE, where each entry has a 24-bit physical base address. Each pagetable entry was 8 bytes whide.
Trace the translation of a 32-bit virtual address to a 36-bit physical address.
28 / 32
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The x86_64 architectures
A 64-bit address but only 48-bits are used.
Bits 63-47 are either 1, kernel space, or 0, user space.The 48 bits are divided into:
9-bit page global directory index9-bit page upper directory index9-bit page lower directory index9-bit page table index12-bit offset
A page table entry is 8 bytes and contains a 40-bit physical address base address.The 40-bit base is combined with the 12-bit index to a 52-bit physical address.
Linux can only handle 64 Tbyte of RAM i.e. 46 bits.
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The x86_64 architectures
A 64-bit address but only 48-bits are used.Bits 63-47 are either 1, kernel space, or 0, user space.The 48 bits are divided into:
9-bit page global directory index9-bit page upper directory index9-bit page lower directory index9-bit page table index12-bit offset
A page table entry is 8 bytes and contains a 40-bit physical address base address.
The 40-bit base is combined with the 12-bit index to a 52-bit physical address.
Linux can only handle 64 Tbyte of RAM i.e. 46 bits.
29 / 32
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The x86_64 architectures
A 64-bit address but only 48-bits are used.Bits 63-47 are either 1, kernel space, or 0, user space.The 48 bits are divided into:
9-bit page global directory index9-bit page upper directory index9-bit page lower directory index9-bit page table index12-bit offset
A page table entry is 8 bytes and contains a 40-bit physical address base address.The 40-bit base is combined with the 12-bit index to a 52-bit physical address.
Linux can only handle 64 Tbyte of RAM i.e. 46 bits.
29 / 32
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The x86_64 architectures
A 64-bit address but only 48-bits are used.Bits 63-47 are either 1, kernel space, or 0, user space.The 48 bits are divided into:
9-bit page global directory index9-bit page upper directory index9-bit page lower directory index9-bit page table index12-bit offset
A page table entry is 8 bytes and contains a 40-bit physical address base address.The 40-bit base is combined with the 12-bit index to a 52-bit physical address.
Linux can only handle 64 Tbyte of RAM i.e. 46 bits.
29 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?
We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.
If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.
Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.
To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).
Used by some models of PowerPC, Ultra Sparc and Itanium.
30 / 32
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Inverted page tables
Why not do something completely different?We will probably not have more than say 8 Gibyte of main memory.If we divide this into 4 Kibyte frames we have 2 Mi frames.Assume maintain a table with 2 Mi entries that describes which process and pagethat occupies the frame.To translating a virtual address we simply search the table (efficient if we use ahash table).Used by some models of PowerPC, Ultra Sparc and Itanium.
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![Page 189: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/189.jpg)
Summary
Segmentation is not an ideal solution (why?).
Small fixed size pages is a solution.Speed of translation is a problem (what is the solution?)The size of the page table is a problem (and you know how to solve it).Inverted page tables - an alternative approach.
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![Page 190: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/190.jpg)
Summary
Segmentation is not an ideal solution (why?).Small fixed size pages is a solution.
Speed of translation is a problem (what is the solution?)The size of the page table is a problem (and you know how to solve it).Inverted page tables - an alternative approach.
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![Page 191: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/191.jpg)
Summary
Segmentation is not an ideal solution (why?).Small fixed size pages is a solution.Speed of translation is a problem (what is the solution?)
The size of the page table is a problem (and you know how to solve it).Inverted page tables - an alternative approach.
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![Page 192: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/192.jpg)
Summary
Segmentation is not an ideal solution (why?).Small fixed size pages is a solution.Speed of translation is a problem (what is the solution?)The size of the page table is a problem (and you know how to solve it).
Inverted page tables - an alternative approach.
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![Page 193: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/193.jpg)
Summary
Segmentation is not an ideal solution (why?).Small fixed size pages is a solution.Speed of translation is a problem (what is the solution?)The size of the page table is a problem (and you know how to solve it).Inverted page tables - an alternative approach.
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![Page 194: Virtual memory - Pagingjohanmon/courses/id2206/lectures/paging.pdf · The paging MMU with TLB virtualaddr. // TLB VPN + offset PFN physicaladdress + PTBR VPN Pagetableinmemory PTE](https://reader033.vdocument.in/reader033/viewer/2022051606/601b7bae8a6afe798475ea90/html5/thumbnails/194.jpg)
AC/DC - TLB
TLB - dynamite, makes paging possible.32 / 32