virtual memory presentation

7/31/2019 Virtual Memory Presentation

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To provide applications with the illusion of having

a very large amount of memory, a technique

known as virtual memory was developed.

In a virtual memory system, not all parts of a

process are stored in the main memory.

The seldom-used parts of a program are stored

elsewhere, such as in disks and other storagedevices, and are only placed in the main memory

when needed.


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Memory management is the general term to coverall techniques of translating a virtual address tophysical address.

The special hardware used to do the translation isthe memory management unit (MMU) via the useof page tables PTs.

The MMU receives the virtual address generated

by the CPU and converts it to the correspondingphysical address, which can be used to access themain memory.


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Each virtual memory reference can cause two

physical memory accesses

One to fetch the page table

One to fetch the data

To overcome this problem a high-speed cache

is set up for page table entries called a

Translation Lookaside Buffer (TLB)


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processors include a translation lookaside buffer

(TLB) that speeds up address translation.

TLB contains page table entries (PTEs) of recently

used virtual-to physical address translations.


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The aim of this study is to design and

implement a TLB design structures using

VHDL.

fully associative structures consume the least

amount of power and provide the shortest

fetch time and also produce the lowest miss

rate.


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CAM: content addressable memory

SRAM: static RAM


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the previous simplified block diagram of the TLB. It is

mainly composed of the content addressable

memory (CAM), which stores the VPN of available

translations, and the static random access memory(SRAM), which stores the corresponding PPN.

Content addressable memories (CAMs) differ from

ordinary memory in that it allows access through itsdata rather than by the datas address.


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The match operation looks for a matchbetween the input data and data stored in thememory array.

Each of the stored word has its correspondingmatch flag indicating a match between the

data and the corresponding word, andsignaling the corresponding word in the SRAMto output its data.


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State machine of the MMU

The system is represented by 5 states:

0- Idle state

1- Read state

2- Hit state

3- Miss state

4- Page Fault state


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Idle stateMMU is waiting for a read signal from cpu

Read stateread virtual address from TLB

Hit stateget Physical address from TLB and send out to read fromRAM.

Miss stateread virtual address from Page table (PT) and send out to

read from RAM. PAGE FAULT

virtual address doesnt exist in page table and system willhave to get it from auxiliary memory.


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virtual memory presentation

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