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16.480/552 Microprocessor and Embedded Systems II

Virtual Memory

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Memory Organization

° What is random access memory (RAM)? What arestatic RAM (SRAM) and dynamic RAM (DRAM)?

° What is DRAM Cell organization? How are the cellsarranged internally? Memory addressing?Refreshing of DRAMs? Difference between DRAMand SRAM?

° Access time of DRAM = Row access time + columnaccess time + refreshing

° What are page-mode and nibble-mode DRAMs?° Synchronous SRAM or DRAM – Ability to transfer a

burst of data given a starting address and a burstlength – suitable for transferring a block of data frommain memory to cache.

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Main Memory OrganizationsCPU

Cache

Bus

Memory

CPU

Bus

Memory

Multiplexor

Cache

CPU

Cache

Bus

Memorybank 1

Memorybank 2

Memorybank 3

Memorybank 0

one-word widememory organization

wide memory organization interleaved memory organization

DRAM access time >> bus transfer time

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Memory Interleaving

Interleaved memory is more flexible than wide-access memory inthat it can handle multiple independent accesses at once.

Add- ress

Addresses that are 0 mod 4

Addresses that are 2 mod 4

Addresses that are 1 mod 4

Addresses that are 3 mod 4

Return data

Data in

Data out

Dispatch (based on 2 LSBs of address)

Bus cycle

Memory cycle

0

1

2

3

0

1

2

3

Module accessed

Time

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Memory Access Time Example

° Assume that it takes 1 cycle to send the address,15 cycles for each DRAM access and 1 cycle tosend a word of data.

° Assuming a cache block of 4 words and one-wordwide DRAM, miss penalty = 1 + 4x15 + 4x1 = 65cycles

° With main memory and bus width of 2 words, misspenalty = 1 + 2x15 + 2x1 = 33 cycles. For 4-wordwide memory, miss penalty is 17 cycles. Expensivedue to wide bus and control circuits.

° With interleaved memory of 4 memory banks andsame bus width, the miss penalty = 1 + 1x15 + 4x1= 20 cycles. The memory controller must supplyconsecutive addresses to different memory banks.Interleaving is universally adapted in high-performance computers.

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Virtual Memory° Idea 1: Many Programs sharing DRAM

Memory so that context switches can occur

° Idea 2: Allow program to be written withoutmemory constraints – program can exceedthe size of the main memory

° Idea 3: Relocation: Parts of the programcan be placed at different locations in thememory instead of a big chunk.

°Virtual Memory:(1) DRAM Memory holds many programsrunning at same time (processes)

(2) use DRAM Memory as a kind of“cache” for disk

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Data movement in a memory hierarchy.

Memory Hierarchy: The Big Picture

Pages

Lines

Words

Registers

Main memory

Cache

Virtual memory

(transferred explicitly

via load/store) (transferred automatically

upon cache miss) (transferred automatically

upon page fault)

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Fig. 20.11 Trends in disk, main memory, and CPU speeds.

Impact of Technology on Virtual Memory

1990 1980 2000 2010

Tim

e

Calendar year

Disk seek time

ps

ns

µs

s

ms

CPU cycle time

DRAM access time

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Virtual Memory has own terminology° Each process has its own private “virtual

address space” (e.g., 232 Bytes); CPU actuallygenerates “virtual addresses”

° Each computer has a “physical address space”(e.g., 128 MegaBytes DRAM); also called “realmemory”

° Address translation: mapping virtual addressesto physical addresses

• Allows multiple programs to use (differentchunks of physical) memory at same time

• Also allows some chunks of virtual memoryto be represented on disk, not in mainmemory (to exploit memory hierarchy)

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Mapping Virtual Memory to Physical Memory

0

Physical Memory

∞Virtual Memory

Heap64 MB

° Divide Memory into equal sized“chunks” (say, 4KB each)

0

° Any chunk of Virtual Memoryassigned to any chunk ofPhysical Memory (“page”)

Stack

Heap

Static

Code

SingleProcess

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Handling Page Faults

°A page fault is like a cache miss• Must find page in lower level of hierarchy

° If valid bit is zero, the Physical PageNumber points to a page on disk

°When OS starts new process, itcreates space on disk for all the pagesof the process, sets all valid bits inpage table to zero, and all PhysicalPage Numbers to point to disk

• called Demand Paging - pages of theprocess are loaded from disk only asneeded

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Comparing the 2 levels of hierarchy°Cache Virtual Memory°Block or Line Page°Miss Page Fault°Block Size: 32-64B Page Size: 4K-16KB°Placement: Fully AssociativeDirect Mapped,N-way Set Associative

°Replacement: Least Recently UsedLRU or Random (LRU) approximation

°Write Thru or Back Write Back°How Managed: Hardware + SoftwareHardware (Operating System)

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How to Perform Address Translation?

°VM divides memory into equal sizedpages

°Address translation relocates entirepages

• offsets within the pages do not change• if make page size a power of two, thevirtual address separates into two fields:

• like cache index, offset fields

Virtual Page Number Page Offset virtual address

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Mapping Virtual to Physical Address

Virtual Page Number Page Offset

Page OffsetPhysical Page Number

Translation

31 30 29 28 27 .………………….12 11 10

29 28 27 .………………….12 11 10

9 8 ……..……. 3 2 1 0

Virtual Address

Physical Address 9 8 ……..……. 3 2 1 0

1KB pagesize

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Address Translation°Want fully associative page placement°How to locate the physical page?°Search impractical (too many pages)°A page table is a data structure whichcontains the mapping of virtual pagesto physical pages

• There are several different ways, all up tothe operating system, to keep this dataaround

°Each process running in the systemhas its own page table

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Address Translation: Page TableVirtual Address (VA):

virtual page nbr offset

Page TableRegister

Page Tableis locatedin physicalmemory

indexintopagetable

+

PhysicalMemory

Address (PA)

Access Rights: None, Read Only,Read/Write, Executable

Page Table

Val-id

AccessRights

PhysicalPageNumber

V A.R. P. P. N.0 A.R.

V A.R. P. P. N.

...

...

disk

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Page Tables and Address Translation

The role of page table in the virtual-to-physical addresstranslation process.

Page table

Main memory

Valid bits

Page table register

Virtual page

number

Other f lags

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Protection and Sharing in Virtual Memory

Virtual memory as a facilitator of sharing and memoryprotection.

Page table for process 1

Main memory

Permission bits

Pointer Flags

Page table for process 2

To disk memory

Only read accesses allow ed

Read & w rite accesses allowed

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Optimizing for Space°Page Table too big!

• 4GB Virtual Address Space ÷ 4 KB page ⇒ 220 (~ 1 million) Page Table Entries ⇒ 4 MB just for Page Table of singleprocess!

°Variety of solutions to tradeoff PageTable size for slower performance whenmiss occurs in TLB

Use a limit register to restrict page tablesize and let it grow with more pages,Multilevelpage table, Paging page tables, etc.

(Take O/S Class to learn more)

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How Translate Fast?° Problem: Virtual Memory requires two

memory accesses!• one to translate Virtual Address into Physical

Address (page table lookup)• one to transfer the actual data (cache hit)• But Page Table is in physical memory! => 2 main

memory accesses!° Observation: since there is locality in pages

of data, must be locality in virtual addressesof those pages!

° Why not create a cache of virtual to physicaladdress translations to make translationfast? (smaller is faster)

° For historical reasons, such a “page tablecache” is called a Translation LookasideBuffer, or TLB

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Typical TLB FormatVirtual Physical Valid Ref Dirty Access

Page Nbr Page Nbr Rights

•TLB just a cache of the page table mappings

• Dirty: since use write back, need to knowwhether or not to write page to disk whenreplaced• Ref: Used to calculate LRU on replacement

• TLB access time comparable to cache (much less than main memory access time)

“tag” “data”

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Translation Look-Aside Buffers•TLB is usually small, typically 32-4,096 entries

• Like any other cache, the TLB can be fullyassociative, set associative, or direct mapped

Processor TLB Cache MainMemory

misshit

data

hit

miss

DiskMemory

OS FaultHandler

page fault/protection violation

PageTable

data

virtualaddr.

physicaladdr.

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Translation Lookaside Buffer

Virtual-to-physical address translation by a TLB and how theresulting physical address is used to access the cache memory.

Virtual page number

Byte offset

Byte offset in word

Physical address tag

Cache index

Valid bits

TLB tags

Tags match and entry is valid

Physical page number Physical

address

Virtual address

Tra

nsla

tion

Other flags

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Valid Tag Data

Page offset

Page offset

Virtual page number

Physical page numberValid

1220

20

16 14

Cache index

32

DataCache hit

2Byte

offset

Dirty Tag

TLB hit

Physical page number

Physical address tag

31 30 29 15 14 13 12 11 10 9 8 3 2 1 0 DECStation 3100/MIPS R2000Virtual Address

TLB

Cache

64 entries,fully

associative

Physical Address

16K entries,direct

mapped

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Real Stuff: Pentium Pro Memory Hierarchy° Address Size: 32 bits (VA, PA)° VM Page Size: 4 KB, 4 MB° TLB organization: separate i,d TLBs

(i-TLB: 32 entries,d-TLB: 64 entries)4-way set associativeLRU approximatedhardware handles miss

° L1 Cache: 8 KB, separate i,d 4-way set associativeLRU approximated32 byte blockwrite back

° L2 Cache: 256 or 512 KB