DRC and LVS checks using Cadence Virtuoso

Version 4.0

Start virtuoso l  Open a virtuoso session in the directory which

contains the required cds.lib and lib.def files. l  Command : virtuoso &

l  Open the layout corresponding to your design(final_chip) in layout XL by right clicking on the layout and selecting “open with”. Change the application to layout XL. This will open the schematic as well as the layout.

l  For DRC check go to verify -> DRC. l  Specify the rules file and uncheck the Rules

library. l  Result will be displayed in the virtuoso

command window

l  Make sure that the total errors are zero. l  If errors are found fix the errors before

proceeding to the next steps. l  You can use the errors displayed in the

command window to debug or also use the following to zoom into the errors locations : verify->Markers->Find. Select “zoom to markers” and then cycle through the different errors by hitting “Next”. Uncheck the warnings to display only the errors during this process.

Extracting the design for LVS check: l  Go to verify-> extract l  Specify the rules file and uncheck the rules

library. l  The results will be displayed in the command

window. l  A successful extraction(total errors = 0) will

generate a extracted cell view. Verify this using the library manager.

LVS check: l  LVS will compare the extracted and the

schematic views. l  Go to verify->LVS. l  Select “Form contents” and click “ok” if a

“Artist LVS form contents Form contents Different window” pops up.

l  Specify the schematic and extracted views for your design.

l  Specify the rules file and Hit run.

l  Make sure that the design passes LVS. The previous slide shows the output generated when the design passes LVS.

l  IF the netlists don't match use the following resources to correct your layout or schematic:

-> click on output in the Artist LVS window to get the report that will show the errors in more detail.

-> You can also use the info button in the Artist LVS window to get a more detailed view of the errors for schematic or layout separately.

-> You can also use the Error Display button in the artist LVS window to cycle through the different errors in the extracted view and then correct them in the layout view. Make sure to open the extracted view before doing this procedure. The schematic can then be opened to cycle through the errors there too.

-> Also the shorts locator can be used to find any net locations causing trouble in the extracted view.

Following are some rules that can help you debug the design using the output from the Artist LVS window:

l  Number of terminals don't match: This is commonly due to missing terminals/pins

in the layout or mismatch in terminal names between layout and schematic.

l  Number of nets don't match: If the number of nets given for your layout is

higher than that of schematic then layout is missing some connections.

The first scenario for this situation is that your output will say something like “ ?Net /net 027 merged with /R.” What the above line means is that net 027, which is some internal connection in the circuit, needs to be connected to terminal R.

The second scenario for this situation is that your output will say something like“terminal gnd! in layout fails to match any terminal in the schematic”. In the given case,a transistor that should be connected to gnd! probably is not connected, so you would need to inspect your layout and find where a connection needs to be made.

l  If the number of nets in the layout is less than that of the schematic then there are some connections in the layout that need not be made but are present.

Note : In case the LVS process terminates in the middle giving the following error:

“The LVS job failed to run to completion” click on info button in the artist LVS window and open the log file and check the schematics that need a check and save(towards the bottom of the log file you will see something like “xyz” has been changed since last extracted). Check the save the required schematics and then re run LVS.

Cadence Assura

for Density Checks

Density issues MOSIS will run these checks for you, but you can preemptively run Assura before submission. In the case that you have failed to meet minimum layer densities, you may need to introduce additional polygons into the design. The design to the right failed on the poly layer density. Notice the four rectangles that were added to the dead space around the core but within the pad ring.

DRC LVS with Cadence Common Problems and Solutions

Metal 2 spacing DRC - you have a Vdd connection that is too close to a row power line and are getting a metal 2 spacing issue. See pic. Just move the power connection down a micron or so.

Metal 3 spacing DRC – a quick jog in metal can cause a problem near a via. Just move the via farther away.