vishwani d. agrawal james j. danaher professor dept. of electrical and computer engineering
DESCRIPTION
ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email protected] - PowerPoint PPT PresentationTRANSCRIPT
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 11
ELEC 5270/6270 Spring 2013ELEC 5270/6270 Spring 2013Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Pass Transistor Logic: A Low Power Pass Transistor Logic: A Low Power Logic FamilyLogic Family
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 22
Low-Power Logic StylesLow-Power Logic Styles
Pass transistor logicPass transistor logicDynamic logicDynamic logicDomino logicDomino logicAdiabatic and charge recovery logicAdiabatic and charge recovery logicAsynchronous logicAsynchronous logicLogic restructuringLogic restructuring
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 33
Pass Transistor Logic (PTL)Pass Transistor Logic (PTL)
Requires fewer transistorsRequires fewer transistorsSmaller areaSmaller areaReduced capacitanceReduced capacitanceReduced energy and powerReduced energy and power
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 44
CMOS AND GateCMOS AND Gate
F = ABA
B
A
B
F = AB
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 55
Pass Transistor AND GatePass Transistor AND Gate
A
B
F = AB
0
Need 4 transistors instead of 6 for CMOS AND gate.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 66
CMOS OR GateCMOS OR Gate
F = A + BA
B
A
B
F = A + B
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 77
Pass Transistor OR GatePass Transistor OR Gate
1
B
F = A + B
A
Need 4 transistors instead of 6 for CMOS OR gate.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 88
Reduced Voltage SwingReduced Voltage Swing
VDD = 2.5V
IN
OUT
n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ
Vx = VDD – Vtn
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 99
Spice SimulationSpice Simulation
Time, ns
0 0.5 1.0 1.5 2.0
3.0
2.0
1.0
0.0
Vo
ltage
, VIN
OUT
Vx
J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1010
Voltage Transfer Characteristic Voltage Transfer Characteristic (VTC) of AND Gate(VTC) of AND Gate
A
B
F = AB
0
n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1111
VTC: Spice SimulationVTC: Spice Simulation
Vin, V
0 0.5 1.0 1.5 2.0 2.5
3.0
2.0
1.0
0.0
F, V
B = VDDA = 0 → VDD
A = VDD, B = 0 → VDDA = B = 0 → VDD
VDD – Vtn
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1212
EnergyEnergy
VDD = 2.5V
0 → VDD
CL
T TE0→1 = ∫ P(t) dt = VDD ∫ i(t) dt
0 0
VDD-Vtn
= VDD ∫ CL dVout = CL VDD (VDD – Vtn) < CL VDD2
0
If this voltage is insufficient for turning the pMOSTransistor in inverter off, leakage power will be consumed.
Vout
i(t)
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1313
Energy: PTL vs. CMOSEnergy: PTL vs. CMOS
PTL consumes less dynamic power than PTL consumes less dynamic power than static CMOS Logic.static CMOS Logic.
PTL leakage may be higher when inverter PTL leakage may be higher when inverter output is low, because the reduced voltage output is low, because the reduced voltage level may be insufficient to turn the PMOS level may be insufficient to turn the PMOS transistor in the inverter off.transistor in the inverter off.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1414
Ways to Reduce LeakageWays to Reduce Leakage
Level restorationLevel restorationMultiple-threshold transistorsMultiple-threshold transistorsTransmission-gate logicTransmission-gate logic
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1515
Level RestorationLevel Restoration
A=1
B=1
CL
Vout
VDD Level restorer
Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible.
0
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1616
Multiple-Threshold TransistorsMultiple-Threshold TransistorsUse zero-threshold pass-transistors.Use zero-threshold pass-transistors.Use high-threshold transistors in all other Use high-threshold transistors in all other
gates.gates.This can cause leakage through multiple This can cause leakage through multiple
gates.gates.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1717
Leakage Through Zero-Threshold Leakage Through Zero-Threshold TransistorsTransistors
0
1
1
0
Zero or low-threshold transistors
Leakage current path
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1818
Transmission-Gate LogicTransmission-Gate Logic Provides both power and ground levels.Provides both power and ground levels. Good design, except needs more transistors. Good design, except needs more transistors.
A
S
B
F’ = S’A’ + SB’
Inverting multiplexer
F
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 1919
Transmission-Gate XORTransmission-Gate XOR
A AB’+A’B
B
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2020
A Logic LibraryA Logic LibraryCellCell
Number of transistorsNumber of transistors
CMOSCMOS TGLTGL
OR02OR02 66
MUX21MUX21 1212 66
AND02AND02 66
XOR2XOR2 1212 66
AND03AND03 88
AOI32AOI32 1010
OAI21OAI21 66
OAI32OAI32 1010
AO21AO21 88
NOR04NOR04 88
OR03OR03 88
NOR02_2xNOR02_2x 44
OAI221OAI221 1010
NAND02_2xNAND02_2x 44
AOI321AOI321 1212
INV02INV02 22
DFFRDFFR 3434
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CMOS MultiplexerCMOS Multiplexer
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2121
AS
BINV02
AND-OR-INVERT (AOI22)
MULTIPLEXER
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CMOS Multiplexer CellCMOS Multiplexer Cell
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2222
A
B
A
S
S
S
B
S
S S F
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2323
Synthesis of PTLSynthesis of PTL
AA BB CC ZZ
00 00 00 00
00 00 11 00
00 11 00 00
00 11 11 11
11 00 00 00
11 00 11 11
11 11 00 11
11 11 11 11
Shannon’s expansion:
Z = AB + BC + AC = A(B+BC+C) + A’(BC) = A(B+C) + A’BC = A[B+B’C] + A’[BC+B’0]
A 1 0
1 0 1 0B
C C1 0
Z
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2424
Synthesis of Z = AB + BC + ACSynthesis of Z = AB + BC + AC
B
C1
A
Z
A = 1, Z = B + B’CB = 1, Z = 1B = 0, Z = C
A = 0, Z = BCB = 1, Z = CB = 0, Z = 0
0
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2525
Pass-Transistor CellPass-Transistor Cell
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2626
Synthesis of Z = A’B + B’C + A’C’Synthesis of Z = A’B + B’C + A’C’
B
0A
C
Z
C = 1, Z = A’B + B’B = 1, Z = A’B = 0, Z = 1
C = 0, Z = A’
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2727
Synthesis of Z = A’ + BC’ + B’CSynthesis of Z = A’ + BC’ + B’C0
B
B’
A
A’
C C’
Z
A = 1, Z = BC’ + B’CB = 1, Z = C’B = 0, Z = C
A = 0, Z = 1
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2828
Synthesis of Z = AB’C’ + A’B’CSynthesis of Z = AB’C’ + A’B’C
A’
A
B’
B
C’ C 1
Z
A = 1, Z = B’C’B = 1, Z = 0B = 0, Z = C’
A = 0, Z = B’CB = 1, Z = 0B = 0, Z = C
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 2929
CPL: Complementary Pass-CPL: Complementary Pass-Transistor LogicTransistor Logic
Every signal and its complement is Every signal and its complement is generated.generated.
Gates are static, because the output is Gates are static, because the output is connected to either VDD or GND.connected to either VDD or GND.
Design is modular; same cell can produce Design is modular; same cell can produce various gates by simply permuting the various gates by simply permuting the input signals.input signals.
Also called differential pass-transistor logic Also called differential pass-transistor logic (DPL)(DPL)
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3030
A CPL CellA CPL Cell
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3131
CPL Cell Used As AND/NANDCPL Cell Used As AND/NAND
A
B
A’
B’
B B’
Z = AB
Z’ = (AB)’
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3232
CPL Cell Used As OR/NORCPL Cell Used As OR/NOR
A
B
A’
B’
B’ B
Z = A + B
Z’ = (A + B)’
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3333
CPL Cell Used As XOR/XNORCPL Cell Used As XOR/XNOR
A
A’
A’
A
B’ B
Z = AB’ + A’B
Z’ = AB + A’B’
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3434
CPL vs. CMOSCPL vs. CMOS
CPL requires fewer transistors.CPL requires fewer transistors.Useful for modular (array) circuits like Useful for modular (array) circuits like
adders, multipliers, barrel shifter, etc.adders, multipliers, barrel shifter, etc.CPL operation can be faster and energy CPL operation can be faster and energy
efficient.efficient.Following example is taken from:Following example is taken from:
M. E. Elrabaa, I. S. Abu-Khater, and M. I. M. E. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Elmasry, Advanced Low-Power Digital Circuit Advanced Low-Power Digital Circuit TechniquesTechniques, Springer, 1997, Chapter 2., Springer, 1997, Chapter 2.
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3535
Example: 4-Bit Carry Select AdderExample: 4-Bit Carry Select Adder
A_1 B_1Adder cell
S1’ S0’ C0’ C0 C1’ C1
A_2 B_2Adder cell
S1’ S0’ C0’ C0 C1’ C1
M M M
M M M
MMMM
S_1
C’_0
C_0 S_2
A_3 B_3Adder cell
S1’ S0’ C0’ C0 C1’ C1
A_4 B_4Adder cell
S1’ S0’ C0’ C0 C1’ C1
M M M
M M M
MMMM
S_3
C’_2
S_4
C’_4
C_4
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3636
CMOS Carry-Select Adder CellCMOS Carry-Select Adder Cell
S1’ S0’ C0’ C0 C1’ C1
Ai Bi
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3737
CPL Adder CellCPL Adder Cell
Ai Bi
S1’ S0’ C0’ C0 C1’ C1
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3838
CPL Multiplexer CellCPL Multiplexer Cell
Ci
Ci’
in1 in2
in1 in2
Ci
Ci’
M
out
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 3939
32-Bit Adders in 0.832-Bit Adders in 0.8μμ, 3.3V, 3.3V
Type of designType of design Type of logicType of logicEnergyEnergy
μμW/MHzW/MHz
DelayDelay
nsns
Minimum Minimum transistor sizetransistor size
CMOSCMOS 90.090.0 11.011.0
CPLCPL 65.065.0 10.010.0
Transistor sizing Transistor sizing for delay for delay
optimizationoptimization
CMOSCMOS 93.093.0 10.510.5
CPLCPL 72.072.0 7.57.5
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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 13, Lecture 12ELEC6270 Spring 13, Lecture 12 4040
ReferencesReferencesG. R. Cho and T. Chen, “On the Impact of G. R. Cho and T. Chen, “On the Impact of
Technology Scaling on Mixed PTL/Static Technology Scaling on Mixed PTL/Static Logic,” Logic,” Proc. IEEE Int. Conf. Computer Proc. IEEE Int. Conf. Computer DesignDesign, 2002., 2002.
R. Zimmermann and W. Fichtner, “Low-R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” Transistor Logic,” IEEE J. Solid State IEEE J. Solid State CircuitsCircuits, vol. 32, no. 7, pp. 1079-1090, July , vol. 32, no. 7, pp. 1079-1090, July 1997.1997.