visual system integrator_svi
TRANSCRIPT
System View Inc. Confidential
System View Inc.
System View Inc. Confidential
Visual System Integrator
System View Inc. Confidential
Problem Embedded SystemsGetting Increasingly Complex
Designs Span Multiple Chips (CPUs, GPUs, FPGAs, DSPs ….)
Difficult to Integrate, No VisibilityNo Universal Tool Exists for Integration
System View Inc. Confidential
Rapid, visual application development:• Describe Hardware platform.• Develop Application
(Import C/C++ blocks connect them)
• Automatic code generation for the complete system(Software/Hardware projects, drivers, DMAs)
Solution: Visual System Integrator
Get unprecedented Transaction level visibility at runtime
Focus on your application, not the platform & firmware!
System View Inc. Confidential
DescribeHardware Platform(Import
Existing)
Visual System Integrator: Work Flow
Compile Platform
PlatformMeta data
Software ProjectsEclipse, Qt, VC++ ,
…
Import Platform
FPGAProjectsDevelop
ApplicationSystem
Compile Generate System
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• System Design Phase• Canvas #1: Define high level platform• Canvas #2: Connect high level functional blocks
• Implementation Phase• Develop block details & run functional verification• Optimize system performance by moving blocks to platform contexts
• SW – intra-block block communication: FIFO (Zero Copy)• SW-SW shared memory or TCP• SW-HW timed + driver/DMA• SW-Simulation timed + BFM• HW- HW : Aurora• HW-HW blocks communication (CDC, Arbitration, FIFOs with Backpressure, Width matching)• System IOs are defined but abstracted as “File I/O” for verification & implementation
• Debug functionality & profile performance with system level trace view
V S I : Design Life Cycle Support
System Design
UnitDesign
Code
Unit Test
System Testing
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Applications Supported
Industrial ControlTimer controlled blocks
Accelerator OffloadCompute offloaded to FPGA
High Speed I/O Processing with SoftwareNetwork Packet ProcessingHigh Speed Signal Processing
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Videos showing VSI in action Click on Image
<space> to play<space> to pause
: https://www.youtube.com/watch?v=39OQ3gSJUFw
Accelerator on Zynq platform
Inline Packet Processing – X86 connected to FPGA (PCI/e) : https://www.youtube.com/watch?v=9m0GiBvkioE
X86 and Two Virtex-7 FPGAs: https://www.youtube.com/watch?v=gd7PZYIcFl0
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Performance: PCI/e Data Transfer Rates
0 50 100 150 200 250 3000
500
1000
1500
2000
2500
3000
3500
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 1 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0 50 100 150 200 250 3000
500
1000
1500
2000
2500
3000
3500
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 2 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0 50 100 150 200 250 3000
1000
2000
3000
4000
5000
6000
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 4 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0 50 100 150 200 250 3000
1000
2000
3000
4000
5000
6000
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 3 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
System View Inc. Confidential
Platform Definition
Technology
CompilePlatform
Platform.plat
Hardware_platform.tclHardware_platform.tcl
System Definition
CompileSystem System.cxx
Generate
System
Software_context.cxxSoftware_System.cxx
Hardware_System.cxxHardware_System.tcl
UserSW Lib*
VSIruntime
Compiler(g++)
executables
Vivado(IPI)
UserIP Lib*
XilinxIP Lib
Design/bitstream
Import platform
* HLS Blocks Included* External Tools
System View Inc. ConfidentialSystem View Inc. Confidential
SW HW Transport
/dev/vsi_...1
/dev/vsi_...2
/dev/vsi_...N
IP..1
IP..2
IP..N
sv_driver
Kernel
Vsi_common_intf
FPGA
TransportPCIeAXI
(Zynq)
Posix open
closereadwritelseekioctlmmap
System View Inc. Confidential
SW Simulator Transport
Remote Procedure Call
RPC - FileIO
Vsi - runtime
RPC to DPI ( C )
DPI AXI (BFM) (System Verilog)
VSIGenerated Design
• Remote Procedure Call (Transport)
• Direct Programming Interface (Simulator Interface)
System View Inc. Confidential
• MPSoC Support• Driver • Runtime
• Support added for Cortex-R5• Ported Pthread library to work with FreeRTOS & rpmsg• Created POSIX compliant “fileio” library for FreeRTOS
FreeRTOS
SW OpenAMP (shared Memory) Transport
RPMSG
Pthread Posix fileio
RPMSG
virtio virtio
RPMSG Driver
Vsi - runtime Vsi - runtime
Linux - StackR5 - Stack
Shared memory
openAMPopenAMP
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SW TCP/IP Transport
TCP/IP
VSI Runtime
Interconnect
VSI Runtime
Interconnect
o N-depth Chainable
o Provides Automatic Routing for
Trace/Performance Data
o Simple configuration
o Dedicated pipeline for each interface
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FPGA - 2FPGA - 1
HW Serdes (Aurora) Transport
Serdes
Design
Aurora
Design
Aurora
• Tunnel multiple connections over single Aurora link
• Will load balance balance between multiple Aurora
Links
• Links shared at a transaction level.
System View Inc. Confidential
AXI, S/MM [15]
AXI, S/MM [14]
AXI, S/MM [2]
AXI, S/MM [1]
AXI, S/MM [0]
Hardware Trace Module
